MAX6960AMH+-MAX6960AMH+D-MAX6960ATH+ Fast Delivery |IC PHOENIX CO.,LIMITED

MAX6960AMH+ ,4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers MAX6960–MAX69634-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers
MAX6960AMH+D ,4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED DriversELECTRICAL CHARACTERISTICS(V+ = 2.7V to 3.6V, T = T to T , typical values at V+ = 3.3V, T = +25°C, ..
MAX6960ATH+ ,4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED DriversFeaturesThe MAX6960–MAX6963 are compact cathode-row dis-♦ 2.7V to 3.6V Operationplay drivers that i ..
MAX6960EVCMODU ,Evaluation Kit/Evaluation System for the MAX6960features.♦ Fully Assembled and TestedThe MAX6960 evaluation system (EV system) consists♦ EV System ..
MAX6964AEG+ ,17-Output LED Driver/GPO with Intensity Control and Hot-Insertion ProtectionFeatures2♦ 400kbps, 2-Wire Serial Interface, 5.5V TolerantThe MAX6964 I C-compatible serial interfa ..
MAX6964ATG ,17- OUTPUT LED DRIVER/GPOMAX696419-3179; Rev 0; 1/0417- LED/GPO____________ ____________TM2MAX6964 I C♦ 400kbps, 2- , 5.5V 1 ..
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB40166 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..
MB40176 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..
MB40176 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..

MAX6960AMH+-MAX6960AMH+D-MAX6960ATH+
4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
General Description
The MAX6960–MAX6963are compact cathode-row dis-
play drivers that interface microprocessors to 8 x 8 dot-
matrix red, green, and yellow (R,G,Y) LED displays
through a high-speed 4-wire serial interface.
The MAX6960–MAX6963drive two monocolor 8 x 8
matrix displays, or a single RGY 8 x 8 matrix display with
no external components. The driver can also be used
with external pass transistors to control red, green, blue
(RGB) and other displays at higher currents and voltages.
The MAX6960–MAX6963 feature open- and short-circuit
LED detection, and provide both analog and digital tile
segment current calibration to allow 8 x 8 displays from
different batches to be compensated or color matched.
A local 3-wire bus synchronizes multiple interconnected
MAX6960–MAX6963s and automatically allocates memory
map addresses to suit the user’s display-panel
architecture.
The MAX6960–MAX6963s’ 4-wire interface connects mul-
tiple drivers, with display memory mapping shared and
allocated among the drivers. A single global write opera-
tion can send a command to all MAX6960s in a panel.
The MAX6963 drives monocolor displays with two-step
intensity control. The MAX6962 drives monocolor displays
with two-step or four-step intensity control. The MAX6961
drives monocolor or RGY displays with two-step intensity
control. The MAX6960 drives monocolor or RGY displays
with two-step or four-step intensity control.
Features2.7V to 3.6V OperationHigh-Speed 20MHz Serial InterfaceTrimmed 40mA or 20mA Peak Segment CurrentDirectly Drives Either Two Monocolor or One RGY
Cathode-Row 8 x 8 Matrix DisplaysAnalog Digit-by-Digit Segment Current CalibrationDigital Digit-by-Digit Segment Current Calibration256-Step Panel Intensity Control (All Drivers)Four Steps per Color Pixel-Level Intensity ControlOpen/Short LED DetectionBurst White to Display Memory PlanesGlobal Command Access All DevicesCan Control RGB Panels or Higher
Current/Voltage Panels with External Pass
TransistorsMultiple Display Data Planes Ease AnimationAutomatic Plane Switching from 63 Planes per
Second to One Plane Every 63s, with InterruptSlew-Rate-Limited Segment Drivers for Lower EMIDriver Switching Timing Can Be Spread Between
Multiple Drivers to Flatten Power-Supply Peak
DemandLow-Power Shutdown with Full Data Retention-40°C to +125°C Temperature Range
Ordering Information
PARTTEMP RANGEPIN-PACKAGEAX6960ATH -40°C to +125°C44 TQFN - E P *A X6 9 6 1AM H-40°C to +125°C44 MQFPAX6961ATH -40°C to +125°C44 TQFN - E P *A X6 9 6 2AM H-40°C to +125°C44 MQFPAX6962ATH -40°C to +125°C44 TQFN - E P *A X6 9 6 3AM H-40°C to +125°C44 MQFPAX6963ATH -40°C to +125°C44 TQFN - E P *
COL13
COL12
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL41314151617181920212243424140393837363534
GNDOSC
DIN
DOUT
CLKRST
COL1COL2COL3
GNDRISET1RISET0ADDCLKADDINADDOUTV+COL16COL15COL14V+
MQFP
MAX6960-MAX6963
TOP VIEW
Pin Configurations
Applications
Message Boards Industrial Controls
Gaming Machines Audio/Video Equipment
*EP = Exposed pad.
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = 2.7V to 3.6V, TA= TMINto TMAX, typical values at V+ = 3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltage with respect to GND.)
V+.............................................................................-0.3V to +4V
All Other Pins................................................-0.3V to (V+ + 0.3V)
ROW1–ROW8 Sink Current ..............................................750mA
COL1–COL16 Source Current ...........................................48mA
Continuous Power Dissipation (TA= +70°C)
44-Pin MQFP
(derate 12.7 mW/°C over +70°C)...............................1012mW
44-Pin TQFN
(derate 27mW/°C over +70°C)...................................2162mW
Operating Temperature Range
(TMINto TMAX)..............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+240°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Supply VoltageV+2.73.6V
TA = +25°C250375
TA = TMIN to +85°C500Shutdown Supply CurrentISHDN
Shutdown mode, all
digital inputs at V+
or GNDTA = TMIN to TMAX600
TA = +25°C7.59
TA = TMIN to +85°C10Operating Supply CurrentI+
Intensity set to full,
no display load
connectedTA = TMIN to TMAX11
Master Clock FrequencyfOSC1.08.5MHz
Dead-Clock Protection
FrequencyfOSC5090.5200kHz
OSC High TimetCH40ns
OSC Low TimetCL40ns
TA = +25°C384042
TA = TMIN to +85°C3743
VLED = 2.3V, V+ =
3.15V to 3.6V,
current = highTA = TMIN to TMAX3744
TA = +25°C192021
TA = TMIN to +85°C18.521.5
Anode Column Source Current
COL1–COL16ISEG
VLED = 2.3V, V+ =
2.7V to 3.6V, current
= lowTA = TMIN to TMAX18.522.0
VLED = 2.3V, V+ = 3.15V to 3.6V,
current = high200Anode Column Source-Current
Temperature Variation
COL1–COL16
ITC
VLED = 2.2V, V+ = 2.7V to 3.3V,
current = low200
ppm/°C
Segment Current Slew Rate ΔISEG/ΔtTA = +25°C30mA/µs
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2.7V to 3.6V, TA= TMINto TMAX, typical values at V+ = 3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS AND OUTPUTS
Input Leakage Current
DIN, CLK, CS, OSC, ADDIN,
ADDCLK, RST
IIH, IIL-1005+100nA
Logic-High Input Voltage
DIN, CLK, CS, OSC, ADDIN,
ADDCLK, RST
VIHI0.7 xV
Logic-Low Input Voltage
DIN, CLK, CS, OSC, ADDIN,
ADDCLK, RST
VILO0.3 xV
DOUT Output Rise and Fall TimestFTDOCLOAD = 100pF10ns
DOUT Output High VoltageVOHDOISOURCE = 20mAV+ -
0.3V
DOUT Output Low VoltageVOLDOISINK = 20mA0.3V
ADDOUT Output High VoltageVOHADOISOURCE = 500µAV+ -
0.3V
ADDOUT Output Low VoltageVOLADOISINK = 500µA0.3V
ADDCLK Output High VoltageVOHACKISOURCE = 2.5mAV+ -
0.3V
ADDCLK Output Low VoltageVOLACKISINK = 2.5mA0.3V
TIMING CHARACTERISTICS
CLK Clock PeriodtCP50ns
CLK Pulse-Width HightCH22ns
CLK Pulse-Width LowtCL22ns
CS Fall to CLK Rise Setup TimetCSS12.5ns
CLK Rise to CS Rise Hold TimetCSH0ns
DIN Setup TimetDS12.5ns
DIN Hold TimetDH10ns
Output Data Propagation DelaytDO22ns
Minimum CS Pulse HightCSW25ns
Note 1:All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
OPERATING SUPPLY CURRENT
vs. TEMPERATURE
MAX6960 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)5926-7
3.6V
3.3V
2.7V
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX6960 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)5926-7
3.6V
3.3V
2.7V
DEAD-CLOCK OSCILLATOR
vs. SUPPLY VOLTAGE
MAX6960 toc03
SUPPLY VOLTAGE (V)
DEAD-CLOCK OSCILLATOR
+25°C
-40°C
+125°C
PEAK-OUTPUT SOURCE CURRENT
vs. SUPPLY VOLTAGE (HIGH-CURRENT MODE)
MAX6960 toc04
SUPPLY VOLTAGE (V)
PEAK-OUTPUT CURRENT (mA)
2.3V LED
PEAK-OUTPUT SOURCE CURRENT
vs.SUPPLY VOLTAGE (LOW-CURRENT MODE)
MAX6960 toc05
SUPPLY VOLTAGE (V)
PEAK-OUTPUT CURRENT (mA)
2.2V LED
PEAK-OUTPUT SOURCE CURRENT
vs. TEMPERATURE (HIGH-CURRENT MODE)
MAX6960 toc06
TEMPERATURE (°C)
PEAK-OUTPUT CURRENT (mA)5926-7
2.3V LED
3.6V
3.3V
3.15V
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Typical Operating Characteristics
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Pin Description
PIN
MQFPTQFNNAMEFUNCTION
1, 6, 11,
12, 44
1, 6, 11,
12, 44GNDGround
2–5, 7–102–5, 7–10ROW1–ROW8LE D C athod e D r i ver s. ROW 1 to RO W 8 outp uts si nk cur r ent fr om the d i sp l ay' s cathod e r ow s.13OSCMultiplex Clock Input. Drive OSC with a 1MHz to 8.5MHz CMOS clock.14CSChip-Select Input. Serial data is loaded into the shift register when CS is low. Data is
loaded into the data latch on CS's rising edge.15DINSerial-Data Input. Data from DIN loads into the internal shift register on CLK's rising edge.16DOUTSerial-Data Output. The output is tri-state.17CLKSerial-Clock Input. On CLK's rising edge data shifts into the internal shift register.18RSTReset Input. Hold RST low until at least 50ms after all interconnected MAX6960s are
powered up.
19, 20,
21,
23–27,
29–33,
35, 36,
19, 20,
21,
23–27,
29–33,
35, 36,
COL1–COL16LED Anode Drivers. COL1 to COL16 outputs source current into the display's anode
columns.
22, 28,
34, 38
22, 28,
34, 38V+Positive Supply Voltage. Bypass V+ to GND with a single 47µF bulk capacitor per chip
plus a 0.1µF ceramic capacitor per V+.39ADDOUTAddress-Data Output. Connect ADDOUT to ADDIN of the next MAX6960. Use ADDOUT of
the last MAX6960 as a plane change interrupt output.40ADDINAddress-Data Input. For first MAX6960, connect ADDIN to V+. For other MAX6960s,
connect ADDIN to ADDOUT of the preceding MAX6960.41ADDCLKAddress-Clock Input/Output. Connect ADDCLK of all MAX6960 drivers together, ensuring
that only one MAX6960's ADDIN input is connected to V+.42RISET0
Digit 0 Current Setting. Connect RISET0 to GND to program all of digit 0's segment
currents to 40mA. Leave RISET0 open circuit to program all of digit 0's segment currents
to 20mA. Connect RISET0 to GND through a fixed or variable resistor to adjust all of digit
0's segment currents between 20mA and 40mA.43RISET1
Digit 1 Current Setting. Connect RISET1 to GND to program all of digit 1's segment
currents to 40mA. Leave RISET1 open circuit to program all of digit 1's segment currents
to 20mA. Connect RISET1 to GND through a fixed or variable resistor to adjust all of digit
1's segment currents between 20mA and 40mA.EPEPExposed Pad on Package Underside. Connect to GND.
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Quick-Start Guide
Selecting the Appropriate Driver
The MAX6960–MAX6963 matrix LED drivers are avail-
able in four versions, with different levels of functionality
(Table 1). The two-part ID bits in the fault and device ID
register (Table 32) identify the driver type to the inter-
face software. The ID bits may be of use if the same
panel software is used to drive more than one type of
display panel, because the software can automatically
detect the panel type.
This data sheet uses the generic name MAX6960 to refer
to the family of four parts MAX6960 through MAX6963,
The purpose of this quick-start guide is to provide an
overview of the capabilities of the MAX6960 so that the
driver can be easily evaluated for a particular applica-
tion, without fighting through a complex data sheet.
TerminologyPixel:One “point” on a display. Comprises one LED
for a monocolor display, two LEDs for an RGY dis-
play, and three LEDs for an RGB display.Monocolor: Display has only one color, typically red
for low-cost signs or orange for traffic signs. Varying
the current through the LED changes the intensity of
the red.
AVAILABLE FUNCTIONS
PARTRGB 2
BITS PER
PIXEL*
RGB
1 BIT PER
PIXEL*
RGY
2 BITS PER
PIXEL
RGY
1 BIT PER
PIXEL
MONOCOLOR
2 BITS PER
PIXEL
MONOCOLOR
1 BIT PER
PIXEL
REGISTER LIMITATIONS
MAX6960√√√√√√None.
MAX6961—√—√—√
PI bit (bit D7) in global panel
configuration register is fixed at 0
(Table 22).
MAX6962√√——√√
C bit (bit D6) in global panel
configuration register is fixed at 0
(Table 21).
MAX6963—√———√
C bit (bit D6) in global panel
configuration register is fixed at 0
(Table 21).
PI bit (bit D7) in global panel
configuration register is fixed at 0
(Table 22).
Table 1. Levels of Functionality
DISPLAY CONFIGURATIONMAXIMUM PIXEL COUNTEXAMPLE MAXIMUM PANEL (PIXELS)
Monocolor32,768256 x 128
RGY16,384256 x 64
RGB32,768 (3 buses required; see Figure 17)128 x 85
Table 2. Maximum Display Matrix on a Single 4-Wire Interface
256 DRIVERS ON 4-WIRE INTERFACE, 50 FRAMES PER SECOND UPDATE RATE
DISPLAY-MEMORY-ACCESS METHOD1-BIT-PER-PIXEL INTENSITY
CONTROL (Mbps)
2-BITS-PER-PIXEL INTENSITY
CONTROL (Mbps)
8-bit indirect display memory addressing1.643.28
24-bit direct display memory addressing4.929.83
Table 3. 4-Wire Interface Speed Requirements for Animation
*When operated per Figure 17.
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED DriversBicolor:Literally means two color, and usually refers
to LEDs built with two LED dice of different colors,
typically red and green or red and orange/yellow.Tricolor:Literally means three color, and can refer to
LEDs built with three LED dice of different colors, typi-
cally red, green, and blue. The term is also used to
refer to a display built with bicolor LEDs, because there
are three main colors available (red, green, yellow).RGY:Display uses one red LED (R) and one green
LED (G) per pixel. When both red and green LEDs
are lit, the resulting color is yellow (Y). Varying the
current through the LEDs changes the intensity of the
pixel and changes the color from red through shades
of orange and yellow to green.RGB:Display uses one red LED (R), one green LED
(G), and one blue LED (B) per pixel. Varying the cur-
rent through the LEDs changes the intensity of the
pixel and changes the color through many shades
limited by the current control resolution.
MAX6960 Applications
The MAX6960 is a multiplexed, constant-current LED
driver intended for high-efficiency indoor signage and
message boards.
The high efficiency arises because the driver operates
from a 3.3V nominal supply with minimal voltage head-
room required across the driver output stages. The
problem of removing heat from even a small display is
therefore minimized.
The maximum peak LED drive current is 40mA, which
when multiplexed eight ways, provides an average cur-
rent of 5mA per LED. This current drive is expected to
be adequate for indoor applications, but inadequate for
outdoor signs operating in direct sun.
The MAX6960 directly drives monocolor (typically red
or orange/yellow) or RGY (typically red/green or
red/yellow) graphic displays using LEDs with a forward
voltage drop up to 2.5V. Blue LEDs and some green
LEDs cannot be driven directly because of their high
forward voltage drop (around 3.5V to 4.5V). For these
displays, the MAX6960 can be used as a graphic con-
troller, just as it can be used for applications requiring
higher peak segment currents, and in RGB panels
needing a higher driver voltage for the blue LEDs. In
these cases, the MAX6960 can be used with external
drive transistors to control anode-row displays, with all
driver features including pixel-level intensity control still
available (see the Applications Informationsection and
Figure 17).
Display Intensity Control
Five levels of intensity control are provided:A 256-step PWM panel intensity adjustment sets all
MAX6960s simultaneously as a global panel bright-
ness control (Table 27). The 256-step resolution is
fine enough to allow fade-in/fade-out graphic effects,
as well as provide a means for compensating a
panel for background lighting.A 2-bits-per-pixel intensity control allows four bright-
ness levels to be set independently per pixel. The
pixel-level intensity control can be set to be either
arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4,
1/2, full) for full flexibility (Table 24), and allows four
colors to be displayed on monocolor panels, or 16
colors to be displayed on RGY panels, or 64 colors
to be displayed on RGB panels.The LED drive current can be selected between
either a 40mA peak per segment and a lower 20mA
peak current on a digit-by-digit basis using the
RISET0and RISET1pins. The lower (20mA) current
may be the better choice to drive high-efficiency dis-
plays, and this setting allows the MAX6960 to oper-
ate from a supply voltage as low as 2.7V.The LED drive current can be adjusted between
40mA and 20mA peak current on a digit-by-digit
basis using fixed or adjustable resistors connected
from the RISET0and RISET1pins to GND. These con-
trols enable analogrelative adjustments in digit
intensity, typically to calibrate digits from different
batches, or to color balance RGY displays.The digit intensity controls allow each digit’s operat-
ing current to be scaled down in 256 steps from the
global panel intensity adjustment. The effective oper-
ating current for each digit becomes n/256th of the
panel intensity value. These controls enable digital
relative adjustments in digit intensity in addition to
the analog approach outlined above.
Display Size Limitations
The maximum display size that can be handled by a
single 4-wire serial interface is given in Table 2, which
is for the maximum 256 interconnected MAX6960s.
Larger display panels can be designed using a sepa-
rate CSline for each group of (up to) 256 MAX6960s.
Each group would also have its own local 3-wire bus to
allocate the driver addresses. The 4-wire interface
speeds requirement when continuously updating dis-
play memory for high-speed animations is given in
Table 3.
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Software Control
The hardware features are designed to simplify the
software interface and eliminate software timing depen-
dencies:Two or four planes of display memory are stored,
allowing images to be preloaded into the MAX6960–
MAX6963 frame memory.Animation timing is built in, sequencing through the
two or four planes automatically. System software
has to update the upcoming plane(s) with new data
ahead of time, but do not be concerned about exact
timing. The frame rate is adjustable to as fast as 63
frames a second for animations, or to as slow as one
frame change every 63s for advertising sequencing.Multiple MAX6960s interconnect and share display
memory so that the software “sees” the display as
memory-mapped planes of contiguous RAM.Global commands that need to be received and
acted on by every MAX6960 in a panel do just that,
with one write.
Hardware Design
A MAX6960 normally drives an 8 x 16 LED matrix, com-
prising 8 cathode rows and 16 anode columns, or
8 anode rows and 16 cathode columns with external
drivers.
The MAX6960 standard wiring connection to either two
monocolor 8 x 8 digits, or to a single RGY 8 x 8 digit is
shown in Table 4. Figure 3 shows the display pin naming.
Figures 1 and 2 show example displays with the
MAX6960 drivers connecting to monocolor and RGY pan-
els. Figure 4 shows how the display memory maps to the
physical pixels on the display panel, provided that the
MAX6960 drivers are interconnected correctly in a raster-
like manner from top left of the panel to bottom right.
Detailed Description
Overview
The MAX6960 is an LED display driver capable of driving
either two monocolor 8 x 8 cathode-row matrix digits, or a
single RGY 8 x 8 cathode-row matrix digit. The architec-
ture of the driver is designed to allow a large graphic
display panel to be driven easily and intuitively by multi-
DRIVER PINS ROW1–ROW8DRIVER PINS COL1–COL8DRIVER PINS COL9–COL16
Monocolor digit 0 (red*)Digit 0 (red*) rows (cathodes)
R1 to R8
Digit 0 columns (anodes) C1 to—
Monocolor digit 1 (green*)Digit 1 (green*) rows
(cathodes) R1 to R8—Digit 1 columns (anodes) C1 to
RGY red/greenRed/green rows (cathodes) R1
to R8
Red columns (anodes) C1 to
Green columns (anodes) C1 to
Table 4. Standard Driver Connection to Monocolor and RGY 8 x 8 Displays
*Digit 0 of a monocolor display is called red, and digit 1 is called green in the data sheet.
RED
DRIVER0
REDRED
DRIVER1
REDRED
DRIVER2
REDRED
DRIVER3
REDRED
DRIVER4
REDRED
DRIVER5
RED
RED
DRIVER6
REDRED
DRIVER7
REDRED
DRIVER8
REDRED
DRIVER9
REDRED
DRIVER10
REDRED
DRIVER11
RED
RED
DRIVER12
REDRED
DRIVER13
REDRED
DRIVER14
REDRED
DRIVER15
REDRED
DRIVER16
REDRED
DRIVER17
RED
RED
DRIVER18
REDRED
DRIVER19
REDRED
DRIVER20
REDRED
DRIVER21
REDRED
DRIVER22
REDRED
DRIVER23
RED
Figure 1. Monocolor 1-Bit-per-Pixel, 96-Pixel x 32-Pixel Display Example
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
ple MAX6960s using 8 x 8 cathode-row matrix digits. The
MAX6960s in a display-driver design not only share the
host 4-wire interface, but they also share a local 3-wire
interface that is not connected to the host. The local 3-
wire interface works with the user’s driver settings to con-
figure all the MAX6960s to appear to the host interface as
one contiguous memory-mapped driver.
The pixel level-intensity control uses frame modulation.
Pixels are enabled and disabled on a frame-by-frame
basis over a 12-frame super frame (Table 5). The effec-
tive pixel frame duty cycle within a super frame sets each
pixel’s effective intensity. The 12-frame period of a super
frame allows arithmetic and geometric intensity scales to
be mixed on the same driver. This allows the user to set
up an RGY display with a different color scale for red and
RED
DRIVER0
GREENGREENGREENGREENGREENGREEN
GREENGREENGREENGREENGREENGREEN
GREENGREENGREENGREENGREENGREEN
GREENGREENGREENGREENGREENGREEN
RED
DRIVER1
RED
DRIVER2
RED
DRIVER3
RED
DRIVER4
RED
DRIVER5
RED
DRIVER6
RED
DRIVER7
RED
DRIVER8
RED
DRIVER9
RED
DRIVER10
RED
DRIVER11
RED
DRIVER12
RED
DRIVER13
RED
DRIVER14
RED
DRIVER15
RED
DRIVER16
RED
DRIVER17
RED
DRIVER18
RED
DRIVER19
RED
DRIVER20
RED
DRIVER21
RED
DRIVER22
RED
DRIVER23
Figure 2. RGY 1-Bit-per-Pixel 48-Pixel x 32-Pixel Display Example
COLUMN 1COLUMN 2COLUMN 3COLUMN 4COLUMN 5COLUMN 6COLUMN 7COLUMN 8
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
ROW 8
MONOCOLOR
COLUMN 1 (RED)
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
ROW 8
RGY
COLUMN 9 (GREEN)
Figure 3. 8 x 8 Matrix Pin Assignment
FIRST DISPLAY PIXEL
MAPS TO FIRST PLANE
LAST DISPLAY PIXEL
MAPS TO LAST PLANE
MEMORY LOCATION
Figure 4. How Plane Memory Across Multiple
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
store the display images. A memory plane is the exact
amount of memory required to store the display image.
The memory plane architecture allows one plane to be
used to refresh the display, while at least one other plane
is available to build up the next image. The global plane
counter register (Table 30) allows the plane used to
refresh the display to be selected either directly on com-
mand, or automatically under MAX6960 control.
Automatic plane switching can be set from 63 plane
changes a second to one plane change every 63s.
Display Memory Addressing
The MAX6960 contains 64 bytes of display mapping
memory. This display memory provides four memory
planes (of 16 bytes) when 1-bit-per-pixel intensity con-
trol is selected, or two memory planes (of 32 bytes)
when 2-bits-per-pixel intensity control is used (Table 6).
The 64 bytes of display memory in a MAX6960 could
be accessed with 6 bits of addressing on a driver-by-
driver basis.
address map encompasses up to 256 MAX6960 dri-
vers, all connected to the host through a common 4-
wire interface, and also interconnected through a local
3-wire interface. The purpose of the 3-wire interface is
to actively segment the 14-bit address space among
the (up to) 256 MAX6960s.
The total display memory is already partitioned among
these MAX6960 drivers in a register format. The
MAX6960s repartition these registers to appear as con-
tiguous planes of display memory, organized by color
(red, then green) and then into planes (P0 to P4)
(Table 6).
Register Addressing Modes
The MAX6960 accepts 8-bit, 16-bit, and 24-bit trans-
missions. All MAX6960s sharing an interface receive
and decode all these transmissions, but the content of
a transmission determines which MAX6960s store and
use a particular transmission, and which discard it
(Table 7).
PATTERN OF MULTIPLEX CYCLES FOR WHICH A PIXEL IS ENABLED
PIXEL
GRADUATIONBITBIT
PIXEL
INTENSITY
SETTING01234567891011
Both11Full111111111111
Arithmetic102/3101101101101
Geometric101/2101010101010
Arithmetic011/3010010010010
Geometric011/4010001000100
Both00Off000000000000
Table 5. Frame Modulation with Pixel Intensity
GLOBAL PANEL CONFIGURATION
REGISTER
PLANES/INTENSITY
(PI BIT)
COLOR
(C BIT)
PIXEL-LEVEL
INTENSITY
CONTROL
DISPLAY TYPEDISPLAY MAPPING
ADDRESSES PER PLANE
DISPLAY
PLANES
AVAILABLE01 bit per pixelMonocolor16 red contiguous411 bit per pixelRGY8 red contiguous,
8 green contiguous402 bits per pixelMonocolor16 red contiguous,
16 red contiguous212 bits per pixelRGY
16 red
(2 noncontiguous groups of 8),
16 green
(2 noncontiguous groups of 8)
Table 6. Panel Configuration
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
8-Bit Transmissions
Eight-bit transmissions are write-only, data-only
accesses that write data to the display memory indi-
rected by the global display indirect address register
(Figure 6). The global display indirect address register
autoincrements after the write access. Eight-bit trans-
missions provide the quickest method of updating a
plane of display memory of the MAX6960. It is the most
suitable display update method if the host system
builds an image in local memory, and then dumps the
image into a display plane of the MAX6960.
16-Bit Transmissions
Sixteen-bit transmissions are read/write, command-
and-data accesses to the MAX6960’s configuration
registers (Figure 7). A write can generally be global
data) or specific (updates just the MAX6960 indirected
by the global driver indirect address register). Note:
The global driver indirect address register selects a
specific MAX6960. This is not the same as the glob-
al display indirect address register, which points to
display memory that could be in any MAX6960. A
16-bit read is always indirected through the global dri-
ver indirect address register to select only one
MAX6960 to respond. When a read or write is indirect-
ed through the global driver indirect address register,
the 16-bit command can choose whether the global dri-
ver indirect address is autoincremented after the com-
mand has been executed. This allows the host to set up
one or more registers in consecutive MAX6960s with
the display indirect address, autoincrementing only
8-, 16-, OR 24-BIT DATA PACKET SENT TO MAX6960
DATA FORMAT
D23D22D21D20D19D18D17D16D15D14D13D12D11D10D8D7D6D5D4D3D2D1D0
8-bit indirect display
memory addressing.
Address is global display
indirect address (14 bits)
stored as {MSB, LSB} in
{register 0x0A, register
0x09}.8 bits of display memory
16-bit device addressing.—R/WAIL/G04-bit
address8 bits of driver register data
Factory reserved; do not
write to this address.—1—
24-bit direct display
memory addressing
(monocolor 1 bit per
pixel).
R/WXPlanes
0, 1, 2, 3
12-bit addressing across 256 drivers,
4096 x 8 red pixels
8 bits of display memory
(1 bit per pixel)
24-bit direct display
memory addressing
(RGY 1 bit per pixel).
R/WXPlanes
0, 1, 2, 3
12-bit addressing across 256 drivers,
2048 x 8 red pixels, and
2048 x 8 green pixels
8 bits of display memory
(1 bit per pixel)
24-bit direct display
memory addressing
(monocolor 2 bits per
pixel).
R/WXPlanes
0, 1
13-bit addressing across 256 drivers,
4096 x 4 red pixels
8 bits of display memory
(2 bits per pixel)
24-bit direct display
memory addressing
(RGY 2 bits per pixel).
R/WXPlanes
0, 1
13-bit addressing across 256 drivers,
4096 x 4 red pixels, and
4096 x 4 green pixels
8 bits of display memory
(2 bits per pixel)
Table 7. Register Addressing Modes
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
24-Bit Transmissions
Twenty-four-bit transmissions are read/write, address-
and-data accesses to the MAX6960’s display memory
(Figure 8). This is direct access to display memory
because the memory address is included in the 24-bit
transmission, compared with an 8-bit transmission,
which uses the memory address stored in the global
display indirect address register. Twenty-four-bit trans-
missions provide the random-access method of updat-
ing a plane of display memory of the MAX6960. It is the
most suitable display update method if the host system
builds an image directly in a display memory plane,
rather than in host local memory.
Host 4-Wire Serial Interface
Serial Addressing
The MAX6960 communicates to the host through a 4-
wire serial interface. The interface has three inputs:
clock (CLK), chip select (CS), and data in (DIN), and
one output, data out (DOUT). CSmust be low to clock
data into the device, and DIN must be stable when
sampled on the rising edge of CLK. DOUT is used for
read access, and is stable on the rising edge of CLK.
DOUT is high impedance except during MAX6960 read
accesses. Multiple MAX6960s may be connected to the
same 4-wire interface, with all devices connected to all
four interface lines in parallel. The normal limit of paral-
leled MAX6960s is 256, because that is the intercon-
nection limit for the 3-wire interface and associated
device addressing. The Applications Information sec-
tion discusses some practical issues raised by driving
many devices in parallel from the same interface.
The serial interface responds to only 8-bit, 16-bit, and
24-bit commands (Table 7).
The MAX6960 ignores any transmission that is not
exactly 8 bits, 16 bits, or 24 bits between the falling
and subsequent rising edge of CS.
Control and Operation Using the 4-Wire Interface
Controlling the MAX6960 requires sending an 8-bit, 16-
bit, or 24-bit word. The last byte, D7 through D0, is
always the data byte. Eight-bit accesses are write-only
accesses; 16-bit or 24-bit accesses are read or write
accesses, as determined by the MSB of the transmis-
sion, which is set for a read access; clear for a write. A
16-bit or 24-bit read involves transmitting 16 or 24 bits
to DIN, taking CShigh, and then reading back 8 bits
from DOUT. Only one MAX6960’s DOUT is enabled
from tri-state for readback. The selected MAX6960’s
DOUT normally returns to tri-state after the 8th falling
edge of CLK. However if CSfalls during the read
before the 8th falling edge of CLK, then the readback is
terminated and the selected MAX6960’s DOUT returns
to tri-state.
If a number of bits other than exactly 8 bits, 16 bits, or
24 bits are clocked into the MAX6960 between takinglow and taking CShigh again, then that transmis-
sion is ignored.
Writing Device Registers
The MAX6960 is written to using the following
sequence (Figures 3, 4, and 5):Take CLK low.Take CSlow.For an 8-bit transmission:
Clock 8 bits of data into DIN, D7 first to D0 last,
observing the setup and hold times.
For a 16-bit transmission:Dn-1
tCSS
tDStDH
tCLtCHD0
tCPtCSH
tCSW
tDO
CLK
DIN
DOUTD7D6D1D0
tDO
tDO
Figure 5. Timing Diagram
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED DriversD6D5D4D3D2D1D0
CLK
DIN
DOUT
TRI-STATE
Figure 6. 8-Bit Write to the MAX6960–MAX6963
D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
CLK
DINDOUT
D15
= 0
TRI-STATE
Figure 7. 16-Bit Write to the MAX6960–MAX6963
D22D21D20D19D18D7D6D5D4D3D2D1D0
CLK
DIN
DOUT
D23= 0
TRI-STATE.
D14D13D12D11D10D9D8D16D15D17
Figure 8. 24-Bit Write to the MAX6960–MAX6963
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
observing the setup and hold times. Bit D15 is low,
indicating a write command.
For a 24-bit transmission:
Clock 24 bits of data into DIN, D23 first to D0 last,
observing the setup and hold times. Bit D23 is low,
indicating a write command.Take CShigh (while CLK is still high after clocking
in the last data bit).Take CLK low.
Reading Device Registers
Any register data within the MAX6960 may be read by
sending a logic-high to bit D15. The sequence is:Take CLK low.Take CSlow.For a 16-bit transmission:
Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is high,
indicating a read command. Bits D7 to D0 are
dummy bits, and are discarded by the MAX6960.
For a 24-bit transmission:Clock 24 bits of data into
hold times. Bit D23 is high, indicating a read com-
mand. Bits D7 to D0 are dummy bits, and are dis-
carded by the MAX6960.Take CShigh (while CLK is still high after clocking
in the last data bit).Take CLK low.The selected MAX6960’s DOUT is enabled from tri-
state for read back.Clock 8 bits of data from DOUT, D7 first to D0 last,
observing the setup and hold times.Take CLK low after the final (8th) data bit.
The selected MAX6960’s DOUT returns to tri-state.
Figure 10 shows a read operation when 24 bits are
transmitted and 8 bits are read back.
Local 3-Wire Serial Interface
The MAX6960 uses a 3-wire interface to bus together
up to 256 MAX6960s. The 3-wire bus enables each
device to calculate its own unique driver address
(0 to 255), and reconfigure its display memory. The
ADDOUT output also provides an interrupt at every
page change, when the plane counter is configured toD6D5D4D3D2D1
CLK
DIN
DOUT
D15
= 1
TRI-STATE
D14D13D12D11D10D9D8D0D6D5D4D3D2D1D0
Figure 9. 16-Bit Read from the MAX6960–MAX6963
D22D21D20D19D18D7D6D5D4D3D2D1
CLK
DIN
DOUT
D23
= 1
TRI-STATE
D14D13D12D11D10D9D8D16D15D17D0D6D5D4D3D2D1D0
Figure 10. 24-Bit Read from the MAX6960–MAX6963
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
3-Wire Interface Data Lines
(ADDOUT and ADDIN)
One MAX6960 is designated the master device, and this
is allocated driver address 0. The master’s ADDIN pin is
connected to V+, identifying it as the first device. This
first MAX6960 should be the driver for the top-left pix-
els of the display panel. The master’s
ADDOUT pin is connected to the second MAX6960’s
ADDIN pin, and that MAX6960’s ADDOUT pin is connect-
ed to the third MAX6960’s ADDIN, and so on up to 256
MAX6960s. The last MAX6960’s ADDOUT pin is left open
circuit. The last MAX6960 should be the driver for the
bottom-right pixels of the display panel. The ADDOUT
is initialized low at the start of a 3-wire interface configura-
tion operation, and goes high (N + 1.5) ADDCLK periods
later, where n is the driver address of the MAX6960 (0 to
255). See Figures 1 and 2 for connection examples.
3-Wire Interface Clock (ADDCLK)
The ADDCLK pins for all MAX6960s are all connected
together. ADDCLK data rate is determined by OSC / 4,
nominally 1.048576 MHz. The ADDCLK pin for the master
MAX6960 (driver address 0) is always an output, and all
the other ADDCLKs are always inputs. ADDCLK is active
for exactly 256 clock cycles when a panel configuration is
being performed (on power-up reset, and after a write to
the global panel configuration register).
Use of ADDOUT as Plane Change Interrupt
(IRQ)
When the plane counter is configured to automatic mode
(bit 6 of the global plane counter register is set) (Table
30), ADDOUT pulses low for a time of 512/OSC (nominally
122µs) at the start of every automatic plane change. This
signal can be used as an interrupt output from the display
panel to the host to flag that the previous display plane is
now unused and can be written with a new image.
Multiplex Clock
The OSC input for all MAX6960s sharing a 3-wire interface
bus (but not necessarily a 4-wire interface bus) should be
driven by a common CMOS-level clock ranging between
1MHz and 8.5MHz. It is usually necessary to use an exter-
nal clock tree to fan out multiple clock drives when larger
numbers of MAX6960s are used because of the capaci-
tive loads. For example, each one of the eight outputs of a
standard 74HC541 octal buffer could drive 8 to 32
MAX6960 OSC inputs, depending on the layout used.
The recommended setting for OSC is 4.194303MHz. This
frequency sets the slow global plane counter resolution to
1s, and the fast global plane counter resolution to 1Hz.
COMMAND ADDRESSREGISTER
D15D14D13D12D11D10D9D8
HEX CODE
Driver Address (read only)XX00000x00
Pixel Intensity ScaleX00010x01
Panel IntensityX00100x02
Digit 0 IntensityX00110x03
Digit 1 IntensityX01000x04
FaultX01010x05X01100x06
Autoincrement
Local/Global01110x07
Global Driver Indirect Address*XXX10000x08
Global Display Indirect Address LSB*XXX10010x09
Global Display Indirect AddressXXX10100x0A
Global Plane Counter*XXX10110x0B
Global Clear Planes*XXX11000x0C
Global Panel Configuration*XXX11010x0D
Global Driver Devices*
R/WXX11100x0E
Global Driver Rows*XXX11110x0F
Table 8. Register Address Map
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
Global and Local Register
Addressing
The register map (Table 8) contains three local regis-
ters and eight global registers. Global registers are
always written to in all MAX6960s (on the same 4-wire
interface) at the same time, using a 16-bit transmission.
A read from a global register also always results in a
read from driver address 0. The global nature of these
registers ensures that all drivers work together, and
there is no chance of a software miss-send causing, for
example, multiple MAX6960s to try to transmit on the 4-
wire DOUT line at the same time.
ual basis (updates just the MAX6960 indirected by the
global driver indirect address register), or on a global
basis (updates all MAX6960s), according to the status
of the local/global bit (Table 9). The local/global bit is
ignored during a 16-bit read transmission, and the
MAX6960 pointed to by the global driver indirect
address register is read.
Register Address Autoincrementing
When a read or write is indirected through the global dri-
ver indirect address register, the 16-bit command can
choose whether the global driver indirect address is
autoincremented after the command has been executed.
COMMAND ADDRESSREGISTER
ADDRESS
CODE
(HEX)D15D14D13D12D11D10D9D8
LOCAL: Only the MAX6960 indirected by driver
indirect address is written.0X0XXXXX
GLOBAL: All MAX6960s are written with the same
data.0X1XXXXX
LOCAL: The MAX6960 indirected by driver indirect
address responds.1X0XXXXX
GLOBAL: The MAX6960 configured to address 0x00
responds.
0x00 to
0x071XXXXX
GLOBAL: All MAX6960s are written with the same
data.0XXXXXXX
GLOBAL: The MAX6960 configured to address 0x00
responds.
0x08 to
0x0F1XXXXXXX
Table 9. Register Address Local/Global Control Bit Format
COMMAND ADDRESSREGISTER
ADDRESS
CODE
(HEX)D15D14D13D12D11D10D9D8
Driver indirect address is not changedX0XXXXXX
Driver indirect address is incremented after read/write
0x00 to
0x07X1XXXXXX
Driver indirect address is not changed0x08 toXXXXXXXX
Table 10. Register Address Autoincrement Control Bit Format
REGISTER DATAREGISTER
ADDRESS
CODE
(HEX)D7D6D5D4D3D2D1D0
Driver address0x00MSB8-bit driver address 0x00 to 0xFFLSB
Table 11. Driver Address Register Format
MAX6960–MAX6963
4-Wire Serially Interfaced
8 x 8 Matrix Graphic LED Drivers
This allows the host to set up one or more registers in
consecutive MAX6960s with the display indirect address,
autoincrementing only when required (Table 10).
Driver Address Register
Reading the driver address register (Table 11) returns
the driver address that has been assigned to a particu-
lar MAX6960. The order of the driver addresses is
determined purely by the order that the 3-wire interface
is daisy-chained through multiple MAX6960s. The reg-
ister is used to detect the presence of a MAX6960 at an
address, and a binary search on the 256 possible
addresses can be used to determine the size of an
array of MAX6960s.
REGISTER DATAREGISTERADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0
Global driver devices0x0EMS8-bit global driver devices 0x00 to 0xFFLSB
Table 13. Global Driver Devices Format
REGISTER DATAREGISTERADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0
Global driver rows0x0FMSB8-bit global driver rows 0x00 to 0xFFLSB
Table 14. Global Driver Rows Format
REGISTER DATAREGISTER FUNCTIONPOWER-UP CONDITIONADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0
Driver address (read only)Address 00x0000000000
Pixel intensity scaleArithmetic for red and green0x01XXXXXX00
Panel intensity128/256 intensity0x0210000000
Digit 0 intensityFull 255/2560x0311111111
Digit 1 intensityFull 255/2560x0411111111
FaultNo faults0x050XXXXX00
Global driver indirect addressAddress 0x000x0800000000
Global display indirect address
LSB0x0900000000
Global display indirect address
MSB
Address 0x0000
0x0AXX000000
Global plane counterManual selection to plane 00x0B00000000
Global panel configuration
Shutdown mode,
ripple sync enabled,
mux flip enabled,
color is mono,
4 display planes/1 bit per
pixel
0x0D0011XXX0
Global driver devices256 drivers interconnected0x0E11111111
Global driver rows256 drivers in a row0x0F11111111
Table 12. Power-Up Configuration
*When reading from the global registers, only the master MAX6960 (whose driver address is 0x00) responds.

Partno	Mfg	Dc	Qty	Available	Descript
MAX6960AMH+	N/A	N/a	2500	avai	4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers
MAX6960AMH+D \|MAX6960AMHD	MAXIM	N/a	2	avai	4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers
MAX6960ATH+	N/A	N/a	2500	avai	4-Wire Serially Interfaced 8 x 8 Matrix Graphic LED Drivers