MAX6955AAX+T ,2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key ScanElectrical Characteristics(Typical Operating Circuit, V+ = 2.7V to 5.5V, T = T to T , unless otherw ..
MAX6956AAI+ ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Display Driver and I/O ExpanderApplicationsTOP VIEWSet-Top Boxes Bar Graph DisplaysISET 1 28 V+Panel Meters Industrial Controllers ..
MAX6956AAX/V+T ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Display Driver and I/O ExpanderELECTRICAL CHARACTERISTICS(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T to T , unless otherw ..
MAX6956AAX+ ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Display Driver and I/O ExpanderMAX695619-2414; Rev 4; 6/102-Wire-Interfaced, 2.5V to 5.5V, 20-Port or28-Port LED Display Driver an ..
MAX6956ATL ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Display Driver and I/O ExpanderFeatures2The MAX6956 compact, serial-interfaced LED display 400kbps I C-Compatible Serial Interfac ..
MAX6956ATL ,2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or 28-Port LED Display Driver and I/O ExpanderApplicationsISET 1 28 V+Set-Top Boxes Bar Graph DisplaysGND 2 27 AD1Panel Meters Industrial Control ..
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB401 , 40 Amp Single Phase Bridge Rectifier 50 to 1000 Volts
MB40166 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..
MB40176 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..
MB40176 ,AD/DA CONVERTERFUJITSU SEMICONDUCTORDS04-28500-5EDATA SHEETASSPAD/DA CONVERTERMB40166/MB401761-CHANNEL 6-BIT AD/DA ..
MAX6955AAX+-MAX6955AAX+T
2-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key ScanEVALUATION KIT AVAILABLE
General DescriptionThe MAX6955 is a compact display driver that interfaces
microprocessors to a mix of 7-segment, 14-segment,
and 16-segment LED displays through an I2C-compati-
ble 2-wire serial interface. The MAX6955 drives up to 16
digits 7-segment, 8 digits 14-segment, 8 digits 16-seg-
ment, or 128 discrete LEDs, while functioning from a
supply voltage as low as 2.7V. The driver includes five
I/O expander or general-purpose I/O (GPIO) lines, some
or all of which can be configured as a key-switch reader.
The key-switch reader automatically scans and
debounces a matrix of up to 32 switches.
Included on chip are full 14- and 16-segment ASCII
104-character fonts, a hexadecimal font for 7-segment
displays, multiplex scan circuitry, anode and cathode
drivers, and static RAM that stores each digit. The max-
imum segment current for the display digits is set using
a single external resistor. Digit intensity can be inde-
pendently adjusted using the 16-step internal digital
brightness control. The MAX6955 includes a low-power
shutdown mode, a scan-limit register that allows the
user to display from 1 to 16 digits, segment blinking
(synchronized across multiple drivers, if desired), and a
test mode, which forces all LEDs on. The LED drivers
are slew-rate limited to reduce EMI.
For an SPI-compatible version, refer to the MAX6954
data sheet. An evaluation kit (EV kit) for the MAX6955 is
available.
ApplicationsSet-Top BoxesBar Graph Displays
Panel MetersAudio/Video Equipment
White Goods
Benefits and FeaturesSimplifies Driving 5 x 7 Matrix LED DisplaysDrives Common-Cathode Monocolor and Bicolor
LED DisplaysDrives Up to 16 Digits 7-Segment, 8 Digits 14-Segment,
8 Digits 16-Segment, 128 Discrete LEDs, or a
Combination of Digit Types2.7V to 5.5V Operation
Standard 2-Wire Interface Supports a Variety of
Microprocessor Architectures400kbps 2-Wire I2C-Compatible Interface
Integrated Flexibility Supports Different Application
RequirementsBuilt-In ASCII 104-Character Font for 14-Segment
and 16-Segment Digits and Hexadecimal Font for
7-Segment Digits 16-Step Digit-by-Digit Digital Brightness ControlDisplay Blanked on Power-UpAutomatic Blinking Control for Each Segment10µA (typ) Low-Power Shutdown (Data Retained)
Five GPIO Port Pins Can Be Configured as Key-Switch
Reader to Scan and Debounce Up to 32 Switches with
n-Key RolloverIRQ Output when a Key Input Is Debounced
Slew-Rate-Limited Segment Drivers for Lower EMI
36-Pin SSOP and 40-Pin DIP and TQFN Packages
Automotive Temperature Range Standard Covers
Usage in Harsh Environments
Ordering Information
PART TEMP RANGE PIN-PACKAGE MAX6955AAX+ -40°C to +125°C 36 SSOP
MAX6955ATL+ -40°C to +125°C 40 TQFN-EP*
Pin Configurations and Typical Operating Circuits appear
at end of data sheet.ISET
OSC
OSC_OUT
BLINK
SCL
AD0
AD1
SDA
2-WIRE SERIAL INTERFACE
RAM
BLINK
CONTROL
CONFIGURATION
REGISTER
CHARACTER
GENERATOR
ROM
CURRENT
SOURCE
DIVIDER/
COUNTER
NETWORK
DIGIT
MULTIPLEXER
PWM
BRIGHTNESS
CONTROL
GPIO
AND KEY-SCAN
CONTROL
LED
DRIVERS
O0 TO O18
P0 TO P4/IRQ
MAX6955
Functional Diagram*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with Respect to GND)
V+.........................................................................-0.3V to +6V
SCL, SDA, AD0, AD1 ...........................................-0.3V to +6V
All Other Pins............................................-0.3V to (V+ + 0.3V)
Current
O0–O7 Sink Current......................................................935mA
O0–O18 Source Current.................................................55mA
SCL, SDA, AD0, AD1, BLINK, OSC, OSC_OUT, ISET....20mA
P0, P1, P2, P3, P4/IRQ....................................................40mA
GND.....................................................................................1A
Continuous Power Dissipation (TA= +70°C)
36-Pin SSOP (derate at 11.8mW/°C above +70°C).....941mW
40-Pin TQFN (derate at 25.6mW/°C above +70°C)....2051.3mW
Operating Temperature Range
(TMINto TMAX)...............................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
DC Electrical Characteristics(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageV+2.75.5V
TA = +25°C1035
Shutdown Supply CurrentISHDN
Shutdown mode, all
digital inputs at V+
or GNDTA = TMIN to TMAX40
TA = +25°C2230
Operating Supply CurrentI+
All segments on, all
digits scanned,
intensity set to full,
internal oscillator, no
display or OSC_OUT
load connected
TA = TMIN to TMAX35
OSC = RC oscillator, RSET = 56kΩ,
CSET = 22pF, V+ = 3.3V4Master Clock FrequencyfOSC
OSC driven externally18
MHz
Dead Clock Protection FrequencyfOSC95kHz
OSC Internal/External Detection
ThresholdVOSC1.7V
OSC High TimetCH50ns
OSC Low TimetCL50ns
Slow Segment Blink PeriodfSLOWBLINK
OSC = RC oscillator, RSET = 56kΩ,
CSET = 22pF, V+ = 3.3V1s
Fast Segment Blink PeriodfFASTBLINKOSC = RC oscillator, RSET = 56kΩ,
CSET = 22pF, V+ = 3.3V0.5s
Fast or Slow Segment Blink Duty
Cycle49.550.5%
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
DC Electrical Characteristics (continued)(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVLED = 2.2V,
V+ = 3.3V
Segment Drive Source CurrentISEG
VLED = 2.2V,
V+ = 2.7V
TA = +25°C-32-40-48mA
Segment Current Slew Rate ΔISEG/ΔtTA = +25°C, V+ = 3.3V11mA/µs
Segment Drive Current Matching ΔISEGTA = +25°C, V+ = 3.3V5%
LOGIC INPUTS AND OUTPUTSInput High Voltage
SDA, SCL, AD0, AD1VIH0.7 xV
Input Low Voltage
SDA, SCL, AD0, AD1VIL0.3 xV
Input Leakage Current
SDA, SCL, AD0, AD1, OSC, P0,
P1, P2, P3, P4/IRQ
IIH, IIL-1+1µA
SDA Output Low VoltageVOLSDAISINK = 6mA0.4V
Port Logic-High Input Voltage
P0, P1, P2, P3, P4/IRQVIHP0.7 xV
Port Logic-Low Input Voltage
P0, P1, P2, P3, P4/IRQVILP0.3 xV
Port Hysteresis Voltage
P0, P1, P2, P3, P4/IRQ ΔVIP0.03 xV
Port Input Pullup Current from V+IIPUP0 to P3 configured as key-scan inputs,
V+ = 3.3V75µA
Port Output Low VoltageVOLPISINK = 8mA0.30.5V
Blink Output Low VoltageVOLBKISINK = 0.6mA0.10.3V
OSC_OUT Output High VoltageVOHOSCISOURCE = 1.6mAV+ -
0.4V
OSC_OUT Output Low VoltageVOLOSCISINK = 1.6mA0.4V
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Timing Characteristics(Typical Operating Circuit, V+ = 2.7V to 5.5V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICSSerial Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP
and a START ConditiontBUF1.3µs
Hold Time (Repeated) START
ConditiontHD, tSTA0.6µs
Repeated START Condition Setup
TimetSU, tSTA0.6µs
STOP Condition Setup TimetSU:STO0.6µs
Data Hold TimetHD, tDAT(Note 3)0.9µs
Data Setup TimetSU, tDAT100ns
SCL Clock Low PeriodtLOW1.3µs
SCL Clock High PeriodtHIGH0.6µs
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Notes 2, 4)20 +
0.1CB300ns
Fall Time of Both SDA and SCL
Signals, ReceivingtF(Notes 2, 4)20 +
0.1CB300ns
Fall Time of SDA TransmittingtF, tX(Notes 2, 5)20 +
0.1CB300ns
Pulse Width of Spike SuppressedtSP(Notes 2, 6)050ns
Capacitive Load for Each
Bus LineCB(Note 2)400pF
Note 1:All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:Guaranteed by design.
Note 3:A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL- of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4:CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 5:ISINK≤6mA. CB= total capacitance of one bus line in pF. tRand tFmeasured between 0.3V+ and 0.7V+.
Note 6:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATUREMAX6955 toc01
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (MHz)
RSET = 56kΩ
CSET = 22pF
SUPPLY VOLTAGE (V)
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX6955 toc02
OSCILLATOR FREQUENCY (MHz)3.8
RSET = 56kΩ
CSET = 22pF
100ns/div
OSC: 500mV/div
OSC_OUT: 2V/div
MAX6954 toc03
OSC
OSC_OUT
INTERNAL OSCILLATOR WAVEFORM
AT OSC AND OSC_OUT PINSRSET = 56kΩ
CSET = 22pF
DEAD CLOCK OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)
MAX6955 toc04
OSCILLATOR FREQUENCY (MHz)
RSET = 56kΩ
CSET = GND
CURRENT NORMALIZED TO 40mA0.94
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
MAX6955 toc05
VLED = 1.8V
1V/div
200μs/div
MAX6954 toc06
O18
WAVEFORM AT PINS O0 AND O18,
MAXIMUM INTENSITY
GPIO SINK CURRENT
vs. TEMPERATUREMAX
6955 toc07
TEMPERATURE (°C)
GPIO SINK CURRENT (mA)
VCC = 5.5V
VCC = 3.3V
VCC = 2.5V
OUTPUT = LOW
VPORT = 0.6V
PORT INPUT PULLUP CURRENT
vs. TEMPERATUREMAX6955 toc08
TEMPERATURE (°C)
KEY-SCAN SOURCE CURRENT (mA)
VCC = 5.5V
VCC = 3.3V
VCC = 2.5V
OUTPUT = HIGH
VPORT = 1.4V
400μs/div
KEY_A: 1V/div
MAX6954 toc09
KEY_A
IRQ
KEY-SCAN OPERATION
(KEY_A AND IRQ)
Typical Operating Characteristics(V+ = 3.3V, LED forward voltage = 2.4V, Typical Application Circuit, TA= +25°C, unless otherwise noted.)
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Detailed DescriptionThe MAX6955 is a serially interfaced display driver that
can drive up to 16 digits 7-segment, 8 digits 14-seg-
ment, 8 digits 16-segment, 128 discrete LEDs, or a
combination of these display types. Table 1 shows the
drive capability of the MAX6955 for monocolor and
bicolor displays.
The MAX6955 includes 104-character ASCII font maps
for 14-segment and 16-segment displays, as well as
the hexadecimal font map for 7-segment displays. The
characters follow the standard ASCII font, with the
addition of the following common symbols: £, €, ¥, °, µ,
±, ↑, and ↓. Seven bits represent the 104-character
font map; an 8th bit is used to select whether the deci-
mal point (DP) is lit. Seven-segment LED digits can be
controlled directly or use the hexadecimal font. Direct
segment control allows the MAX6955 to be used to
drive bar graphs and discrete LED indicators.
Tables 2, 3, and 4 list the connection schemes for 16-,
14-, and 7-segment digits, respectively. The letters in
Tables 2, 3, and 4 correspond to the segment labels
shown in Figure 1. (For applications that require mixed
display types, see Tables 38–41.)
Serial Interface
Serial AddressingThe MAX6955 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
Pin Description
PIN
SSOPTQFN-EPNAMEFUNCTION1, 2,
34, 35
36, 37,
33, 34P0–P3
General-Purpose I/O Ports (GPIOs). GPIO can be configured as logic inputs or open-drain
outputs. Enabling key scanning configures some or all ports P0–P3 as key-switch matrix inputs
with internal pullup (Key_A through Key_D).38AD0Address Input 0. Sets device slave address. Connect to GND, V+, SCL, or SDA to give four
logic combinations. See Table 5.39SDAI2C-Compatible Serial Data I/O40SCLI2C-Compatible Serial Clock Input1AD1Address Input 1. Sets device slave address. Connect to GND, V+, SCL, or SDA to give four
logic combinations. See Table 5.
7–15,
2–10,
21–30O0–O18
Digit/Segment Drivers. When acting as digit drivers, outputs O0 to O7 sink current from the
display common cathodes. When acting as segment drivers, O0 to O18 source current to the
display anodes. O0 to O18 are high impedance when not being used as digit or segment
drivers.
16, 1812, 13, 15GNDGround14ISETSegment Current Setting. Connect ISET to GND through series resistor RSET to set the peak
current.
19, 2116, 18, 19V+Positive Supply Voltage. Bypass V+ to GND with a 47µF bulk capacitor and a 0.1µF ceramic
capacitor.17OSCMultiplex Clock Input. To use internal oscillator, connect capacitor CSET from OSC to GND.
To use external clock, drive OSC with a 1MHz to 8MHz CMOS clock.31BLINKBlink Clock Output. Output is open drain.32OSC_OUTClock Output. OSC_OUT is a buffered clock output to allow easy blink synchronization of
multiple MAX6955s. Output is push-pull.35P4/IRQGeneral-Purpose I/O Port. Also functions as IRQ output when key scanning is enabled.11, 20N.C.Not Internally ConnectedEPExposed Paddle. Internally connected to GND. Connect to a large ground plane to improve
thermal performance.
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX6955, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX6955 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX6955 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX6955
7-bit slave address plus R/Wbit (Figure 4), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 3).
Start and Stop ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit TransferOne data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
AcknowledgeThe acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 6).
Thus, each byte transferred effectively requires 9 bits. The
master generates the 9th clock pulse, and the recipient
pulls down SDA during the acknowledge clock pulse, such
that the SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the
MAX6955, the MAX6955 generates the acknowledge bit
because the MAX6955 is the recipient. When the
MAX6955 is transmitting to the master, the master gener-
ates the acknowledge bit because the master is the recipi-
ent.
Slave AddressThe MAX6955 has a 7-bit-long slave address (Figure
4). The eighth bit following the 7-bit slave address is
the R/Wbit. It is low for a write command, high for a
read command.
The first 3 bits (MSBs) of the MAX6955 slave address
are always 110. Slave address bits A3, A2, A1, and A0
are selected by the address input pins AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX6955 has 16 possible slave
addresses (Table 5) and therefore a maximum of 16
DISPLAY TYPE
7 SEGMENT
(16-CHARACTER
HEXADECIMAL FONT)
14 SEGMENT/
16 SEGMENT
(104-CHARACTER ASCII FONT MAP)
DISCRETE LEDs
(DIRECT CONTROL)Monocolor168128
Bicolor8464
Table 1. MAX6955 Drive Capability1dp2dpg2
hj
dp dp1b1c2b2cg2
hj
Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Message Format for WritingA write to the MAX6955 comprises the transmission of
the MAX6955’s slave address with the R/Wbit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte, which deter-
mines which register of the MAX6955 is to be written by
the next byte, if received. If a STOP condition is detect-
ed after the command byte is received, then the
MAX6955 takes no further action (Figure 7) beyond
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX6955 selected by the command byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX6955 internal registers because the
command byte address generally autoincrements
(Table 6) (Figure 9).
DIGITO0O1O2O3O4O5O6O7O8O9O10O11O12O13O14O15O16O17O18CCO—a1a2bcd1d2efg1g2hijklmdp—CC1a1a2bcd1d2efg1g2hijklmdpa1a2CC2—bcd1d2efg1g2hijklmdpa1a2—CC3bcd1d2efg1g2hijklmdpa1a2bcCC4—d1d2efg1g2hijklmdpa1a2bc—CC5d1d2efg1g2hijklmdpa1a2bcd1d2CC6—efg1g2hijklmdpa1a2bcd1d2—CC7efg1g2hijklmdp
DIGITO0O1O2O3O4O5O6O7O8O9O10O11O12O13O14O15O16O17O18CCO—a—bcd—efg1g2hijklmdp—CC1a—bcd—efg1g2hijklmdpa—CC2—bcd—efg1g2hijklmdpa——CC3bcd—efg1g2hijklmdpa—bcCC4—d—efg1g2hijklmdpa—bc—CC5d—efg1g2hijklmdpa—bcd—CC6—efg1g2hijklmdpa—bcd——CC7efg1g2hijklmdp
Table 2. Connection Scheme for Eight 16-Segment Digits
Table 3. Connection Scheme for Eight 14-Segment Digits
DIGITO0O1O2O3O4O5O6O7O8O9O10O11O12O13O14O15O16O17O180, 0aCC0—1a—1b1c1d1dp1e1f1g2a2b2c2d2e2f2g2dp
1, 1a—CC11a—1b1c1d1dp1e1f1g2a2b2c2d2e2f2g2dp
2, 2a1a—CC2—1b1c1d1dp1e1f1g2a2b2c2d2e2f2g2dp
3, 3a1a——CC31b1c1d1dp1e1f1g2a2b2c2d2e2f2g2dp
4, 4a1a—1b1cCC4—1d1dp1e1f1g2a2b2c2d2e2f2g2dp
5, 5a1a—1b1c—CC51d1dp1e1f1g2a2b2c2d2e2f2g2dp
6, 6a1a—1b1c1d1dpCC6—1e1f1g2a2b2c2d2e2f2g2dp
7, 7a1a—1b1c1d1dp—CC71e1f1g2a2b2c2d2e2f2g2dp
Table 4. Connection Scheme for Sixteen 7-Segment Digits
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
SDA
START CONDITIONSTOP CONDITION
SCLP
SDA
SCL
MSBSTART10A3A2A1A0R/W
LSB
ACK
Figure 3. Start and Stop Conditions
Figure 4. Slave Address
SDA
tLOW
tBUFtSU, DATtSU, STA
tHD, STAtSU, STOtHD, DAT
tHIGHtF
SCL
START
CONDITION
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
tHD, STA
Figure 2. 2-Wire Serial Interface Timing Details
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Message Format for ReadingThe MAX6955 is read using the MAX6955’s internally
stored command byte as address pointer, the same
way the stored command byte is used as address
pointer for a write. The pointer generally autoincrements
after each data byte is read using the same rules as for
a write (Table 6). Thus, a read is initiated by first config-
uring the MAX6955’s command byte by performing a
write (Figure 7). The master can now read n consecu-
tive bytes from the MAX6955, with the first data byte
being read from the register addressed by the initial-
ized command byte (Figure 9). When performing read-
after-write verification, reset the command byte’s
address because the stored byte address generally is
autoincremented after the write (Table 6).
Operation with Multiple MastersIf the MAX6955 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6955
should use a repeated start between the write, which
sets the MAX6955’s address pointer, and the read(s)
that takes the data from the location(s). This is because
it is possible for master 2 to take over the bus after
master 1 has set up the MAX6955’s address pointer but
before master 1 has read the data. If master 2 subse-
quently changes the MAX6955’s address pointer, then
master 1’s delayed read may be from an unexpected
location.
Command Address AutoincrementingAddress autoincrementing allows the MAX6955 to be
configured with the shortest number of transmissions by
minimizing the number of times the command byte
needs to be sent. The command address or the font
pointer address stored in the MAX6955 generally incre-
ments after each data byte is written or read (Table 6).
To utilize the autoincrement read cycle feature, the mas-
ter clocks SCL after the first data byte is read, and the
MAX6955 continues sending data, incrementing the
pointer after each byte is sent. A not-acknowledge or
stop condition halts autoincrement.
Digit Type RegistersThe MAX6955 uses 32 digit registers to store the char-
acters that the user wishes to display. These digit regis-
ters are implemented with two planes, P0 and P1. Each
digit is represented by 2 bytes of memory, 1 byte in
plane P0 and the other in plane P1. The digit registers
are mapped so that a digit’s data can be updated in
plane P0, plane P1, or both planes at the same time
(Table 7).
If the blink function is disabled through the Blink Enable
Bit E (Table 20) in the configuration register, then the
digit register data in plane P0 is used to multiplex the
display. The digit register data in P1 is not used. If the
blink function is enabled, then the digit register data in
both plane P0 and plane P1 are alternately used to mul-
tiplex the display. Blinking is achieved by multiplexing
the LED display using data plane P0 and plane P1 on
alternate phases of the blink clock (Table 21).
COMMAND BYTE
ADDRESS RANGEAUTOINCREMENT BEHAVIORx0000000 to x0001100Command byte address autoincrements after byte read or written.
x0001101Factory reserved; do not write this register.
x0001111 to x1111110Command byte address autoincrements after byte read or written.
Table 5. MAX6955 Address Map
Table 6. Command Address Autoincrement Rules
PIN CONNECTION DEVICE ADDRESS
AD1AD0A6A5A4A3A2A1A0GNDGND1100000
GNDV+1100001
GNDSDA1100010
GNDSCL1100011GND1100100V+1100101SDA1100110SCL1100111
SDAGND1101000
SDAV+1101001
SDASDA1101010
SDASCL1101011
SCLGND1101100
SCLV+1101101
SCLSDA1101110
SCLSCL1101111
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
The data in the digit registers does not control the digit
segments directly for 14- and 16-segment displays.
Instead, the register data is used to address a charac-
ter generator that stores the data for the 14- and 16-
segment fonts (Tables 8 and 9). The lower 7 bits of the
digit data (D6 to D0) select the character from the font.
The most significant bit of the register data (D7) con-
trols the DP segment of the digits; it is set to 1 to light
DP, and to zero to leave DP unlit (Table 10).
For 7-segment displays, the digit plane data register
can be used to address a character generator, which
contains the data of a 16-character font containing the
hexadecimal font. The decode mode register can be
used to disable the character generator and allow the
segments to be controlled directly. Table 11 shows the
one-to-one pairing of each data bit to the appropriate
segment line in the digit plane data registers. The hexa-
decimal font is decoded according to Table 12.
The digit-type register configures the display driver for
various combinations of 14-segment digits, 16-segment
digits, and/or pairs, or 7-segment digits. The function of
this register is to select the appropriate font for each
digit and route the output of the font to the appropriate
MAX6955 driver output pins. The MAX6955 has four
digit drive slots. A slot can be filled with various combi-
nations of monocolor and bicolor 16-segment displays,
14-segment displays, or two 7-segment displays. Each
pair of bits in the register corresponds to one of the four
digit drive slots, as shown in Table 13. Each bit also cor-
responds to one of the eight common-cathode digit
drive outputs, CC0 to CC7. When using bicolor digits,
the anode connections for the two digits within a slot are
always the same. This means that a slot correctly drives
two monocolor or one bicolor 14- or 16-segment digit.
The digit type register can be written, but cannot be
read. Examples of configuration settings required for
some display digit combinations are shown in Table 14.
7-Segment Decode-Mode RegisterIn 7-segment mode, the hexadecimal font can be dis-
abled (Table 15). The decode-mode register selects
between hexadecimal code or direct control for each of
eight possible pairs of 7-segment digits. Each bit in the
register corresponds to one pair of digits. The digit
pairs are {digit 0, digit 0a} through {digit 7, digit 7a}.
Disabling decode mode allows direct control of the 16
LEDs of a dual 7-segment display. Direct control mode
can also be used to drive a matrix of 128 discrete LEDs.
A logic high selects hexadecimal decoding, while a
logic low bypasses the decoder. When direct control is
selected, the data bits D7 to D0 correspond to the seg-
ment lines of the MAX6955. Write x0010000 to blank all
Display Blink ModeThe display blinking facility, when enabled, makes the
driver flip automatically between displaying the digit
register data in planes P0 and P1. If the digit register
data for any digit is different in the two planes, then that
digit appears to flip between two characters. To make a
character appear to blink on or off, write the character
to one plane, and use the blank character (0x20) for the
other plane. Once blinking has been configured, it con-
tinues automatically without further intervention.
Blink SpeedThe blink speed is determined by the frequency of the
multiplex clock, OSC, and by the setting of the Blink
Rate Selection Bit B (Table 19) in the configuration reg-
ister. The Blink Rate Selection Bit B sets either fast or
slow blink speed for the whole display.
Initial Power-UpOn initial power-up, all control registers are reset, the
display is blanked, intensities are set to minimum, and
shutdown is enabled (Table 16).
Configuration RegisterThe configuration register is used to enter and exit shut-
down, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, select
between global or digit-by-digit control of intensity, and
reset the blink timing (Tables 17–20 and 22–25).
The configuration register contains 7 bits: S bit selects shutdown or normal operation
(read/write).B bit selects the blink rate (read/write).E bit globally enables or disables the blink function
(read/write).T bit resets the blink timing (data is not stored—tran-
sient bit).R bit globally clears the digit data for both planes P0
and P1 for ALL digits (data is not stored—transient bit).I bit selects between global or digit-by-digit control
of intensity (read/write).P bit returns the current phase of the blink timing
(read only—a write to this bit is ignored).
Character Generator Font MappingThe font is composed of 104 characters in ROM. The
lower 7 bits of the 8-bit digit register represent the char-
acter selection. The most significant bit, shown as x in
the ROM map of Tables 8 and 9, is 1 to light the DP
segment and zero to leave the DP segment unlit.
The character map follows the standard ASCII font for
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
range. The first 16 characters of the 16-segment ROM
map cover 7-segment displays. These 16 characters
are numeric 0 to 9 and characters A to F (i.e., the hexa-
decimal set).
Multiplex Clock and Blink TimingThe OSC pin can be fitted with capacitor CSETto GND to
use the internal RC multiplex oscillator, or driven by an
external clock to set the multiplex clock frequency and
blink rate. The multiplex clock frequency determines the
frequency that the complete display is updated. With
OSC at 4MHz, each display digit is enabled for 200µs.
The internal RC oscillator uses an external resistor,
RSET, and an external capacitor, CSET, to set the oscil-
lator frequency. The suggested values of RSET(56kΩ)
and CSET(22pF) set the oscillator at 4MHz, which
makes the blink frequency 0.5Hz or 1Hz.
The external clock is not required to have a 50:50 duty
cycle, but the minimum time between transitions must
be 50ns or greater and the maximum time between
transitions must be 750ns.
The on-chip oscillator may be accurate enough for
applications using a single device. If an exact blink rate
is required, use an external clock ranging between
1MHz and 8MHz to drive OSC. The OSC inputs of multi-
ple MAX6955s can be connected to a common external
clock to make the devices blink at the same rate. The
relative blink phasing of multiple MAX6955s can be syn-
chronized by setting the T bit in the control register for
all the devices in quick succession. If the serial inter-
faces of multiple MAX6955s are daisy-chained by con-
necting the DOUT of one device to the DIN of the next,
then synchronization is achieved automatically by
updating the configuration register for all devices simul-
taneously. Figure 10 is the multiplex timing diagram.
OSC_OUT OutputThe OSC_OUT output is a buffered copy of either the
internal oscillator clock or the clock driven into the OSC
pin if the external clock has been selected. The feature
is useful if the internal oscillator is used, and the user
wishes to synchronize other MAX6955s to the same
blink frequency. The oscillator is disabled while the
MAX6955 is in shutdown.
Scan-Limit RegisterThe scan-limit register sets how many 14-segment dig-
its or 16-segment digits or pairs of 7-segment digits are
displayed, from 1 to 8. A bicolor digit is connected as
two monocolor digits. The scan register also limits the
number of keys that can be scanned.
Since the number of scanned digits affects the display
brightness, the scan-limit register should not be used to
blank portions of the display (such as leading-zero sup-
pression). Table 26 shows the scan-limit register format.
Intensity RegistersDigital control of display brightness is provided and
can be managed in one of two ways: globally or individ-
ually. Global control adjusts all digits together.
Individual control adjusts the digits separately.
The default method is global brightness control, which
is selected by clearing the global intensity bit (I data bit
D6) in the configuration register. This brightness setting
applies to all display digits. The pulse-width modulator
is then set by the lower nibble of the global intensity
register, address 0x02. The modulator scales the aver-
age segment current in 16 steps from a maximum of
15/16 down to 1/16 of the peak current. The minimum
interdigit blanking time is set to 1/16 of a cycle. When
using bicolor digits, 256 color/brightness combinations
are available.
Individual brightness control is selected by setting the
global intensity bit (I data bit D6) in the configuration
register. The pulse-width modulator is now no longer
set by the lower nibble of the global intensity register,
address 0x02, and the data is ignored. Individual digital
control of display brightness is now provided by a sep-
arate pulse-width modulator setting for each digit. Each
digit is controlled by a nibble of one of the four intensity
registers: intensity10, intensity32, intensity54, and inten-
sity76 for all display types, plus intensity10a, intensi-
ty32a, intensity54a, and intensity76a for the extra eight
digits possible when 7-segment displays are used. The
data from the relevant register is used for each digit as
it is multiplexed. The modulator scales the average
segment current in 16 steps in exactly the same way as
global intensity adjustment.
Table 27 shows the global intensity register format. Table
28 shows individual segment intensity registers. Table 29
shows the even individual segment intensity format. Table
30 shows the odd individual segment intensity format.
GPIO and Key ScanningThe MAX6955 features five general-purpose input/out-
put (GPIO) ports: P0 to P4. These ports can be individ-
ually enabled as logic inputs or open-drain logic
outputs. The GPIO ports are not debounced when con-
figured as inputs. The ports can be read and the out-
puts set using the 2-wire interface.
Some or all of the five ports can be configured to per-
form key scanning of up to 32 keys. Ports P0 to P4 are
renamed Key_A, Key_B, Key_C, Key_D, and IRQ,
respectively, when used for key scanning. The full key-
scanning configuration is shown in Figure 11. Table 31
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
ADDRESS (COMMAND BYTE)REGISTERD15D14D13D12D11D10D9D8HEX CODENo-OpX00000000x00
Decode ModeX00000010x01
Global IntensityX00000100x02
Scan LimitX00000110x03
ConfigurationX00001000x04
GPIO DataX00001010x05
Port ConfigurationX00001100x06
Display TestX00001110x07
Write KEY_A Mask
Read KEY_A DebounceX00010000x08
Write KEY_B Mask
Read KEY_B DebounceX00010010x09
Write KEY_C Mask
Read KEY_C DebounceX00010100x0A
Write KEY_D Mask
Read KEY_D DebounceX00010110x0B
Write Digit Type
Read KEY_A PressedX00011000x0C
Read KEY_B Pressed*X00011010x0D
Read KEY_C Pressed*X00011100x0E
Read KEY_D Pressed*X00011110x0F
Intensity 10X00100000x10
Intensity 32X00100010x11
Intensity 54X00100100x12
Intensity 76X00100110x13
Intensity 10a (7 Segment Only)X00101000x14
Intensity 32a (7 Segment Only)X00101010x15
Intensity 54a (7 Segment Only)X00101100x16
Intensity 76a (7 Segment Only)X00101110x17
Digit 0 Plane P0X01000000x20
Digit 1 Plane P0X01000010x21
Digit 2 Plane P0X01000100x22
Digit 3 Plane P0X01000110x23
Digit 4 Plane P0X01001000x24
Digit 5 Plane P0X01001010x25
Digit 6 Plane P0X01001100x26
Digit 7 Plane P0X01001110x27
Digit 0a Plane P0 (7 Segment Only)X01010000x28
Digit 1a Plane P0 (7 Segment Only)X01010010x29
Digit 2a Plane P0 (7 Segment Only)X01010100x2A
Digit 3a Plane P0 (7 Segment Only)X01010110x2B
Table 7. Register Address Map*Do NOT write to register.
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
ADDRESS (COMMAND BYTE)REGISTERD15D14D13D12D11D10D9D8HEX CODEDigit 4a Plane P0 (7 Segment Only)X01011000x2C
Digit 5a Plane P0 (7 Segment Only)X01011010x2D
Digit 6a Plane P0 (7 Segment Only)X01011100x2E
Digit 7a Plane P0 (7 Segment Only)X01011110x2F
Digit 0 Plane P1X10000000x40
Digit 1 Plane P1X10000010x41
Digit 2 Plane P1X10000100x42
Digit 3 Plane P1X10000110x43
Digit 4 Plane P1X10001000x44
Digit 5 Plane P1X10001010x45
Digit 6 Plane P1X10001100x46
Digit 7 Plane P1X10001110x47
Digit 0a Plane P1 (7 Segment Only)X10010000x48
Digit 1a Plane P1 (7 Segment Only)X10010010x49
Digit 2a Plane P1 (7 Segment Only)X10010100x4A
Digit 3a Plane P1 (7 Segment Only)X10010110x4B
Digit 4a Plane P1 (7 Segment Only)X10011000x4C
Digit 5a Plane P1 (7 Segment Only)X10011010x4D
Digit 6a Plane P1 (7 Segment Only)X10011100x4E
Digit 7a Plane P1 (7 Segment Only)X10011110x4F
Write Digit 0 Planes P0 and P1 with Same
Data, Reads as 0x00X11000000x60
Write Digit 1 Planes P0 and P1 with Same
Data, Reads as 0x00X11000010x61
Write Digit 2 Planes P0 and P1 with Same
Data, Reads as 0x00X11000100x62
Write Digit 3 Planes P0 and P1 with Same
Data, Reads as 0x00X11000110x63
Write Digit 4 Planes P0 and P1 with Same
Data, Reads as 0x00X11001000x64
Write Digit 5 Planes P0 and P1 with Same
Data, Reads as 0x00X11001010x65
Write Digit 6 Planes P0 and P1 with Same
Data, Reads as 0x00X11001100x66
Write Digit 7 Planes P0 and P1 with Same
Data, Reads as 0x00X11001110x67
Write Digit 0a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11010000x68
Write Digit 1a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11010010x69
Table 7. Register Address Map (continued)
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
One diode is required per key switch. Note that the for-
ward voltages of the diode and LED must exceed VIH
of P0–P3. If this condition is not met, the voltage input
to the port might be lower than the logic threshold and
keys will not be detected properly.
The MAX6955 can only scan the maximum 32 keys if
the scan-limit register is set to scan the maximum eight
digits. If the MAX6955 is driving fewer digits, then a
maximum of (4 x n) switches can be scanned, where n
is the number of digits set in the scan-limit register. For
example, if the MAX6955 is driving four 14-segment
digits, cathode drivers O0 to O3 are used. Only 16 keys
can be scanned in this configuration; the switches
shown connected to O4 through O7 are not read.
If the user wishes to scan fewer than 32 keys, then
fewer scan lines can be configured for key scanning.
The unused Key_x ports are released back to their orig-
inal GPIO functionality. If key scanning is enabled,
regardless of the number of keys being scanned,
P4/IRQis always configured as IRQ (Table 32).
The key-scanning circuit utilizes the LEDs’ common-
cathode driver outputs as the key-scan drivers. O0 to
O7 go low for nominally 200µs (with OSC = 4MHz) in
turn as the displays are multiplexed. By varying the
oscillator frequency, the debounce time changes,
though key scanning still functions. Key_x inputs have
internal pullup resistors that allow the key condition to
be tested. The Key_x input is low during the appropri-
ate digit multiplex period when the key is pressed. The
timing diagram of Figure 12 shows the normal situation
where all eight LED cathode drivers are used.
ADDRESS (COMMAND BYTE)REGISTERD15D14D13D12D11D10D9D8HEX CODEWrite Digit 2a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11010100x6A
Write Digit 3a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11010110x6B
Write Digit 4a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11011000x6C
Write Digit 5a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11011010x6D
Write Digit 6a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11011100x6E
Write Digit 7a Planes P0 and P1 with Same
Data (7 Segment Only), Reads as 0x00X11011110x6F
Table 7. Register Address Map (continued)
Note:Unused register bits read as zero.
SDA
DATA LINE STABLE,
DATA VALID
CHANGE OF DATA
ALLOWED
SCL
Figure 5. Bit TransferSCL
START CONDITION
SDA
BY TRANSMITTER
SDA
BY RECEIVER9
CLOCK PULSE FOR ACKNOWLEDGMENT
Figure 6. Acknowledge
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Each key press is scanned twice in a 25.6ms time peri-
od with a nominal oscillator frequency of 4MHz, as
shown in Figure 12. In the first key test period of 1.6ms,
input level at ports P0–P3 (Key_A, Key_B, Key_C, and
Key_D) are examined in conjunction with the signal-low
period of ports O0–O7 to see if any key is pressed. If
pressed, the corresponding key pressed register bit is
set. In the second key test period of 1.6ms, input level
at ports P0–P3 are examined again (debounce) to see if
the key is still pressed. If still pressed, the correspond-
ing debounce register bit is set. The debounce time
between key tests is 12.8ms.
Port Configuration RegisterThe port configuration register selects how the five port
pins are used. The port configuration register format is
described in Table 33.
Key Mask RegistersThe Key_A Mask, Key_B Mask, Key_C Mask, and
Key_D Mask write-only registers (Table 34) configure
the key-scanning circuit to cause an interrupt only when
selected (masked) keys have been debounced. Each
bit in the register corresponds to one key switch. The bit
is clear to disable interrupt for the switch, and set to
enable interrupt. Keys are always scanned (if enabled
through the port configuration register), regardless of
the setting of these interrupt bits, and the key status isA0SLAVE ADDRESSCOMMAND BYTE
ACKNOWLEDGE FROM MAX6955
R/WACKNOWLEDGE FROM MAX6955
D15D14D13D12D11D10D9D8COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITIONP
Figure 7. Command Byte Received0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
ACKNOWLEDGE FROM MAX6955
R/W1 BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6955ACKNOWLEDGE FROM MAX6955
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6955's REGISTERSAA
Figure 8. Command and Single Data Byte Received0SLAVE ADDRESSCOMMAND BYTEDATA BYTE
ACKNOWLEDGE FROM MAX6955
R/Wn BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
ACKNOWLEDGE FROM MAX6955ACKNOWLEDGE FROM MAX6955
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6955's REGISTERSAA
Figure 9. n Data Bytes Received
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
DIGIT 1
ONE COMPLETE 1.6ms MULTIPLEX CYCLE AROUND 8 DIGITS
DIGIT 0's 200µs MULTIPLEX TIMESLOT
DIGIT 0
200µs
DIGIT 2DIGIT 3DIGIT 4DIGIT 5DIGIT 6DIGIT 7
START OF
NEXT CYCLE
LOW
2/16TH
1/16TH
(MIN ON)
HIGH-Z
HIGH-Z
LOW
3/16THHIGH-Z
LOW
4/16THHIGH-Z
LOW
5/16THHIGH-Z
LOW
6/16THHIGH-Z
LOW
7/16THHIGH-Z
LOW
8/16THHIGH-Z
LOW
9/16THHIGH-Z
LOW
10/16THHIGH-Z
LOW
11/16THHIGH-Z
LOW
12/16THHIGH-Z
LOW
13/16THHIGH-Z
LOW
14/16THHIGH-Z
LOW
15/16THHIGH-Z
LOW
15/16THHIGH-Z
(MAX ON)
HIGH-Z
HIGH-Z
CURRENT SOURCE ENABLEDMINIMUM 12.5µs INTERDIGIT BLANKING INTERVAL
HIGH-Z
ANODE (LIT)
DIGIT 0 CATHODE
DRIVER INTENSITY
SETTINGS
ANODE (UNLIT)
Figure 10. Multiplex Timing Diagram (OSC = 4MHz)
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
LED OUTPUT 00
LED OUTPUT 01
LED OUTPUT 02
LED OUTPUT 03
LED OUTPUT 04
LED OUTPUT 05
LED OUTPUT 06
LED OUTPUT 07
FIRST KEY TEST
PERIOD
STARTEND
SECOND KEY TEST
PERIOD
(DEBOUNCE)STARTSTART OF NEXT KEY-SCAN CYCLE
INTERRUPT ASSERTED IF PERIOD
DEBOUNCE REGISTER UPDATED
END
12.5µs TO 187.5µs DIGIT PERIOD
1.6ms MULTIPLEX CYCLE 1
12.8MS FIRST HALF KEY-SCAN CYCLE12.8MS SECOND HALF KEY-SCAN CYCLE
A 25.6MS KEY-SCAN CYCLE
1.6ms MULTIPLEX CYCLE 21.6ms MULTIPLEX CYCLE 81.6ms MULTIPLEX CYCLE 11.6ms MULTIPLEX CYCLE 6
Figure 11. Key-Scanning Configuration
SW A0
SW A1
SW A2
SW A3
SW A4
SW A5
SW A6
SW A7
KEY_A (P0)
VCC
LED OUTPUT O0
LED OUTPUT O1
LED OUTPUT O2
LED OUTPUT O3
LED OUTPUT O4
LED OUTPUT O5
LED OUTPUT O6
LED OUTPUT O7
KEY_B (P1)
KEY_C (P2)
KEY_D (P3)
IRQ (P4)MICROCONTROLLER INTERRUPT
SW B0
SW B1
SW B2
SW B3
SW B4
SW B5
SW B6
SW B7
SW C0
SW C1
SW C2
SW C3
SW C4
SW C5
SW C6
SW C7
SW D0
LED0
LED SEGMENT IS OPTIONAL AND
BASED ON APPLICATION.
SW D1
SW D2
SW D3
SW D4
SW D5
SW D6
SW D7
LED1
LED2
LED3
LED4
LED5
Figure 12. Key-Scan Timing Diagram
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Key Debounced RegistersThe Key_A debounced, Key_B debounced, Key_C
debounced, and Key_D debounced read-only registers
(Table 35) show which keys have been detected as
debounced by the key-scanning circuit.
Each bit in the register corresponds to one key switch.
The bit is set if the switch has been correctly
debounced since the register was read last. Reading a
debounced register clears that register (after the data
has been read) so that future keys pressed can be
identified. If the debounced registers are not read, the
key-scan data accumulates. However, as there is no
FIFO in the MAX6955, the user is not able to determine
key order, or whether a key has been pressed more
than once, unless the debounced key status registers
are read after each interrupt, and before the next key-
scan cycle.
Reading any of the four debounced registers clears the
P4/IRQoutput. If a key is pressed and held down, the
key is reported as debounced (and IRQ issued) only
once. The key must be detected as released by the key-
scanning circuit, before it debounces again. If the
debounced registers are being read in response to the
P4/IRQbeing asserted, then the user should generally
read all four registers to ensure that all the keys that were
detected by the key-scanning circuit are discovered.
Key Pressed RegistersThe Key_A pressed, Key_B pressed, Key_C pressed,
and Key_D pressed read-only registers (Table 36)
show which keys have been detected as pressed by
the key-scanning circuit during the last test.
Each bit in the register corresponds to one key switch.
The bit is set if the switch has been detected as
pressed by the key-scanning circuit during the last test.
The bit is cleared if the switch has not been detected
as pressed by the key-scanning circuit during the last
test. Reading a pressed register does not clear that
register or clear the P4/IRQoutput.
Display Test RegisterThe display test register (Table 37) operates in two
modes: normal and display test. Display test mode
turns all LEDs on (including DPs) by overriding, but not
altering, all controls and digit registers (including the
shutdown register), except for the digit-type register
and the GPIO configuration register. The duty cycle,
while in display test mode, is 7/16 (see the Choosing
Supply Voltage to Minimize Power Dissipationsection).
External Components RSETand
CSET to Set Oscillator Frequency and
Peak Segment CurrentThe RC oscillator uses an external resistor, RSET, and
an external capacitor, CSET, to set the frequency, fOSC.
The allowed range of fOSCis 1MHz to 8MHz. RSETalso
sets the peak segment current. The recommended val-
ues of RSETand CSETset the oscillator to 4MHz, which
makes the blink frequencies selectable between 0.5Hz
and 1Hz. The recommended value of RSETalso sets the
peak current to 40mA, which makes the segment cur-
rent adjustable from 2.5mA to 37.5mA in 2.5mA steps.
ISEG= KL/RSETmA
fOSC= KF/(RSETx CSET) MHz
where: = 2240= 10K (typ)
RSET= external resistor in kΩ
CSET= external capacitor in pF
CSTRAY= stray capacitance from OSC pin to GND in pF
The recommended value of RSETis 56kΩand the rec-
ommended value of CSETis 22pF.
The recommended value of RSETis the minimum
allowed value, since it sets the display driver to the
maximum allowed peak segment current. RSETcan be
set to a higher value to set the segment current to a
lower peak value where desired. The user must also
ensure that the peak current specifications of the LEDs
connected to the driver are not exceeded.
The effective value of CSETincludes not only the actual
external capacitor used, but also the stray capacitance
from OSC to GND. This capacitance is usually in the
1pF to 30pF range, depending on the layout used.
Applications Information
Driving Bicolor LEDsBicolor digits group a red and a green die together for
each display element, so that the element can be lit red
or green (or orange), depending on which die (or both)
is lit. The MAX6955 allows each segment’s current to
be set individually from the 1/16th (minimum current
and LED intensity) to 15/16th (maximum current and
LED intensity), as well as off (zero current). Thus, a
bicolor (red-green) segment pair can be set to 256
color/intensity combinations.
MAX69552-Wire Interfaced, 2.7V to 5.5V
LED Display Driver with I/O
Expander and Key Scan
Choosing Supply Voltage to Minimize
Power DissipationThe MAX6955 drives a peak current of 40mA into LEDs
with a 2.2V forward-voltage drop when operated from a
supply voltage of at least 3.0V. The minimum voltage
drop across the internal LED drivers is therefore (3.0V -
2.2V) = 0.8V. If a higher supply voltage is used, the dri-
ver absorbs a higher voltage, and the driver’s power
dissipation increases accordingly. However, if the LEDs
used have a higher forward-voltage drop than 2.2V, the
supply voltage must be raised accordingly to ensure
that the driver always has at least 0.6V of headroom.
The voltage drop across the drivers with a nominal 5V
supply (5.0V - 2.2V) = 2.8V is nearly 3 times the drop
across the drivers with a nominal 3.3V supply (3.3V -
2.2V) = 1.1V. In most systems, consumption is an
important design criterion, and the MAX6955 should be
operated from the system’s 3.3V nominal supply. In
other designs, the lowest supply voltage may be 5V.
The issue now is to ensure the dissipation limit for the
MAX6955 is not exceeded. This can be achieved by
inserting a series resistor in the supply to the MAX6955,
ensuring that the supply decoupling capacitors are still
on the MAX6955 side of the resistor. For example, con-
sider the requirement that the minimum supply voltage
to a MAX6955 must be 3.0V, and the input supply
range is 5V ±5%. Maximum supply current is 35mA +
(40mA x 17) = 715mA. Minimum input supply voltage is
4.75V. Maximum series resistor value is (4.75V -
3.0V)/0.715A = 2.44Ω. We choose 2.2Ω±5%. Worst-
case resistor dissipation is at maximum toleranced
resistance, i.e., (0.715A) 2 x (2.2Ωx 1.05) = 1.18W. The
maximum MAX6955 supply voltage is at maximum
input supply voltage and minimum toleranced resis-
tance, i.e., 5.25V - (0.715A x 2.2Ωx 0.95) = 3.76V.
Low-Voltage OperationThe MAX6955 works over the 2.7V to 5.5V supply
range. The minimum useful supply voltage is deter-
mined by the forward-voltage drop of the LEDs at the
peak current ISEG, plus the 0.8V headroom required by
the driver output stages. The MAX6955 correctly regu-
lates ISEGwith a supply voltage above this minimum
voltage. If the supply drops below this minimum volt-
age, the driver output stages can brown out, and be
unable to regulate the current correctly. As the supply
voltage drops further, the LED segment drive current
becomes effectively limited by the output driver's on-
resistance, and the LED drive current drops. The char-
acteristics of each individual LED in a display digit are
well matched, so the result is that the display intensity
dims uniformly as supply voltage drops out of regula-
tion and beyond.
Computing Power DissipationThe upper limit for power dissipation (PD) for the
MAX6955 is determined from the following equation:= (V+ x 35mA) + (V+ - VLED) (DUTY x ISEGx N)
where:
V+ = supply voltage
DUTY = duty cycle set by intensity register
N = number of segments driven (worst case is 17)
VLED= LED forward voltage at ISEG
ISEG= segment current set by RSET= Power dissipation, in mW if currents are in mA
Dissipation example:
ISEG= 30mA, N = 17, DUTY = 15/16,
VLED= 2.4V at 30mA, V+ = 3.6V= 3.6V (35mA) + (3.6V - 2.4V)(15/16 x
30mA x 17) = 0.700W
Thus, for a 36-pin SSOP package (TJA= 1/0.0118 =
+85°C/W from Operating Ratings), the maximum
allowed ambient temperature TAis given by:
TJ(MAX)= TA+ (PDx TJA) = +150°C
= TA+ (0.700 x +85°C/W)
So TA= +90.5°C. Thus, the part can be operated safely
at a maximum package temperature of +85°C.
Power SuppliesThe MAX6955 operates from a single 2.7V to 5.5V
power supply. Bypass the power supply to GND with a
0.1µF capacitor as close to the device as possible. Add
a 47µF capacitor if the MAX6955 is not close to the
board’s input bulk decoupling capacitor.
