MAX6950EEE+ ,Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display DriversApplicationsMAX6950EEE -40°C to +85°C 16 QSOP-EP*Set-Top BoxesMAX6951CEE 0°C to +70°C 16 ..
MAX6951CEE ,Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display DriversFeaturesThe MAX6950/MAX6951 are compact common-cath-
MAX6950EEE+-MAX6951CEE+-MAX6951EEE+-MAX6951EEE+T
Serially Interfaced, +2.7V to +5.5V, 5- and 8-Digit LED Display Drivers
General DescriptionThe MAX6950/MAX6951 are compact common-cathode
display drivers that interface microprocessors to individ-
ual 7-segment numeric LED digits, bar graph, or discrete
LEDs through an SPI™-, QSPI™-, MICROWIRE™-com-
patible serial interface. The supply voltage can be as low
as 2.7V.
The MAX6950 drives up to five 7-segment digits or 40
discrete LEDs. The MAX6951 drives up to eight 7-seg-
ment digits or 64 discrete LEDs.
Included on-chip are hexadecimal character decoders
(0–9, A–F), multiplex scan circuitry, segment and digit
drivers, and a static RAM that stores each digit. The
user may select hexadecimal decoding or no-decode
for each digit to allow any mix of 7-segment digits, bar
graph, or discrete LEDs to be driven. The segment cur-
rent for the LEDs is set by an internal digitalbrightness
control. The segment drivers are slew-rate limited to
reduce EMI.
Individual digits may be addressed and updated with-
out rewriting the entire display. The devices include a
low-power shutdown mode, digital brightness control, a
scan-limit register that allows the user to display from
one to eight digits, segment blinking that can be syn-
chronized across drivers, and a test mode that forces
all LEDs on.
ApplicationsSet-Top Boxes
Panel Meters
White Goods
Bar Graphs and Matrix Displays
Industrial Controllers and Instrumentation
Professional Audio Equipment
Medical Equipment
FeaturesHigh-speed 26MHz SPI-, QSPI-, MICROWIRE-
Compatible Serial Interface+2.7V to +5.5V OperationIndividual LED Segment ControlSegment Blinking Control that Can Be
Synchronized Across Multiple DriversHexadecimal Decode/No-Decode Digit SelectionDigital Brightness ControlDisplay Blanked on Power-UpDrives Common-Cathode LED DigitsMultiplex Clock Syncronizable to External ClockSlew-Rate Limited Segment Drivers for Low EMI75µA Low-Power Shutdown (Data Retained)Small 16-Pin QSOP Package
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display DriversDINV+
(DIG6)/SEG6
DIG4/SEG4
(DIG5)/SEG5
(DIG7)/SEG7
SEG8
OSC
TOP VIEW
MAX6950
MAX6951
QSOPCLK
DIG3/SEG3
DIG0/SEG0
DIG2/SEG2
DIG1/SEG1
ISET
GND
( ) MAX6951 ONLY
Pin Configuration19-2227; Rev 2; 3/05
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX6950CEE0°C to +70°C 16 QSOP-EP*
MAX6950EEE-40°C to +85°C 16 QSOP-EP*
MAX6951CEE0°C to +70°C 16 QSOP-EP*
MAX6951EEE-40°C to +85°C 16 QSOP-EP*
Functional Diagram appears at end of data sheet.
Typical Application appears at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage (with Respect to GND)
V+………………………………....................................-0.3V to 6V
All Other Pins................................................-0.3V to (V+ + 0.3V)
DIG1–DIG8 Sink Current..................................................440mA
SEG1–SEG9 Source Current..............................................55mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.34mW/°C above +70°C)........667mW
Operating Temperature Ranges (TMINto TMAX)
MAX695_CEE....................................................0°C to +70°C
MAX695_EEE.................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(Typical operating circuit, V+ = +3.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Supply VoltageV+2.75.5V
Overtemperature75Shutdown Supply CurrentISHDNS hutd ow n m od e, al l d i g i tal np uts at V + or GN D TA = +25oC62160µA
Operating Supply CurrentI+
All segments on, all digits scanned,
intensity set to full, internal oscillator,
no display load connected15mA
OSC = RC oscillator18
Master Clock Frequency (OSC
Internal Oscillator)fOSCOSC = RC oscillator, RSET = 56kΩ,
CSET = 27pF4MHz
Master Clock Frequency (OSC
External Clock)fOSCOSC overdriven externally18MHz
Display Scan Rate (OSC
External Clock)fSCANEight digits scanned, OSC = overdriven
externally1551250Hz
Display Scan Rate (OSC Internal
Oscillator)fSCANEight digits scanned, OSC = RC oscillator1551250Hz
Display Scan Rate (OSC Internal
Oscillator)fSCANEight digits scanned, OSC = RC oscillator,
RSET = 56kΩ, CSET = 27pF625Hz
OSC Internal/External Detection
ThresholdVOSC1.7V
Dead Clock Protection
FrequencyfOSC75.5kHz
OSC High Time (OSC External
Clock)tCH50ns
OSC Low Time (OSC External
Clock)tCL50ns
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
ELECTRICAL CHARACTERISTICS(Typical operating circuit, V+ = +3.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSlow Segment Blink Period
(Internal Oscillator)fS LOWBLIN KEight digits scanned, OSC = RC oscillator,
RSET = 56kΩ, CSET = 27pF1s
Fast Segment Blink Period
(Internal Oscillator)fFASTBLIN KEight digits scanned, OSC = RC oscillator,
RSET = 56kΩ, CSET = 27pF0.5s
Fast or Slow Segment Blink Duty
Cycle (Note 2)49.95050.1%
Digit Drive Sink CurrentIDIGITTA = +25°C, VLED = 2.4V240320400mA
Segment Drive Source CurrentISEGTA = +25°C, VLED = 2.4V-30-40-50mA
Digit Drive Sink Current (Note 2)IDIGITTA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V80mA
Segment Drive Source Current
(Note 2)ISEGTA = +25°C, V+ = 2.7V to 3V, VLED = 2.2V-10mA
Slew Rate Rise Time∆ISEG/∆tTA = +25°C35mA/µs
LOGIC INPUTSInput Current DIN, CLK, CSIIH, IILVIN = 0 or V+-22µA
Logic High Input Voltage DIN,
CLK, CSVIH2.4V
Logic Low Input Voltage DIN,
CLK, CSVIL0.4Vyster esi s V ol tag e D IN , C LK, C S∆VI0.5V
TIMING CHARACTERISTICS (Figure 1)CLK Clock PeriodtCP38.4ns
CLK Pulse Width HightCH19ns
CLK Pulse Width LowtCL19nsS Fall to CLK Ri se S etup Ti m etCSS9.5ns
CLK Ri se to CS Rise Hold TimetCSH3ns
DIN Setup TimetDS9.5ns
DIN Hold TimetDH0ns
CS Pulse HightCSW19ns
TIMING CHARACTERISTICS (V+ = +2.7V) (Note 2)CLK Clock PeriodtCP50ns
CLK Pulse Width HightCH24ns
CLK Pulse Width LowtCL24nsS Fall to CLK Ri se Setup TimetCSS12ns
CLK Ri se to CS Rise Hold TimetCSH4ns
DIN Setup TimetDS12ns
DIN Hold TimetDH4ns
CS Pulse HightCSW24ns
Note 1:All parameters tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2:Guaranteed by design.
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATUREMAX6950/1 toc01
OSCILLATOR FREQUENCY (MHz)
TEMPERATURE (°C)
V+ = 2.7V
V+ = 3.3V
V+ = 5V
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX6950/1 toc02
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (MHz)
INTERNAL OSCILLATOR WAVEFORM
AT OSC (PIN 9)
MAX6950/1 toc03
TIMELINE (ns)
VOLTAGE AT OSC (V)
DEAD CLOCK OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX6950/1 toc04
SUPPLY VOLTAGE (V)
OSCILLATOR FREQUENCY (kHz)
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
MAX6950/1 toc05
SUPPLY VOLTAGE (V)
CURRENT NORMALIZED TO 40mA
WAVEFORM AT SEGO/DIGO (PIN 6)
V+ = 3.3V, 8 DIGITS SCANNED, 8/16 INTENSITY
MAX6950/1 toc06
TIMELINE (ns)
VOLTAGE (V)500100015002000
DIGIT 0 MULTIPLEX TIMESLOT
Typical Operating Characteristics(Typical operating circuit, scan limit set to eight digits, V+ = +3.3V, VLED= 2.4V, TA = +25°C, unless otherwise noted.)
Detailed Description
Differences Between
MAX6950 and MAX6951The MAX6950 is a five-digit common-cathode display
driver. It drives five digits, with each digit comprising
eight LEDs with cathodes connected to a common
cathode. The display limit is therefore 40 LEDs or digit
segments.
The MAX6951 is an eight-digit common-cathode dis-
play driver. It drives eight digits, with each digit com-
prising eight LEDs. The only difference between the
MAX6950 and MAX6951 is that the MAX6950 is missing
three digit drivers. The MAX6950 can be configured to
scan eight digits, but if the last three digits are wired
up, they do not light.
The MAX6950/MAX6951 use a unique multiplexing
scheme to minimize the connections between the driver
and LED display. The scheme requires that the seg-
ment connections are different to each of the five
(MAX6950) or eight (MAX6951) digits (Table 1). This is
shown in the Typical Application Circuit, which uses
single-digit type displays. The MAX6950/MAX6951 are
not intended to drive multidigit display types, which
have the segments internally wired together, unless the
segments are wired with the common cathodes to fol-
low Table 1. The MAX6950/MAX6951 can drive multi-
digit LED displays that have the segments individually
pinned for each digit because then the digits can be
connected together correctly externally, just as if indi-
vidual digits were used.
Serial-Addressing ModesThe microprocessor interface on the MAX6950/
MAX6951 is a SPI-compatible 3-wire serial interface
using three input pins (Figure 1). This interface is used
to write configuration and display data to the MAX6950/
MAX6951. The serial interface data word length is 16
bits, which are labeled D15–D0 (Table 2). D15–D8 con-
tain the command address, and D7–D0 contain the
data. The first bit received is D15, the most-significant
bit (MSB). The three input pins are:CLK is the serial clock input, and may idle low or
high at the start and end of a write sequence.CSis the MAX6950/MAX6951s’ chip-select input,
and must be low to clock data into the MAX6950/
MAX6951.DIN is the serial data input, and must be stable
when it is sampled on the rising edge of the clock.
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
PINNAMEFUNCTIONDINSerial Data Input. Data is loaded into the internal 16–bit Shift register on CLK’s rising edge.CLKSerial-Clock Input. On CLK’s rising edge, data is shifted into the Internal Shift register. On CLK’s
falling edge, data is clocked out of DOUT. CLK input is active only while CS is low.
3–6, 10–14DIGX, SEGX
Digit X outputs sink current from the display common cathode when acting as digit drivers.
Segment X drivers source current to the display. Segment/digit drivers are high impedance when
turned off.
7ISETCurrent Setting. Connect to GND through a resistor (RSET) to set the peak current. This resistor,
together with capacitor CSET, also sets the multiplex clock frequency.GNDGroundOSC
Multiplexer Clock Input. A capacitor (CSET) is connected to GND when the internal RC oscillator
multiplex clock is used. Resistor RSET (also used to set the peak current) and capacitor CSET
together set the multiplex clock frequency. When the external clock is used, OSC should be driven
by a 1MHz to 8MHz clock.CSChip-Select Input. Serial data is loaded into the Shift register while CS is low. The last 16 bits of
serial data are latched on CS’s rising edge.V+Positive Supply Voltage. Bypass to GND with a 0.1µF capacitor.
PADE xposed p adExposed pad on package underside. Connect to GND.
Pin Description
MAX6950/MAX6951The serial interface comprises a 16-bit shift register into
which DIN data is clocked on the rising edge of CLK
when CSis low. When CSis high, transitions on CLK do
not clock data into the shift register. When CSgoes
high, the 16 bits in the shift register are parallel loaded
into a 16-bit latch. The 16 bits in the latch are then
decoded to determine and execute the command.
The MAX6950/MAX6951 are written to using the follow-
ing sequence (Figure 2):Take CLK low.Take CSlow. This enables the internal 16-bit shift
register.Clock 16 bits of data in order, D15 first to D0 last,
into DIN, observing the setup and hold times.Take CShigh.
CLK and DIN may well be used to transmit data to other
peripherals. The MAX6950/MAX6951 ignore all activity
on CLK and DIN except when CSis low. Data cannot
be read from the MAX6950/MAX6951.
If fewer or greater than 16 bits are clocked into the
MAX6950/MAX6951 between taking CSlow and takinghigh again, the MAX6950/MAX6951 store the last 16
bits received, including the previous transmission(s).
The general case is when n bits (where n > 16) are
transmitted to the MAX6950/MAX6951. The last bits
comprising bits {n-15} to {n} are retained and are paral-
lel loaded into the 16-bit latch as bits D15 to D0,
respectively (Figure 3).
Digit and Control RegistersTable 3 lists the addressable Digit and Configuration
registers. The digit registers are implemented by two
planes of 8-byte dual-port SRAM, P0 and P1.
Initial Power-UpOn initial power-up, all control registers are reset, the
display is blanked, and the MAX6950/MAX6951 enter
shutdown mode. Program the display driver prior to dis-
play use. Otherwise, it is initially set to scan five digits, it
does not decode data in the data registers, and the
Intensity register is set to its minimum value. Table 4
lists the register status after power-up.
Configuration RegisterThe configuration register is used to enter and exit shut-
down, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, and
reset the blink timing. Bit position D1 should always be
written with a zero when the configuration register is
updated. See Table 5 for configuration register format.
The S bit selects shutdown or normal operation.
The B bit selects the blink rate.
The E bit globally enables or disables the blink function.
The T bit resets the blink timing.
The R bit globally clears the digit data for both planes
P0 and P1 for all digits.
When the MAX6950/MAX6951 are in shutdown mode
(Table 6), the scan oscillator is halted; all segment and
digit drivers are high impedance. Data in the digit and
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 1. Standard Driver Connection to Single-Digit Displays
DIG/SEG0
PIN 6
DIG/SEG1
PIN 5
DIG/SEG2
PIN 4
DIG/SEG3
PIN 3
DIG/SEG4
PIN 14
DIG/SEG5
PIN 13
DIG/SEG6
PIN 12
DIG/SEG7
PIN 11
SEG 8
PIN 10LED Digit 0
CC0SEG dpSEG gSEG fSEG eSEG dSEG cSEG bSEG a
LED Digit 1SEG dp
CC1SEG gSEG fSEG eSEG dSEG cSEG bSEG a
LED Digit 2SEG dpSEG g
CC2SEG fSEG eSEG dSEG cSEG bSEG a
LED Digit 3SEG dpSEG gSEG f
CC3SEG eSEG dSEG cSEG bSEG a
LED Digit 4SEG dpSEG gSEG fSEG e
CC4SEG dSEG cSEG bSEG a
LED Digit 5SEG dpSEG gSEG fSEG eSEG d
CC5SEG cSEG bSEG a
LED Digit 6SEG dpSEG gSEG fSEG eSEG dSEG c
CC6SEG bSEG a
LED Digit 7SEG dpSEG gSEG fSEG eSEG dSEG cSEG b
CC7SEG a
Table 2. Serial-Data Format (16 Bits)
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0ADDRESSMSBDATALSB
control registers remains unaltered. Shutdown can be
used to save power. For minimum supply current in
shutdown mode, logic inputs should be at ground or
V+ (CMOS-logic levels). The display driver can be pro-
grammed while in shutdown mode, and shutdown
mode can be overridden by the display test function.
Table 7 lists the blink rate selection format.
If blink is globally enabled by setting the E bit of the
configuration register (Table 8), then the digit data in
both planes P0 and P1 are used to control the display
(Table 9).
When the global blink timing synchronization bit is set,
the multiplex and blink timing counter is cleared on the
rising edge of CS. By setting the T bit in multiple
MAX6950/MAX6951s at the same time (or in quick suc-
cession), the blink timing can be synchronized across
all the devices.
When the global digit data clear (R data bit D5) is set,
the digit data for both planes P0 and P1 for ALL digits
is cleared on the rising edge of CS. Digits with decode
enabled display the zero. Digits without decode
enabled show all segments unlit.
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display DriversFigure 1. Timing Diagram
tCSStCLtCHtCP
tCSH
tCSW
tDS
tDH
D15
CLK
DIN
D14D1D0
Figure 2. Transmission of 16 Bits to the MAX6950/MAX6951
CLK
DIND15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
Figure 3 . Transmission of More than 16 Bits to the MAX6950/MAX6951
CLK
DINBIT1BIT2N-15N-14N-13N-12N-11N-10N-9N-8N-7N-6N-5N-4N-3N-2N-1N
MAX6950/MAX6951
No-Op RegisterThe no-op register is used when the MAX6950/
MAX6951 are connected as the last device on a chain
of cascaded SPI devices. To write the other cascaded
device(s), ensure that while the intended device
receives its specific command, the MAX6950/MAX6951
receive a no-op command.
Display-Test RegisterThe display-test register switches the drivers between
one of two modes: normal and display test. Display-test
mode turns all LEDs on by overriding, but not altering,
all control and digit registers (including the Shutdown
register) In display-test mode, eight digits are scanned
and the duty cycle is 7/16 (half power). Table 11 lists
the display-test register format.
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 3. Register Address Map
COMMAND ADDRESSREGISTERD15D14D13D12D11D10D9D8
HEX
CODENo-Op000000000x00
Decode Mode000000010x01
Intensity000000100x02
Scan Limit000000110x03
Configuration000001000x04
Factory reserved. Do not write to this.000001100x06
Display Test000001110x07
Digit 0 plane P0 only (plane 1 unchanged)001000000x20
Digit 1 plane P0 only (plane 1 unchanged)001000010x21
Digit 2 plane P0 only (plane 1 unchanged)001000100x22
Digit 3 plane P0 only (plane 1 unchanged)001000110x23
Digit 4 plane P0 only (plane 1 unchanged)001001000x24
Digit 5 plane P0 only (plane 1 unchanged)001001010x25
Digit 6 plane P0 only (plane 1 unchanged)001001100x26
Digit 7 plane P0 only (plane 1 unchanged)001001110x27
Digit 0 plane P1 only (plane 0 unchanged)010000000x40
Digit 1 plane P1 only (plane 0 unchanged)010000010x41
Digit 2 plane P1 only (plane 0 unchanged)010000100x42
Digit 3 plane P1 only (plane 0 unchanged)010000110x43
Digit 4 plane P1 only (plane 0 unchanged)010001000x44
Digit 5 plane P1 only (plane 0 unchanged)010001010x45
Digit 6 plane P1 only (plane 0 unchanged)010001100x46
Digit 7 plane P1 only (plane 0 unchanged)010001110x47i g i t 0 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011000000x60i g i t 1 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011000010x61i g i t 2 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011000100x62i g i t 3 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011000110x63i g i t 4 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011001000x64i g i t 5 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011001010x65i g i t 6 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011001100x66i g i t 7 p l ane P 0 and p l ane P 1 ( w i th sam e d ata) 011001110x67
Scan-Limit RegisterThe scan-limit register sets how many digits are dis-
played, from one to eight digits. It is possible to set the
MAX6950 (the five-digit part) to scan six, seven, or
eight digits. The MAX6951 set to eight digits displays
five digits less brightly than if it had been set to scan
five digits, but the brightness would match that of a
MAX6951 used in the same system if the Intensity reg-
isters are set to the same value. For example, consider
an 11-digit requirement. This can be served by using a
MAX6950 to drive five digits plus a MAX6951 to drive
six digits. Both parts are configured to drive six digits to
ensure the brightness is the same.
The digits are displayed in a multiplexed manner with a
typical display scan rate of 1kHz with five digits dis-
played or 625Hz with eight digits displayed with fOSC=
4MHz. Since the number of scanned digits affects the
display brightness, the Scan-Limit register should not
be used to blank portions of the display (such as for
leading-zero suppression). Table 12 lists the scan-limit
register format.
Intensity RegisterDigital control of display brightness is provided by an
internal pulse-width modulator, which is controlled by the
lower nibble of the intensity register (Figure 4). The mod-
ulator scales the average segment current in 16 steps
from a minimum of 15/16 down to 1/16 of the peak cur-
rent. The minimum interdigit blanking time is set to 1/16
of a cycle. See Table 13 for Intensity register format.
Decode Mode RegisterThe decode mode register sets hexadecimal code
(0–9, A–F) or no-decode operation for each digit. Each
bit in the register corresponds to one digit. A logic high
selects hexadecimal code font decoding for that digit,
while logic low bypasses the decoder. Digits may be
set for decode or no-decode in any combination.
Examples of the decode mode control register format
are shown in Table 14.
When the hexadecimal code-decode mode is used, the
decoder looks only at the lower nibble of the data in the
digit register (D3–D0), disregarding bits D6–D4. D7,
which sets the decimal point (SEG DP), is independent
of the decoder, and is positive logic (D7 = 1 turns the
decimal point on). Table 15 lists the hexadecimal code
font. When no-decode is selected, data bits D7–D0 cor-
respond to the segment lines of the MAX6950/
MAX6951. Table 15 shows the one-to-one pairing of
each data bit to the appropriate segment line.
Display Digit RegistersThe MAX6950/MAX6951 use a digit register to store the
data that the user wishes to display on the LED digits.
These digit registers are implemented by two planes of
8-byte, dual-port SRAM, called P0 and P1. The digit
registers are dual port to enable them to be written to
through the SPI interface, asynchronous to being read
to multiplex the display.
MAX6950/MAX6951
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 4. Initial Power-Up Register Status
REGISTER DATAREGISTERPOWER-UP CONDITIONADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0DecodeNo decode for digits 7–00x0100000000
Intensity1/16 (min on)0x02XXXX0000
Scan LimitDisplay 5 digits: 0 1 2 3 40x03XXXXX100
ConfigurationS hutd ow n enab l ed /b l i nk
sp eed i s sl ow /b l i nk d i sab l ed 0x04XXX00000
Display TestNormal operation0x07XXXXXXX0
Digit 0Blank digit, both planes0x6000000000
Digit 1Blank digit, both planes0x6100000000
Digit 2Blank digit, both planes0x6200000000
Digit 3Blank digit, both planes0x6300000000
Digit 4Blank digit, both planes0x6400000000
Digit 5Blank digit, both planes0x6500000000
Digit 6Blank digit, both planes0x6600000000
Digit 7Blank digit, both planes0x6700000000
MAX6950/MAX6951Each LED digit is represented by 2 bytes of memory, 1
byte in plane P0 and the other in plane P1. Each LED
digit’s segment is represented by 2 bits of memory, 1
bit from the appropriate byte in each plane. The digit
registers are mapped so that a digit’s data can be
updated in plane P0, or plane P1, or both planes at the
same time (Table 3).
Serially Interfaced, +2.7V to +5.5V,
5- and 8-Digit LED Display Drivers
Table 5. Configuration Register Format
REGISTER DATAMODEADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0Configuration register0x04XXRTEB0S
Table 6. Shutdown Control (S Data Bit D0) Format
REGISTER DATAMODEADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0Shutdown0x04XXRTEB00
Normal operation0x04XXRTEB01
Table 7. Blink Rate Selection (B Data Bit D2) Format
REGISTER DATAMODEADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0l ow - b l i nki ng seg m entsl i nk on for 1s, off for 1si th fOS C = 4M H z
0x04XXRTE00S
Fast-blinking segments
blink on for 0.5s, off for
0.5s with fOSC = 4MHz
0x04XXRTE10S
Table 8. Global Blink Enable/Disable (E Data Bit D3) Format
REGISTER DATAMODEADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0Blink function is
disabled0x04XXRT0B0S
Blink function is
enabled0x04XXRT1B0S
Table 9. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATAMODEADDRESS
CODE (HEX)D7D6D5D4D3D2D1D0Blink timing counters
are unaffected0x04XXR0EB0S
Blink timing counters
are cleared on the
rising edge of CS
0x04XXR1EB0S
