MAX6900ETT+-MAX6900ETT+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX6900ETT+T ,I²C-Compatible RTC in a TDFNFeatures2The MAX6900, I C-bus-compatible real-time clock♦ Real-Time Clock Counts Seconds, Minutes,( ..
MAX6900ETT-T ,I2C-Compatible RTC in a TDFNApplications Single-Byte or Multiple-Byte (Burst Mode) DataPortable InstrumentsTransfer for Read o ..
MAX6902ETA ,SPI-Compatible RTC in a TDFNApplicationsPoint-of-Sale EquipmentOrdering InformationIntelligent InstrumentsPIN- TOPTEMP RANGEFax ..
MAX6902ETA+ ,SPI-Compatible RTC in a TDFNFeatures♦ Real-Time Clock Counts Seconds, Minutes, Hours,The MAX6902 SPI™-compatible real-time cloc ..
MAX6902ETA+T ,SPI-Compatible RTC in a TDFNELECTRICAL CHARACTERISTICS(V = +2.0V to +5.5V, T = -40°C to +85°C. Typical values are at V = +3.3V, ..
MAX6902ETA-T ,SPI-Compatible RTC in a TDFNApplications No External Crystal Bias Resistors or CapacitorsPoint-of-Sale EquipmentRequiredIntell ..
MB3800PNF ,Switching Regulator Controller (Low Voltage)ApplicationsBIPOLARSwitching Regulator Controller(Low Voltage)MB3800n DESCRIPTIONThe MB3800 is a si ..
MB3800PNF ,Switching Regulator Controller (Low Voltage)applications incorporating a soft start function and short circuit detection function. The device h ..
MB3807A ,Power Management Switching IC (with flash memory power switching function)FUJITSU SEMICONDUCTORDS04-27602-1EDATA SHEETASSP Power SupplyBIPOLARPower Management Switching I ..
MB3813A ,Lithium Ion Battery Charger DC/DC Converter IC (High Precision with Constant-current Function)Applications (Secondary battery)Lithium Ion Battery Charger DC/DC Converter IC (High Precision with ..
MB3813A ,Lithium Ion Battery Charger DC/DC Converter IC (High Precision with Constant-current Function)Applications (Secondary battery)Lithium Ion Battery Charger DC/DC Converter IC (High Precision with ..
MB3813A ,Lithium Ion Battery Charger DC/DC Converter IC (High Precision with Constant-current Function)applications.Cell count Output voltage Part number3-cell 12.6 V/12.3 V MB3813A2-cell 8.4 V/8.2 V MB ..

MAX6900ETT+-MAX6900ETT+T
I²C-Compatible RTC in a TDFN
General Description
The MAX6900, I2C-bus-compatible real-time clock
(RTC) in a 6-pin TDFN package contains a real-time
clock/calendar and 31-byte ✕8-bit wide of static ran-
dom access memory (SRAM). The real-time clock/cal-
endar provides seconds, minutes, hours, day, date,
month, and year information. The end of the month date
is automatically adjusted for months with fewer than 31
days, including corrections for leap year up to the year
2100. The clock operates in either the 24hr or 12hr for-
mat with an AM/PM indicator.
Applications
Portable Instruments
Point-of-Sale Equipment
Intelligent Instruments
Battery-Powered Products
FeaturesReal-Time Clock Counts Seconds, Minutes,
Hours, Date, Month, Day, and Year Leap Year Compensation Valid up to Year 2100Fast (400kHz) I2C-Bus-Compatible Interface from
2.0V to 5.5V31 ✕8 SRAM for Scratchpad Data StorageUses Standard 32.768kHz, 12.5pF Load, Watch
CrystalUltra-Low 225nA (typ) Timekeeping CurrentSingle-Byte or Multiple-Byte (Burst Mode) Data
Transfer for Read or Write of Clock Registers or
SRAM6-Pin 3mm x 3mm x 0.8mm TDFN Surface-Mount
PackageNo External Crystal Bias Resistors or Capacitors
Required
MAX69002C-Compatible RTC in a TDFN
RPURPU
0.01μF
CRYSTALSCL
SDA2GNDRPU = tr/Cbus
VCC
VCC
VCC
VCC
MAX6900
19-1942; Rev 3; 6/03
Typical Operating Circuit
GNDX26SDASCL
VCC
MAX6900
TDFN
TOP VIEW
Pin Configuration
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARK
MAX6900ETT-T-40°C to +85°C6 TDFNAEU
Related Real-Time Clock Products
PARTSERIAL BUSSRAMALARM
FUNCTION
OUTPUT
FREQUENCYPIN-PACKAGE
MAX6900I2C compatible31 ✕ 8——6 TDFN
MAX69013-wire31 ✕ 8Polled32kHz8 TDFN
MAX6902SPI™ compatible31 ✕ 8Polled—8 TDFN
SPI is a trademark of Motorola, Inc.
MAX69002C-Compatible RTC in a TDFN
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND..............................................................-0.3V to +6V
All Other Pins to GND ................................-0.3V to (VCC+ 0.3V)
Input Current
All Pins ............................................................................20mA
Output Current
All Outputs.......................................................................20mA
Rate of Rise, VCC............................................................100V/µs
Continuous Power Dissipation (TA= +70°C)
6-Pin TDFN (derate 24.4mW/°C above +70°C).......1951.0mW
Operating Temperature Range...............................TMINto TMAX
MAX6900 ETT-T .......................TMIN= -40°C, TMAX= +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range............................-65°C to +150°C
ESD Protection (all pins, Human Body model)..................2000V
Lead Temperature (soldering, 10s)...…………………….+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= +2.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(VCC= +2.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Notes 1, 6)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Operating Voltage RangeVCC25.5V
VCC = +2.0V30Active Supply Current (Note 2)ICCVCC = +5.0V110µA
VCC = +2.0V0.2250.630Timekeeping Supply Current
(Note 3)ITKVCC = +5.0V1.21.7µA
2-WIRE DIGITAL INPUTS SCL, SDA
Input High VoltageVIH0.7 x VCC V
Input Low VoltageVIL0.3 x
VCCV
Input Hysteresis (Note 5)VHYS0.05 x
VCCV
Input Leakage Current (Note 4)0 < VIN < VCC-1010nA
Input Capacitance (Note 5)10pF
2-WIRE DIGITAL OUTPUT SDA
Output Low VoltageVOLISINK = 4mA0.4V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OSCILLATOR
X1 to Ground Capacitance25pF
X2 to Ground Capacitance25pF
FAST I2C-BUS-COMPATIBLE TIMING
SCL Clock FrequencyfSCL0400kHz
Bus Free Time Between STOP
and START Condition (Note 4)tBUF1.3µs
MAX69002C-Compatible RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.0V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.) (Notes 1, 6)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Hold Time After (Repeated)
START Condition (After this
Period, the First Clock Is
Generated)
tHD:STA0.6µs
Repeated START Condition
Setup TimetSU:STA0.6µs
STOP Condition Setup TimetSU:STO0.6µs
Data Hold Time (Note 7)tHD:DAT00.9µs
Data Setup TimetSU:DAT100ns
SCL Low PeriodtLOW1.3µs
SCL High PeriodtHIGH0.6µs
Minimum SCL/SDA Rise Time
(Note 8)tr20 +
0.1CBns
Maximum SCL/SDA Rise Time
(Note 8)tr300ns
Minimum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)tf20 +
0.1CBns
Maximum SCL/SDA Fall Time
(Receiving) (Notes 8, 9)tf300ns
Minimum SDA Fall Time
(Transmitting) (Notes 8, 9)tf20 +
0.1CBns
Maximum SDA Fall Time
(Transmitting) (Notes 8, 9)tf250ns
Pulse Width of Spike SuppressedtSP50ns
Capacitive Load for Each
Bus LineCB400pF
Note 1:All parameters are 100% tested at TA= +25°C. Limits over temperature are guaranteed by design and not production tested.
Note 2:ICCis specified with SCL = 400kHz and SDA = 400kHz.
Note 3:ITKis specified with SCL = Logic High (4.7kΩpullup resistor) and SDA = Logic High (4.7kΩpullup resistor); 2C-compatible bus inactive.
Note 4:MAX6900 I/O pins do not obstruct the SDA and SCL lines if VCCis switched off.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:All values referred to VIHminand VILmaxlevels.
Note 7:The MAX6900 internally provides a hold time of at least 300ns for the SDA signal (referred to the VIHminof the SCL signal)
in order to bridge the undefined region of the falling edge of SCL.
Note 8:CB= total capacitance of one bus line in pF.
Note 9:The maximum tffor the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tfis
specified at 250ns. This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tf.
Detailed Description
The MAX6900 contains eight timekeeping registers,
burst address registers, a control register, an on-chip
32.768kHz oscillator circuit, and a serial 2-wire, I2C-
compatible interface. There are also 31 bytes, 8 bits
wide of SRAM on board. Time and calendar data are
stored in the registers in a binary-coded decimal (BCD)
format. Figure 1 shows an I2C-bus-compatible timing
diagram. Figure 2 shows the MAX6900 functional dia-
gram.
Real-Time Clock
The RTC provides seconds, minutes, hours, day, date,
month, and year information. The end of the month is
automatically adjusted for months with fewer than 31
MAX69002C-Compatible RTC in a TDFN
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TIMEKEEPING CURRENT vs. VCC
MAX6900 toc01
VCC (V)
TIMEKEEPING CURRENT (
Pin Description
PINNAMEFUNCTION
1VCCPower SupplyX132.768kHz External CrystalX232.768kHz External CrystalGNDGroundSCLI2C-Bus-Compatible Clock InputSDAI2C-Bus-Compatible Data
Input/OutputPADGround
Figure 1. Detailed I2C-Bus Timing Diagrams
PROTOCOL
START
CONDITION
(S)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
BIT 7
MSB
(A7)
BIT 0
LSB
(R/W)
BIT 6
(A6)
SCL
tSU:STA
tHD:STAtHD:DATtHD:DATtSU:STO
1/fSCL
tHIGHtLOW
tBUFtrtf
SDA
days, including corrections for leap year up to the year
Crystal Oscillator
The MAX6900 uses an external, standard 12.5pF load
watch crystal. No other external components are
required for this timekeeping oscillator. Power-up oscil-
lator start-time is dependent mainly upon applied VCC
and ambient temperature. The MAX6900, because of
its low timekeeping current, exhibits a typical startup
time between 5s to 10s. 2C-Compatible Interface
Interfacing the MAX6900 with a microprocessor or
other I2C master is made easier by using the serial, I2C-
bus-compatible or other I2C master interface. Only 2
wires are required to communicate with the clock and
SRAM: SCL (serial clock) and SDA (data line). Data is
transferred to and from the MAX6900 over the I/O data
line, SDA. The MAX6900 uses 7-bit slave ID address-
ing. The MAX6900 does not respond to general call
address commands.
Applications Information2C-Bus-Compatible Interface
The I2C-bus-compatible serial interface allows bidirec-
tional, 2-wire communication between multiple ICs. The
two lines are SDA and SCL. Connect both lines to a
positive supply through individual pullup resistors. A
device on the I2C-compatible bus that generates a
message is called a transmitter and a device that
receives the message is a receiver. The device that
controls the message is the master and the devices
that are controlled by the master are called slaves
(Figure 3). The word message refers to data in the form
of three 8-bit bytes for a Single Read or Write. The first
byte is the Slave ID byte, the second byte is the
Address/Command byte, and the third is the data.
Data transfer can only be initiated when the bus is not
busy (both SDA and SCL are high). A high-to-low tran-
sition of SDA while SCL is high is defined as the Start
(S) condition; low-to-high transition of the data line
while SCL is high is defined as the Stop (P) condition
(Figure 4).
MAX69002C-Compatible RTC in a TDFN
Figure 2. Functional Diagram
OSCILLATOR
32.768kHz
CONTROL
LOGIC
ADDRESS
REGISTER
31 X 8
SRAM2C BUS
INTERFACE
DIVIDER
SECONDS
MINUTES
HOURS
DATE
MONTH
DAY
YEAR
CONTROL
CENTURY
CLOCK
BURST
1HzX1
VCC
GND
SCL
SDA
MAX69002C-Compatible RTC in a TDFN
After the Start condition occurs, 1 bit of data is trans-
ferred for each clock pulse. The data on SDA must
remain stable during the high portion of the clock pulse
as changes in data during this time are interpreted as a
control signal (Figure 5). Any time a start condition
occurs, the Slave ID must follow immediately, regard-
less of completion of the previous data transfer.
Before any data is transmitted on the I2C-bus-compati-
ble serial interface, the device that is expected to
respond is addressed first. The first byte sent after the
start (S) procedure is the Address byte or 7-bit Slave
ID. The MAX6900 acts as a slave transmitter/receiver.
Therefore, SCL is only an input clock signal and SDA is
a bidirectional data line. The Slave Address for the
MAX6900 is shown in Figure 6.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
SCL
Figure 5. I2C Bus Bit Transfer
RD/W
BIT 0BIT 7000101
Figure 6. I2C Bus Slave Address or 7-Bit Slave ID
SDA
SCL
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Figure 3. I2C Bus System Configuration
START CONDITIONSTOP CONDITIONS
SDA
SCL
SDA
SCL
Figure 4. I2C Bus Start and Stop Conditions
MAX69002C-Compatible RTC in a TDFN
An unlimited number of data bytes between the start
and stop conditions can be sent between the transmit-
ter and receiver. Each 8-bit byte is followed by an
acknowledge bit. Also, a master receiver must gener-
ate an acknowledge after each byte it receives that has
been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse (Figure 7), so
that the SDA line is stable low during the high period of
the acknowledge clock pulse (setup and hold times
must also be met). A master receiver must signal an
end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave
SDA high to enable the master to generate a stop con-
dition. Any time a stop condition is received before the
current byte of data transfer is complete, the last incom-
plete byte is ignored.
The second byte of data sent after the start condition is
the Address/Command byte (Figure 8). Each data
transfer is initiated by an Address/Command byte. The
MSB (bit 7) must be a logic 1. When the MSB is zero,
Writes to the MAX6900 are disabled. Bit 6 specifies
clock/calendar data if logic 0 or RAM data if logic 1
(Tables 1 and 2). Bits 1 through 5 specify the designat-
ed registers to be input or output. The LSB (bit 0) spec-
ifies a Write operation (input) if logic 0 or Read
operation (output) if logic 1. The Command byte is
always input starting with the MSB (bit 7).
Reading from the Timekeeping
Registers
The timekeeping registers (Seconds, Minutes, Hours,
Date, Month, Day, Year, and Century) read either with a
Single Read or a Burst Read. Since the clock runs con-
tinuously and a Read takes a finite amount of time, it is
possible that the clock counters could change during a
Read operation, thereby reporting inaccurate timekeep-
ing data. In the MAX6900, the clock counter data is
buffered by a latch. Clock counter data is latched by the
I2C-bus-compatible read command (on the falling edge
of SCL when the Slave Acknowledge bit is sent after the
Address/Command byte has been sent by the master to
read a timekeeping register). Collision-detection circuitry
ensures that this does not happen coincident with a sec-
onds counter update to ensure accurate time data is
being read. This avoids time data changes during a
Read operation. The clock counters continue to count
and keep accurate time during the Read operation.
When using a Single Read to read each of the time-
keeping registers individually, perform error checkingD6D7DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGECLK9
CLK1CLK2CLK821
NOT ACKNOWLEDGE
Figure 7. I2C Bus Acknowledge
Figure 8. Address/Command Byte
/CLK
RAMA2A1A3A4A51A1A3A4A5A7A6
MAX69002C-Compatible RTC in a TDFN
FUNCTIONA7A6A5A4A3A2A1A0VALUED7D6D5D4D3D2D1D0
CLOCK
SEC1000000RD00-59710 SEC1 SEC*POR STATE00000000
MIN1000001RD00-59010 MIN1 MIN*POR STATE000000001000010RD00-2312/241001-121/0A/P
0/11 HR
*POR STATE00000000
DATE1000011RD
01-28/29
01-31010 DATE1 DATE*POR STATE00000001
MONTH1000100RD01-1200010M1 MONTH*POR STATE00000001
DAY1000101RD01-0700000WEEK DAY*POR STATE00000001
YEAR1000110RD00-9910 YEAR1 YEAR*POR STATE01110000
CONTROL1000111RDWP0000000*POR STATE00000000
CENTURY1001001RD00-991000 YEAR100 YEAR*POR STATE00011001
RESERVED1001011RD00000000*POR STATE00000111
CLOCK
BURST1011111RD
Table 1. Register Address Definition
MAX69002C-Compatible RTC in a TDFN
FUNCTIONA7A6A5A4A3A2A1A0VALUED7D6D5D4D3D2D1D0
CLOCK
RAM
RAM 01100000RDRAM DATA 0xxxxxxxx
RAM 301111110RDRAM DATA 30xxxxxxxx
RAM BURST1111111RD
Table 1. Register Address Definition (continued)
Table 2. Hex Register Address Definition
HEX REGISTER ADDRESS/DESCRIPTION
WRITE
ADDRESS/
COMMAND
BYTE
(HEX)
READ
ADDRESS/
COMMAND
BYTE
(HEX)
DESCRIPTIONPOR
CONTENTS81Seconds0083Minutes0085Hours0087Date0189Month018BDay018DYear708FControl0093Century1997Reserved07BFClock BurstN/AC1RAM 0IndeterminateC3RAM 1IndeterminateC5RAM 2IndeterminateC7RAM 3IndeterminateC9RAM 4IndeterminateCBRAM 5IndeterminateCDRAM 6IndeterminateCFRAM 7Indeterminate
Note: POR STATEdefines power-on reset state of register contents.

Partno	Mfg	Dc	Qty	Available	Descript
MAX6900ETT+ \|MAX6900ETT	MAXIM	N/a	182	avai	I²C-Compatible RTC in a TDFN
MAX6900ETT+T	MAXIM	N/a	488	avai	I²C-Compatible RTC in a TDFN