MAX5952AEAX+ ,High-Power, Quad, PSE Controller for Power-Over-EthernetApplicationsPower-Sourcing Equipment (PSE)Switches/RoutersMidspan Power InjectorsPin Configuration ..
MAX5952AEAX+T ,High-Power, Quad, PSE Controller for Power-Over-EthernetELECTRICAL CHARACTERISTICS (V = 32V to 60V, V = 0V, V to V = +3.3V, all voltages are referenced to ..
MAX5952AUAX+ ,High-Power, Quad, PSE Controller for Power-Over-Ethernetapplications.♦ Open-Drain INT SignalThe MAX5952 provides four operating modes to suit dif-ferent sy ..
MAX5954LETX+ ,Single PCI Express, Hot-Plug Controllerapplications. The device provides hot-plug♦ Hot Swaps 12V, 3.3V, and 3.3V Auxiliary for a control f ..
MAX5955AEEE+ ,Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off ControlFeaturesThe MAX5955 and MAX5956 are +1V to +13.2V dual ♦ Safe Hot Swap for +1V to +13.2V Power Supp ..
MAX5955AEEE+ ,Low-Voltage, Dual Hot-Swap Controllers with Independent On/Off ControlFeaturesThe MAX5955 and MAX5956 are +1V to +13.2V dual ♦ Safe Hot Swap for +1V to +13.2V Power Supp ..
MAZ8160-H ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8160-L ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8160-M ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAZ8180 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8180G ,Silicon planar typeFeatures Package Extremely low noise voltage caused from the diode (2.4 V to Code 39V, 1/3 to 1 ..
MAZ8180-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAX5952AEAX+-MAX5952AEAX+T-MAX5952AUAX+
High-Power, Quad, PSE Controller for Power-Over-Ethernet
General DescriptionThe MAX5952 is a quad -48V power controller
designed for use in IEEE®802.3af-compliant/pre-IEEE
802.3at-compatible power-sourcing equipment (PSE).
This device provides powered device (PD) discovery,
classification, current limit, DC and AC load disconnect
detections in compliance with the IEEE 802.3af stan-
dard. The MAX5952 is pin compatible with MAX5945/
LTC4258/LTC4259A PSE controllers and provides addi-
tional features.
The MAX5952 features high-power mode that provides
up to 45W per port. The MAX5952 provides instanta-
neous readout of each port current through the I2C inter-
face. The MAX5952 also provides high-capacitance
detection for legacy PDs.
The device features an I2C-compatible, 3-wire serial inter-
face, and is fully software configurable and programma-
ble. The class-overcurrent detection function enables
system power management to detect if a PD draws more
than the allowable current. The MAX5952’s extensive pro-
grammability enhances system flexibility, enables field
diagnosis, and allows for uses in other applications.
The MAX5952 provides four operating modes to suit dif-
ferent system requirements. Auto mode allows the device
to operate automatically without any software supervision.
Semi-automatic mode automatically detects and classi-
fies a device connected to a port after initial software acti-
vation, but does not power up that port until instructed to
by software. Manual mode allows total software control of
the device and is useful for system diagnostics.
Shutdown mode terminates all activities and securely
turns off power to the ports.
The MAX5952 provides input undervoltage lockout
(UVLO), input undervoltage detection, input overvolt-
age lockout, overtemperature detection, output voltage
slew-rate limit during startup, power-good status, and
fault status. The MAX5952’s programmability includes
startup timeout, overcurrent timeout, and load-discon-
nect detection timeout.
The MAX5952 is available in a 36-pin SSOP package and
is rated for both extended (-40°C to +85°C) and upper
commercial (0°C to +85°C) temperature ranges.
ApplicationsPower-Sourcing Equipment (PSE)
Switches/Routers
Midspan Power Injectors
FeaturesIEEE 802.3af Compliant/Pre-IEEE 802.3at
CompatibleInstantaneous Readout of Port Current Through
I2C InterfaceHigh-Power Mode Enables Up to 45W Per PortHigh-Capacitance Detection for Legacy DevicesPin Compatible to MAX5945 and
LTC4258/LTC4259AFour Independent Power-Switch ControllersPD Detection and ClassificationSupports Both DC and AC Load Removal
DetectionsI2C-Compatible, 3-Wire Serial InterfaceCurrent Foldback and Duty-Cycle-Controlled
Current LimitOpen-Drain INTSignalDirect Fast Shutdown Control Capability
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet19-0858; Rev 1; 1/10
Pin Configuration and Selector Guide appear at end of data
sheet.
EVALUATION KIT
AVAILABLE
Ordering Information
PARTTEMP RANGEPIN-PACKAGEMAX5952AEAX+*-40°C to +85°C36 SSOP
MAX5952AUAX+0°C to +85°C36 SSOP
MAX5952CEAX+*-40°C to +85°C36 SSOP
MAX5952CUAX+*0°C to +85°C36 SSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
IEEE is a registered service mark of the Institute of Electrical
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DGND, DET_, VDD, RESET, A3–A0, SHD_, OSC,
SCL, SDAIN, and AUTO......................................-0.3V to +80V
OUT_........................................................-12V to (AGND + 0.3V)
GATE_ (internally clamped) (Note 1)..................-0.3V to +11.4V
SENSE_..................................................................-0.3V to +24V
VDD, RESET, MIDSPAN, A3–A0, SHD_, OSC, SCL,
SDAIN and AUTO to DGND..................................-0.3V to +7V
INTand SDAOUT to DGND....................................-0.3V to +12V
AGND to DGND........................................................-0.3V to +7V
Maximum Current into INT, SDAOUT, DET_.......................80mA
Maximum Power Dissipation (TA= +70°C)
36-Pin SSOP (derate 11.4mW/°C above +70°C)..........941mW
Operating Temperature Ranges:
MAX5952_EAX..............…………………………-40°C to +85°C
MAX5952_UAX....................................................0°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Note 1:GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEEmay damage the device.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIESVAGNDVAGND - VEE3260
VDGND060
VDD to VDGND, VDGND = VAGND1.715.50Operating Voltage Range
VDDVDD to VDGND, VDGND = VEE3.05.5
IEE
VOUT_ = VEE, VSENSE_ = VEE, DET_ = AGND,
all logic inputs open, SCL = SDAIN = VDD.
INT and SDAOUT open. Measured at AGND in
power mode after GATE_ pullup
4.86.8Supply Currents
IDIGAll logic inputs high, measured at VDD3.05.6
GATE DRIVER AND CLAMPINGGATE_ Pullup CurrentIPUPower mode, gate drive on, VGATE = VEE-40-50-60µA
Weak GATE_ Pulldown CurrentIPDWSHD_ = DGND, VGATE_ = VEE + 10V304255µA
Maximum Pulldown CurrentIPDSVSENSE = 600mV, VGATE_ = VEE + 2V70mA
External Gate DriveVGSVGATE - VEE, power mode, gate drive on91011V
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)(VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CURRENT LIMITIVEE = 00202212220
IVEE = 01192202212
IVEE = 10186190200
Current-Limit Clamp VoltageVSU_LIM
Maximum VSENSE_ allowed
during current limit, VOUT_ = 0V
(ICUT = 000) (Note 3)
IVEE = 11170180190
ICUT = 000
(Class 0/3)177186196
ICUT =110
(Class 1)475562
ICUT = 111
(Class 2)8694101
ICUT = 001265280295
ICUT = 010310327345
ICUT = 011355374395
ICUT = 100398419440
Overcurrent Threshold After
StartupVFLT_LIM
Overcurrent VSENSE_ threshold
allowed for t ≤ tFAULT after
startup; VOUT_ = 0V,
(IVEE = 00)
ICUT =101443466488
ICUT = 000,
ICUT = 110,
ICUT = 111
Foldback Initial OUT_ VoltageVFLBK_ST
VOUT_ - VEE, above which the
current-limit trip voltage starts
folding back, IVEE = 00ICUT =
001…10110
Foldback Final OUT_ VoltageVFLBK_END
IVEE = 00, ICUT = 000, VOUT - VEE above
which the current-limit trip voltage reaches
VTH_FBV
Minimum Foldback
Current-Limit ThresholdVTH_FBVOUT_ = VAGND = 60V, IVEE = 00, ICUT = 00064mV
SENSE_ Input Bias CurrentVSENSE_ = VEE-2+2µA
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)(VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLY MONITORSVEE Undervoltage LockoutVEEUVLOVAGND - VEE, VAGND - VEE increasing28.5V
VEE Undervoltage Lockout
HysteresisVEEUVLOHP or ts shut d ow n i f VAGND - V E E < V U V L O - E E U V L OH 3V
VEE Overvoltage LockoutVEE_OVVEE_OV event bit sets and ports shut down if
VAGND - VEE > VEE_OV, VAGND increasing62.5V
VEE Overvoltage Lockout
HysteresisVOVH1V
VEE UndervoltageVEE_UVV E E _ U V event b i t i s set i f VAGND - V E E < V E E _ U V ,E E i ncr easi ng 40V
MAX5952A3.82
VDD OvervoltageVDD_OV
VDD_OV event bit is set if
VDD - VDGND > VDD_OV;
VDD increasingMAX5952C5.7
MAX5952A2.7
VDD UndervoltageVDD_UVVDD_OV is set if VDD - VDGND
> VDD_UV, VDD decreasingMAX5952C4.2
VDD Undervoltage LockoutVDDUVLODevice operates when VDD - VDGND >
VDDUVLO, VDD increasing2V
VDD Undervoltage Lockout
HysteresisVDDHYS120mV
Thermal Shutdown ThresholdTSHD
Ports shut down and device resets if its
junction temperature exceeds this limit,
temperature increasing (Note 4)
150°C
Thermal Shutdown HysteresisTSHDHThermal hysteresis, temperature decreasing
(Note 5)20°C
OUTPUT MONITOROUT_ Input CurrentIBOUTVOUT = VAGND, all modes2µA
Idle Pullup Current at OUT_IDIS
OUT_ discharge current, detection and
classification off, port shutdown,
VOUT_ = VAGND - 2.8V
200260µA
PGOOD High ThresholdPGTHVOUT_ - VEE, OUT_ decreasing1.52.02.5V
PGOOD HysteresisPGHYS220mV
PGOOD Low-to-High Glitch
FiltertPGOODMinimum time PGOOD has to be high to set
bit in register 10h3ms
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)(VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOAD DISCONNECTDC Load Disconnect
ThresholdVDCTHMinimum VSENSE allowed before disconnect
(DC disconnect active), VOUT_ = 0V2.53.755.0mV
AC Load Disconnect
Threshold (Note 6)IACTHCurrent into DET_, for I < IACTH the port
powers off, ACD_EN_ bit = H; VOSC_IN = 2.2V300320350µA
Oscillator Buffer GainAOSCVDET_/VOSC, ACD_EN_ bit = H2.93.03.1V/V
OSC Fail Threshold (Note 7)VOSC_FAILPort does not power on if VOSC < VOSC_FAIL
and ACD_EN_ bit is high1.82.2V
OSC Input ImpedanceZOSCOSC input impedance when all the ACD_EN_
are active100kΩ
Load Disconnect TimertDISCTime from VSENSE < VDCTH to gate shutdown
(Note 8)300400ms
DETECTIONDetection Probe Voltage
(First Phase)VDPH1VAGND - VDET_ during the first detection
phase3.844.2V
Detection Probe Voltage
(Second Phase)VDPH2VAGND - VDET_ during the second detection
phase9.09.39.6V
Current-Limit ProtectionIDLIMVDET_ = VAGND, during detection, measure
current through DET_1.51.752.0mA
Short-Circuit ThresholdVDCP
If VAGND - VOUT < VDCP after the first
detection phase a short circuit to AGND is
detected
Open-Circuit ThresholdID_OPENFirst point measurement current threshold for
open condition12.5µA
Resistor Detection WindowRDOK(Note 9)19.026.5kΩ
Detection rejects lower values15.2Resistor Rejection WindowRDBADDetection rejects higher values32kΩ
CLASSIFICATIONClassification Probe VoltageVCLVAGND - VDET_ during classification1620V
Current-Limit ProtectionICILIMDET_ = AGND, during classification, measure
current through DET_6881mA
Class 0, Class 15.56.57.5
Class 1, Class 21314.516
Class 2, Class 3212325
Class 3, Class 4313335
Classification Current
ThresholdsICL
Classification current
thresholds between
classes
Class 4, Class 5454851
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)(VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS/OUTPUTS (Referred to DGND)Digital Input LowVIL0.9V
Digital Input HighVIH2.4V
Internal Input Pullup/Pulldown
ResistorRDINPullup (pulldown) resistor to VDD (DGND) to
set default level255075kΩp en- D r ai n O utp ut Low V ol tag eVOLISINK = 15mA0.4V
Digital Input LeakageIDLInput connected to the pull voltage2µA
Open-Drain LeakageIOLOpen-drain high impedance, VO = 3.3V2µA
TIMINGStartup TimetSTART
Time during which a current limit set by
VSU_LIM is allowed, starts when the GATE_ is
turned on (Note 5)6070ms
Fault TimetFAULTMaximum allowed time for an overcurrent
condition set by VFLT_LIM after startup (Note 5)506070ms
Port Turn-Off TimetOFFMinimum delay between any port turning off,
does not apply in case of a reset0.5ms
Detection Reset TimeTime allowed for the port voltage to reset
before detection starts8090ms
Detection TimetDETMaximum time allowed before detection is
completed330msi d sp an M od e D etecti on D el aytDMID2.02.4s
Classification TimetCLASSTime allowed for classification1923ms
VEEUVLO Turn-On DelaytDLYTime VAGND must be above the VEEUVLO
thresholds before the device operates24ms
RSTR bits = 0016 x
tFAULT
RSTR bits = 0132 x
tFAULT
RSTR bits = 1064 x
tFAULT
Restart TimertRESTART
Time a port has to wait
before turning on after an
overcurrent fault,
RSTR_EN_ bits = high
RSTR bits = 110
Watchdog Clock PeriodtWDRate of decrement of the watchdog timer164ms
ADC PERFORMANCEResolution9Bits
Range0.51V
LSB Step Size1mV
Integral Nonlinearity (Relative)INL0.5LSB
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)(VAGND= 32V to 60V, VEE= 0V, VDDto VDGND= +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at
VAGND= +48V, VDGND= +48V, VDD= (VDGND+ 3.3V), TA= +25°C. Currents are positive when entering the pin and negative other-
wise.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential NonlinearityDNL0.1LSB
VSENSE = 100mV5B
(91)
(98)
(104)
VSENSE = 250mVF0
(240)
(252)
(264)ADC Absolute Accuracy
VSENSE = 400mV186
(390)
(406)
1A6
(422)
Hex
(Dec)
TIMING CHARACTERISTICS (For 2-Wire Fast Mode, Note 10)Serial-Clock FrequencyfSCL400kHz
Bus Free Time Between a
STOP and START ConditiontBUF1.2µs
Hold Time for a START
ConditiontHD, STA0.6µs
Low Period of the SCL ClocktLOW1.2µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated
START Condition (Sr)tSU, STA0.6µs
Data Hold TimetHD, DAT0150ns
Data in Setup TimetSU, DAT100ns
Rise Time of Both SDA and
SCL Signals, ReceivingtR20 +
0.1CB300ns
Fall Time of SDA TransmittingtF20 +
0.1CB300ns
Setup Time for STOP ConditiontSU, STO0.6µs
Capacitive Load for Each Bus
LineCB400pF
Pulse Width of Spike
SuppressedtSP50ns
Note 2: Limits to TA= -40°C are guaranteed by design.
Note 3:Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register
Map and Descriptionsection).
Note 4: Functional test is performed over thermal shutdown entering test mode.
Note 5:Default values. The startup and fault times can be also programmed through the I2C serial interface (see the Register Map
and Descriptionsection).
Note 6: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 7:AC disconnect works only if (VDD- VDGND)≥3V and DGND is connected to AGND.
Note 8: tDISCcan also be programmed through the serial interface (R16H) (see the Register Map and Descriptionsection).
Note 9:RD = (VOUT_2- VOUT_1) / (IDET_2- IDET_1). VOUT_1, VOUT_2, IDET_2and IDET_1represent the voltage at OUT_ and the cur-
rent at DET_ during phase 1 and 2 of the detection.
Note 10: Guaranteed by design. Not subject to production testing.
SENSE TRIP VOLTAGE
vs. INPUT VOLTAGEMAX5952 toc09
SENSE TRIP VOLTAGE (mV)52474237
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Typical Operating Characteristics
(VEE= -48V, VDD= +3.3V, VAUTO= VAGND= VDGND= 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, IVEE = 00, ICUT = 000,= +25°C, all registers = default setting, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. INPUT VOLTAGEMAX5952 toc01
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)52474237
MEASURED AT AGND
ANALOG SUPPLY CURRENT
vs. TEMPERATUREMAX5952 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX5952 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX5952 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MEASURED AT VDD
VEE UNDERVOLTAGE LOCKOUT
vs. TEMPERATUREMAX5952 toc05
TEMPERATURE (°C)
UNDERVOLTAGE LOCKOUT (V)3510-15
GATE OVERDRIVE
vs. INPUT VOLTAGE
MAX5952 toc06
INPUT VOLTAGE (V)
GATE OVERDRIVE (V)52474237
GATE OVERDRIVE vs. TEMPERATURE
MAX5952 toc07
TEMPERATURE (°C)
GATE OVERDRIVE (V)35-1510
SENSE TRIP VOLTAGE
vs. TEMPERATURE
MAX5952 toc08
TEMPERATURE (°C)
SENSE TRIP VOLTAGE (mV)3510-15
-4085
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
FOLDBACK CURRENT-LIMIT
THRESHOLD vs. OUTPUT VOLTAGEMAX5952 toc10
VOUT - VEE (V)
SENSE
- V
EE
(mV)302010
FOLDBACK CURRENT-LIMIT
THRESHOLD vs. OUTPUT VOLTAGE
MAX5952 toc10a
VOUT - VEE (V)
SENSE
- V
EE
(mV)302010
DC LOAD DISCONNECT THRESHOLD
vs. TEMPERATURE
MAX5952 toc11
TEMPERATURE (°C)
DC LOAD DISCONNECT THRESHOLD (mV)3510-15
OVERCURRENT TIMEOUT
(RLOAD = 240Ω TO 57Ω)
MAX5952 toc12
20ms/div
(AGND - VOUT)
50V/div
IOUT
200mA/div
INT
5V/div
VGATE_
10V/div
VEE
OVERCURRENT RESPONSE WAVEFORM
(MAX5952AUAX) (RLOAD = 240Ω TO 57Ω)MAX5952 toc13
400μs/div
(AGND - VOUT)
50V/div
IOUT
200mA/div
INT
2V/div
GATE
10V/div
VEE
SHORT-CIRCUIT RESPONSE TIMEMAX5952 toc14
20ms/div
(AGND - VOUT)
20V/div
IOUT
200mA/div
VGATE_
10V/div
VEE
SHORT-CIRCUIT RESPONSE TIMEMAX5952 toc15
4μs/div
(AGND - VOUT)
20V/div
IOUT
10A/div
VGATE_
10V/div
130mA
VEE
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, VAUTO= VAGND= VDGND= 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, IVEE = 00, ICUT = 000,= +25°C, all registers = default setting, unless otherwise noted.)
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, VAUTO= VAGND= VDGND= 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, IVEE = 00, ICUT = 000,= +25°C, all registers = default setting, unless otherwise noted.)
RESET TO OUT TURN-OFF DELAYMAX5952 toc16
100μs/div
RESET
2V/div
IOUT
200mA/div
VGATE_
5V/div
VEE
ZERO-CURRENT DETECTION WAVEFORMMAX5952 toc17
100ms/div
INT
2V/div
IOUT
200mA/div
VGATE_
10V/div
VEE
(AGND - VOUT)
20V/div
OVERCURRENT RESTART DELAYMAX5952 toc18
400ms/div
IOUT
200mA/div
VGATE_
10V/div
VEE
(AGND - VOUT)
20V/div
STARTUP WITH VALID PD
(25kΩ AND 0.1μF)MAX5952 toc19
100ms/div
IOUT
100mA/div
VGATE_
5V/div
VEE
(AGND - VOUT)
20V/div
DETECTION WITH INVALID PD
(25kΩ AND 10μF)MAX5952 toc20
40ms/div
IOUT
1mA/div
(AGND - VOUT)
20V/div
DETECTION WITH INVALID PD (15kΩ)MAX5952 toc21
100ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
DETECTION WITH INVALID PD (33kΩ)MAX5952 toc22
100ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
STARTUP IN MIDSPAN MODE
WITH VALID PD (25kΩ AND 0.1μF)MAX5952 toc23
100ms/div
IOUT
100mA/div
(AGND - VOUT)
20V/div
VGATE_
5V/div
VEE
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (15kΩ)MAX5952 toc24
400ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
VGATE_
10V/divVEE
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (33kΩ)MAX5952 toc25
400ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
VGATE_
10V/divVEE
DETECTION WITH OUTPUT SHORTEDMAX5952 toc26
40ms/div
IOUT
1mA/div
(AGND - VOUT)
5V/div
VGATE_
10V/divVEE
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 1)MAX5952 toc27
40ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
VGATE_
10V/divVEE
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, VAUTO= VAGND= VDGND= 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, IVEE = 00, ICUT = 000,= +25°C, all registers = default setting, unless otherwise noted.)
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 2)MAX5952 toc28
40ms/div
IOUT
1mA/div0A
(AGND - VOUT)
5V/div
VGATE_
10V/divVEE
STARTUP WITH DIFFERENT PD CLASSESMAX5952 toc29
40ms/div
IOUT
20mA/div
(AGND - VOUT)
5V/div
CLASS 5
CLASS 4
CLASS 3
CLASS 2
CLASS 1
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, VAUTO= VAGND= VDGND= 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, IVEE = 00, ICUT = 000,= +25°C, all registers = default setting, unless otherwise noted.)
Pin Description
PINNAMEFUNCTIONRESET
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to their
default value. The address (A0–A3), and AUTO and MIDSPAN input-logic levels latch on during low-to-
high transition of RESET. RESET is internally pulled up to VDD with a 50kΩ resistor.MIDSPAN
Midspan Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to end-point PSE
operation (power-over-signal pairs). Pull MIDSPAN to VDIG to set midspan operation. The MIDSPAN value
latches after the IC is powered up or reset (see the PD Detection section).INT
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section for more information about interrupt
management).SCLSerial Interface Clock Line InputSDAOUTSerial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Operating
Circuits). Connect SDAOUT to SDAIN if using a 2-wire, I2C-compatible system.SDAINSerial Interface Input Data Line. Connect the data line optocoupler output to SDAIN (see the Typical
Operating Circuits). Connect SDAIN to SDAOUT if using a 2-wire, I2C-compatible system.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Pin Description (continued)
PINNAMEFUNCTION7–10A3–A0
Address Bits. A3–A0 form the lower part of the device’s address. Address inputs default high with an
internal 50kΩ pullup resistor to VDD. The address values latch when VDD or VEE ramps up and exceeds
its UVLO threshold or after a reset. The 3 MSBs of the address are set to 010.
11–14DET1–DET4
Detection/Classification Voltage Outputs. Use DET1 to set the detection and classification probe voltages
on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect scheme (see the
Typical Operating Circuits).DGNDDigital Ground. Connect to digital ground.VDDPositive Digital Supply. Connect to a digital power supply (reference to DGND).
17– 20SHD1–SHD4Port Shutdown Inputs. Pull SHD_ low to turn off the external FET on port_. Internally pulled up to VDD with
a 50kΩ resistor.AGNDAnalog Ground. Connect to the high-side analog supply.
22, 25,
29, 32
SENSE4,
SENSE3,
SENSE2,
SENSE1
MOSFET Source Current-Sense Negative Inputs. Connect to the source of the power MOSFET and
connect a current-sense resistor between SENSE_ and VEE (see the Typical Operating Circuits).
23, 26,
30, 33
GATE4,
GATE3,
GATE2,
GATE1
Port_ MOSFET Gate Drivers. Connect GATE_ to the gate of the external MOSFET (see the Typical
Operating Circuits).
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
MOSFET Drain-Output Voltage Senses. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV (see the
Typical Operating Circuits).VEELow-Side Analog Supply Input. Connect the low-side analog supply to VEE (-48V). Bypass with a 1µF
capacitor between AGND and VEE.AUTO
Auto or Shutdown Mode Input. Force AUTO high to enter auto mode after a reset or power-up. Drive low
to put the MAX5952 into shutdown mode. In shutdown mode, software controls the operational modes of
the MAX5952. A 50kΩ internal pulldown resistor defaults to AUTO low. AUTO latches when VDD or VEE
ramps up and exceeds its UVLO threshold or when the device resets. Software commands can take the
MAX5952 out of AUTO while AUTO is high.OSC
Oscillator Input. AC-disconnect detection function uses OSC. Connect a 100Hz ±10%, 2VP-P ±5%, +1.2V
offset sine wave to OSC. If the oscillator positive peak falls below the OSC_FAIL threshold of 2V, the ports
that have the AC function enabled shut down and are not allowed to power-up. When not using the AC-
disconnect detection function, leave OSC unconnected.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Functional Diagram50μA
90μA100mA
MAX
FAST
DISCHARGE
CONTROL
212mV182mV
13V CLAMP
CURRENT-LIMIT
DETECTOR
4mV
OVERCURRENT
(OVC)
OPEN CIRCUIT
(OC)
CURRENT
LIMIT (ILIM)
PWR_EN
10V
VOLTAGE
SENSING
FOLDBACK
CONTROL
9-BIT ADC
CONVERTER
VOLTAGE PROBING
AND
CURRENT-LIMIT
CONTROL
CURRENT SENSING
SENSE_
GATE_
OUT_
DET_
A = 3
DETECTION
ACD_ENABLE
AC DISCONNECT
SIGNAL
(ACD)
ACD
REFERENCE
CURRENT
DETECTION/
CLASSIFICATION
PORT
STATE
MACHINE
(SM)
REGISTER FILE
SERIAL
PORT
INTERFACE
(SPI)
AUTO
MIDSPAN
ANALOG
BIAS/
SUPPLY
MONITOR
AGND
VEE
VDD
DGND
+10V ANALOG
+5V DIG
VOLTAGE
REFERENCES
CURRENT
REFERENCES
CENTRAL LOGIC UNIT
(CLU)
DGNDOSC_INSCLSDAINSDAOUTVDD
OSCILLATOR
MONITOR
SHD_
RESET
INT
MAX5952
9 BITS
ADC
REGISTER
FILE
CURRENT
MEASUREMENT
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Detailed DescriptionThe MAX5952 is a quad -48V power controller
designed for use in IEEE 802.3af-compliant/pre-IEEE
802.3at-compatible PSE. This device provides PD dis-
covery, classification, current limit, DC and AC load
disconnect detections in compliance with the IEEE
802.3af standard. The MAX5952 is pin compatible with
the MAX5945/LTC4258/LTC4259A PSE controllers and
provides additional features.
The MAX5952 features a high-power mode which pro-
vides up to 45W per port. The device allows the user to
program the current-limit and overcurrent thresholds up
to 2.5 times the default thresholds. The MAX5952 can
also be programmed to decrease the current-limit and
overcurrent threshold by 15% for high operating voltage
conditions to keep the output power constant.
The MAX5952 provides instantaneous readout of each
port current through the I2C interface. The MAX5952 also
provides high-capacitance detection for legacy PDs.
The MAX5952 is fully software configurable and pro-
grammable through an I2C-compatible, 3-wire serial
interface with 49 registers. The class-overcurrent
detection function enables system power management
to detect if a PD draws more than the allowable current.
The MAX5952’s extensive programmability enhances
system flexibility, enables field diagnosis, and allows
for uses in other applications.
The MAX5952 provides four operating modes to suit
different system requirements. Auto mode allows the
device to operate automatically without any software
supervision. Semi-auto mode automatically detects and
classifies a device connected to a port after initial soft-
ware activation but does not power up that port until
instructed to by software. Manual mode allows total
software control of the device and is useful for system
diagnostics. Shutdown mode terminates all activities
and securely turns off power to the ports.
The MAX5952 provides input undervoltage lockout, input
undervoltage detection, input overvoltage lockout,
overtemperature detection, output voltage slew-rate limit
during startup, power-good, and fault status. The
MAX5952’s programmability includes startup timeout,
overcurrent timeout, and load-disconnect detection time-
out.
The MAX5952 communicates with the system micro-
controller through an I2C-compatible interface. The
MAX5952 features separate input and output data lines
(SDAIN and SDAOUT) for use with optocoupler isola-
tion. As a slave device, the MAX5952 includes four
address inputs allowing 16 unique addresses. A sepa-
rate INToutput and four independent shutdown inputs
(SHD_) provide fast response from a fault to port shut-
down between the MAX5952 and the microcontroller. A
RESETinput allows hardware reset of the device.
ResetReset is a condition the MAX5952 enters after any of
the following conditions:After power-up (VEEand VDDrise above their
UVLO thresholds).Hardware reset. The RESETinput is driven low and
back high again any time after power-up.Software reset. Writing a 1 into R1Ah[4] any time
after power-up.Thermal shutdown.
During a reset, the MAX5952 resets its register map to
the reset state as shown in Table 37 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, change at the AUTO and MIDSPAN
input is ignored. While the condition that caused the
reset persists (i.e. high temperature, RESETinput low,
or UVLO conditions) the MAX5952 does not acknowl-
edge any addressing from the serial interface.
Port Reset (R1Ah[3:0])Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Midspan ModeIn midspan mode, the device adopts cadence timing
during the detection phase. When cadence timing is
enabled and a failed detection occurs, the port waits
between 2s and 2.4s before attempting to detect again.
Midspan mode is activated by setting R11[1] high. The
status of the MIDSPAN pin is written to R11[1] during
power-up or after a reset. MIDSPAN is internally pulled
low by a 50kΩresistor.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Operation ModesThe MAX5952 contains four independent, but identical
state machines to provide reliable and real-time control
of the four network ports. Each state machine has four
operating modes: auto mode, semi-auto mode, manual,
and shutdown. Auto mode allows the device to operate
automatically without any software supervision. Semi-
auto mode, upon request, continuously detects and
classifies a device connected to a port but does not
power up that port until instructed by software. Manual
mode allows total software control of the device and is
useful in system diagnostics. Shutdown mode termi-
nates all activities and securely turns off power to the
ports.
Switching between auto, semi, or manual mode does
not interfere with the operation of the port. When the
port is set into shutdown mode, all the port operations
are immediately stopped and the port remains idle until
shutdown is exited.
Automatic (Auto) ModeEnter automatic (auto) mode by forcing the AUTO input
high prior to a reset, or by setting R12h[P_M1,P_M0] to
[1,1] during normal operation (see Tables 16 and 16a).
In auto mode, the MAX5952 performs detection, classi-
fication, and powers up the port automatically once a
valid PD is detected at the port. If a valid PD is not con-
nected at the port, the MAX5952 repeats the detection
routine continuously until a valid PD is connected.
Going into auto mode, the DET_EN and CLASS_EN bits
are set to high and stay high unless changed by soft-
ware. Using software to set DET_EN and/or CLASS_EN
low causes the MAX5952 to skip detection and/or clas-
sification. As a protection, disabling the detection rou-
tine in auto mode does not allow the corresponding port
to power up, unless the DET_BY (R23H[4]) is set to 1.
The AUTO status is latched into the register only dur-
ing a reset. Any changes to the AUTO input after reset
are ignored.
Semi-Automatic (Semi-Auto) ModeEnter semi-auto mode by setting R12h[P_M1,P_M0] to
[1,0] during normal operation (see Tables 16 and 16a).
In semi-auto mode, the MAX5952, upon request, per-
forms detection and/or classification repeatedly but
does not power up the port(s), regardless of the status
of the port connection.
Setting R19h[PWR_ON_] (Table 22) high immediately
terminates detection/classification routines and turns on
power to the port(s).
R14h[DET_EN_, CLASS_EN_] default to low in semi-auto
mode. Use software to set R14h[DET_EN_, CLASS_EN_]
to high to start the detection and/or classification rou-
tines. R14h[DET_EN_, CLASS_EN_] are reset every time
the software commands a power off of the port (either
through reset or PWR_OFF). In any other case, the status
of the bits is left unchanged (including when the state
machine turns off the power because a load disconnect
or a fault condition is encountered).
Manual ModeEnter manual mode by setting R12h[P_M1,P_M0] to [0,1]
during normal operation (see Tables 16 and 16a).
Manual mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_EN_]
and R14h[CLASS_EN_] to start detection and classifica-
tion operations, respectively, and in that priority order.
After execution, the command is cleared from the regis-
ter(s). PWR_ON_ has highest priority. Setting PWR_ON_
high at any time causes the device to immediately enter
the powered mode. Setting DET_EN and CLASS_EN
high at the same time causes detection to be performed
first. Once in the powered state, the device ignores
DET_EN_ or CLASS_EN_ commands.
When switching to manual mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become pushbutton rather than configuration bits (i.e.,
writing ones to these bits while in manual mode com-
mands the device to execute one cycle of detection
and/or classification. The bits are reset back to zeros at
the end of the execution).
Shutdown ModeEnter shutdown mode by forcing the AUTO input low
prior to a reset, or by setting R12h[P_M1,P_M0] to [0,0]
during normal operation (see Tables 16 and 16a). Putting
the MAX5952 into shutdown mode immediately turns off
power and halts all operations to the corresponding port.
The event and status bits of the affected port(s) are also
cleared. In shutdown mode, the DET_EN_, CLASS_EN_
and PWR_ON_ commands are ignored.
In shutdown mode, the serial interface operates normally.
PD DetectionWhen PD detection is activated, the MAX5952 probes
the output for a valid PD. After each detection cycle,
the device sets the DET_END_ bit R04h/05h[3:0] high
and reports the detection results in the status registers
R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The
DET_END_ bit is reset to low when read through R05h
or after a port reset.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-EthernetA valid PD has a 25kΩdiscovery signature characteristic
as specified in the IEEE 802.3af/at standard. Table 1
shows the IEEE 802.3af/at specification for a PSE detect-
ing a valid PD signature. See the Typical Operating
Circuitsand Figure 1 (Detection, Classification, and
Power-Up Port Sequence). The MAX5952 can probe and
categorize different types of devices connected to the
port such as: a valid PD, an open circuit, a low resistive
load, a high resistive load, a high capacitive load, a posi-
tive DC supply, or a negative DC supply.
During detection, the MAX5952 keeps the external
MOSFET off and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5952 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
An external diode, in series with the DET_ input,
restricts PD detection to the first quadrant as specified
by the IEEE 802.3af/at standard. To prevent damage to
non-PD devices, and to protect itself from an output
short circuit, the MAX5952 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5952 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
High-Capacitance DetectionThe CLC_EN bit in register R23h[5] enables the large
capacitor detection feature for legacy PD devices.
When CLC_EN = 1, the high-capacitance detection limit
is extended up to 100µF. CLC_EN = 0 is the default
condition for the normal capacitor size detection. See
Table 1 and the Register Map and Descriptionsection.
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
PARAMETERSYMBOLMINMAXUNITSADDITIONAL INFORMATIONOpen-Circuit VoltageVOC—30VIn detection mode only
Short-Circuit CurrentISC—5mAIn detection mode only
Valid Test VoltageVVALID2.810V
Voltage Difference
Between Test PointsΔVTEST1—V
Time Between Any Two
Test PointstBP2—msThis timing implies a 500Hz maximum probing
frequency
Slew RateVSLEW0.1V/µs
Accept Signature
ResistanceRGOOD1926.5kΩ
Reject Signature
ResistanceRBAD< 15> 33kΩ
Open-Circuit ResistanceROPEN500—kΩ
Accept Signature
CapacitanceCGOOD—150nF
Reject Signature
CapacitanceCBAD10—µF
Signature Offset Voltage
ToleranceVOS02.0V
Signature Offset Current
ToleranceIOS012µA
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Powered Device Classification
(PD Classification)During the PD classification mode, the MAX5952 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both status registers, R04h, and R05h are
cleared after the port powers down. Table 2 shows the
IEEE 802.3af requirement for a PSE classifying a PD at
the power interface (PI).
The MAX5952 supports high power beyond the IEEE
802.3af standard by providing additional classifications
(Class 5 and ping-pong classification).
Powered StateWhen the MAX5952 enters a powered state, the tSTART
and tDISCtimers are reset. Before turning on the port
power, the MAX5952 checks if any other port is not
turning on and if the tFAULTtimer is zero. Another
check is performed if the ACD_EN bit is set, in this
case the OSC_FAIL bit must be low (oscillator is okay)
for the port to be powered.
If these conditions are met, the MAX5952 enters startup
where it turns on power to the port. An internal signal,
POK_, asserts high when VOUTis within 2V from VEE.
PGOOD_ status bits are set high if POK_ stays high
longer than tPGOOD. PGOOD immediately resets when
POK goes low.
The PG_CHG_ bit sets when a port powers up or down.
PWR_EN sets when a port powers up and resets when
a port shuts down. The port shutdown timer lasts 0.5ms
and prevents other ports from turning off during that
period, except in the case of emergency shutdowns
(RESET= L, RESET_IC = H, VEEUVLO, VDDUVLO, and
TSHD).
The MAX5952 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., port 1 turns on first, port 2 second, port 3
third and port 4 fourth). Setting PWR_OFF_ high turns off
power to the corresponding port.
Table 2. PSE Classification of a PD (Table
33-4 of the IEEE 802.3af)
MEASURED ICLASS (mA)CLASSIFICATION0 to 5Class 0
> 5 and < 8May be Class 0 and 1
8 to 13Class 1
> 13 and < 16May be Class 1 or 2
16 to 21Class 2
> 21 and < 25May be Class 2 or 3
25 to 31Class 3
> 31 and < 35May be Class 3 or 4
35 to 45Class 4
> 45 and < 51May be Class 4 or 5
51 to 68Class 5
Figure 1. Detection, Classification, and Power-Up Port
Sequence
OUT_
-4V
-9V
-18V
-48V
tDETItDETIItCLASS
150ms150ms21.3ms
80ms
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Overcurrent ProtectionA sense resistor RSconnected between SENSE_ and
VEEmonitors the load current. Under normal operating
conditions, the voltage across RS(VRS) never exceeds
the threshold VSU_LIM. If VRSexceeds VSU_LIM, an
internal current-limiting circuit regulates the GATE volt-
age, limiting the current to ILIM= VSU_LIM / RS. During
transient conditions, if VRSexceeds VSU_LIM by more
than 1V, a fast pulldown circuit activates to quickly
recover from the current overshoot. During startup, if
the current-limit condition persists, when the startup
timer, tSTART, times out, the port shuts off, and the
STRT_FLT_ bit is set. In the normal powered state, the
MAX5952 checks for overcurrent conditions as deter-
mined by VFLT_LIM= ~88% of VSU_LIM. The tFAULT
counter sets the maximum allowed continuous overcur-
rent period. The tFAULTcounter increases when VRS
exceeds VFLT_LIMand decreases at a slower pace
when VRSdrops below VFLT_LIM. A slower decrement
for the tFAULTcounter allows for detecting repeated
short-duration overcurrents. When the counter reaches
the tFAULTlimit, the MAX5952 powers off the port and
asserts the IMAX_FLT_ bit. For a continuous overstress,
a fault latches exactly after a period of tFAULT. VSU_LIM
is programmable through the ICUT registers R2Ah[6:4],
R2Ah[2:0], R2Bh[6:4], R2Bh[2:0], and the IVEE bits in
register R29h[1:0]. See the High-Power Modesection
for more information on the ICUT register.
After power-off due to an overcurrent fault, and if the
RSTR_EN bit is set, the tFAULTtimer is not immediately
reset but starts decrementing at the same slower pace.
The MAX5952 allows the port to be powered on only
when the tFAULTcounter is at zero. This feature sets an
automatic duty-cycle protection to the external MOS-
FET avoiding overheating.
The MAX5952 continuously flags when the current
exceeds the maximum current allowed for the class as
indicated in the CLASS status register. When class
overcurrent occurs, the MAX5952 sets the IVC bit in
register R09h.
ICUT Register and High-Power Mode
ICUT RegisterThe ICUT register determines the maximum current lim-
its allowed for each port of the MAX5952. The 3 ICUT
bits (R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], and R2Bh[2:0])
allow programming of the current-limit and overcurrent
thresholds in excess of the IEEE standard limit (see
Tables 34a, 34b, and 34c). The ICUT registers can be
written to directly through the I2C interface when
CL_DISC (R17h[2]) is set to 0 (see Table 3). In this
case, the current limit of the port is configured regard-
less of the status of the classification.
By setting the CL_DISC bit to 1, the MAX5952 automati-
cally sets the ICUT register based upon the classifica-
tion result of the port. See Table 3 and the Register
Map and Description section.
Figure 2. PGOOD Timing
PGOOD
POKtPGOOD
Table 3. Automatic ICUT Programming
CL_DISC
PORT
CLASSIFICATION
RESULT
RESULTING ICUT
REGISTER BITSAnyUser programmed1ICUT = 1102ICUT = 1110, 3ICUT = 000
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-EthernetFigure 3a. Foldback Current Characteristics
48V28V
VSU_LIM
VSU_LIM / 3
(VSENSE_ - VEE)
(VOUT_ - VEE)
Figure 3b. Foldback Current Characteristics for High-Power
Mode
48V10V
VSU_LIM
VSU_LIM / 3
(VRS - VEE)
(VOUT_ - VEE)
High-Power ModeWhen CL_DISC (R17h[2]) is set to 0, high-power mode
is configured by setting the ICUT bits to any combina-
tion other than 000, 110, or 111 (note that 000 is the
default value for the IEEE standard limit). See Table 3
and the Register Map and Descriptionsection.
Foldback CurrentDuring startup and normal operation, an internal circuit
senses the voltage at OUT_ and reduces the current-
limit value when (VOUT_ - VEE) > 28V. The foldback
function helps to reduce the power dissipation on the
FET. The current limit eventually reduces to 1/3 of ILIM
when (VOUT_ - VEE ) > 48V (see Figure 3a). For high-
power mode, the foldback starts when (VOUT_ - VEE ) >
10V (see Figure 3b). In high-power mode, the current
limit (ILIM)is reduced up to 1/8 of its programmed value
when (VOUT_ - VEE ) > 48V.
MOSFET Gate DriverConnect the gate of the external n-channel MOSFET to
GATE_. An internal 50µA current source pulls GATE_ to
(VEE+ 10V) to turn on the MOSFET. An internal 40µA
current source pulls down GATE_ to VEEto turn off the
MOSFET.
The pullup and pulldown current controls the maximum
slew rate at the output during turn-on or turn-off. Use
the following equation to set the maximum slew rate:
where CGDis the total capacitance between GATE and
DRAIN of the external MOSFET. Current limit and the
capacitive load at the drain control the slew rate during
startup. During current-limit regulation, the MAX5952
manipulates the GATE_ voltage to control the voltage at
SENSE_ (VRS). A fast pulldown activates if VRSover-
shoots the limit threshold (VSU_LIM). The fast pulldown
current increases with the amount of overshoot. The
maximum fast pulldown current is 100mA.
During turn-off, when the GATE voltage reaches a value
lower than 1.2V, a strong pulldown switch is activated
to keep the MOSFET securely off.
OUTGATE
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Digital LogicVDDsupplies power for the internal logic circuitry. VDD
ranges from +3.0V to +5.5V and determines the logic
thresholds for the CMOS connections (SDAIN,
SDAOUT, SCL, AUTO, SHD_, A_). This voltage range
enables the MAX5952 to interface with a nonisolated
low-voltage microcontroller. The MAX5952 checks the
digital supply for compatibility with the internal logic.
The MAX5952 also features a VDDundervoltage lockout
(VDDUVLO) of +2.0V. A VDDUVLOcondition keeps the
MAX5952 in reset and the ports shut off. Bit 0 in the
supply event register shows the status of VDDUVLO
(Table 12) after VDDhas recovered. All logic inputs and
outputs reference to DGND. DGND and AGND must be
connected together externally. Connect DGND to
AGND at a single point in the system as close as possi-
ble to the MAX5952.
Hardware ShutdownSHD_shuts down the respective ports without using
the serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_low to
remove power. SHD_also resets the corresponding
events and status register bits.
InterruptThe MAX5952 contains an open-drain logic output (INT)
that goes low when an interrupt condition exists. R00h
and R01h (Tables 6 and 7) contain the definitions of the
interrupt registers. The mask register R01h determines
events that trigger an interrupt. As a response to an inter-
rupt, the controller reads the status of the event register
to determine the cause of the interrupt and takes subse-
quent actions. Each interrupt event register also contains
a Clear on Read (CoR) register. Reading through the
CoR register address clears the interrupt. INTremains
low when reading the interrupt through the read-only
addresses. For example, to clear a startup fault on the
port 4 read address 09h (see Table 11). Use the global
pushbutton bit in register 1Ah (bit 7, Table 23) to clear
interrupts, or use a software or hardware reset.
Undervoltage and
Overvoltage ProtectionThe MAX5952 contains several undervoltage and over-
voltage protection features. Table 12 in the Register
Map and Descriptionsection shows a detailed list of
the undervoltage and overvoltage protection features.
An internal VEEundervoltage lockout (VEEUVLO) circuit
keeps the MOSFET off and the MAX5952 in reset until
VAGND - VEEexceeds 29V for more than 3ms. An inter-
nal VEEovervoltage (VEE_OV) circuit shuts down the
ports when (VAGND - VEE) exceeds 60V. The digital
supply also contains an undervoltage lockout
(VDDUVLO). The MAX5952 also features three other
undervoltage and overvoltage interrupts: VEEundervolt-
age interrupt (VEEUV), VDDundervoltage interrupt
(VDDUV), and VDDovervoltage interrupt (VDDOV). A
fault latches into the supply events register (Table 12),
but the MAX5952 does not shut down the ports with
VEEUV, VDDUV, or VDDOV.
DC Disconnect MonitoringSetting R13h[DCD_EN_] bits high enable DC load moni-
toring during a normal powered state. If VRS(the voltage
across RS) falls below the DC load disconnect threshold,
VDCTH, for more than tDISC, the device turns off power
and asserts the LD_DISC_ bit of the corresponding port.
AC Disconnect MonitoringThe MAX5952 features AC load disconnect monitoring.
Connect an external sine wave to OSC. The oscillator
requirements are:VP-P x Frequency = 200VP-Px Hz ±15%Positive peak voltage > +2VFrequency > 60Hz
A 100Hz ±10%, 2VP-P±5%, with +1.2V offset (VPEAK=
+2.2V typical) is recommended.
The MAX5952 buffers and amplifies 3x the external
oscillator signal and sends the signal to DET_, where
the sine wave is AC-coupled to the output. The
MAX5952 senses the presence of the load by monitor-
ing the amplitude of the AC current returned to DET_
(see the Functional Diagram).
Setting R13h[ACD_EN_] bits high enable AC load dis-
connect monitoring during a normal powered state. If
the AC current peak at the DET_ input falls below IACTH
for more than tDISC, the device turns off power and
asserts the LD_DISC_ bit of the corresponding port.
IACTHis programmable using R23h[0-3].
An internal comparator checks for a proper amplitude
of the oscillator input. If the positive peak of the input
sinusoid falls below a safety value of 2V, OSC_FAIL
sets and the port shuts down. Power cannot be applied
to the ports when ACD_EN is set high and OSC_FAIL is
set high. Leave OSC unconnected or connect it to
DGND when not using AC-disconnect detection.
Thermal ShutdownIf the MAX5952 die temperature reaches +150°C, an
overtemperature fault generates and the MAX5952
shuts down. The MOSFETs turn off. The die tempera-
ture of the MAX5952 must cool down below 130°C to
remove the overtemperature fault condition. After a
thermal shutdown, the part is reset.
WatchdogR1Dh, R1Eh, and R1Fh registers control the watchdog
operation. The watchdog function, when enabled, allows
the MAX5952 to gracefully take over control or securely
shuts down the power to the ports in case of software/
firmware crashes. Contact the factory for more details.
Address InputsA3, A2, A1, and A0 represent the four LSBs of the chip
address. The complete chip address is 7 bits (see
Table 4).
The four LSBs latch on the low-to-high transition of RESET
or after a power-supply start (either on VDDor VEE).
Address inputs default high through an internal 50kΩ
pullup resistor to VDD. The MAX5952 also responds to the
call through a global address 30h (see the Global
Addressing and Alert Response Protocolsection).
2C-Compatible Serial InterfaceThe MAX5952 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire or
3-wire interface. The interface uses a serial-data input
line (SDAIN), a serial-data output line (SDAOUT), and a
serial-clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX5952, and generates the SCL clock that
synchronizes the data transfer. In most applications,
connect the SDAIN and the SDAOUT lines together to
form the serial-data line (SDA).
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
The MAX5952 SDAIN line operates as an input. The
MAX5952 SDAOUT operates as an open-drain output. A
pullup resistor, typically 4.7kΩ, is required on SDAOUT.
The MAX5952 SCL line operates only as an input. A
pullup resistor, typically 4.7kΩ, is required on SCL if
there are multiple masters, or if the master in a single-
master system has an open-drain SCL output.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet10A3A2A1A0R/W
Table 4. MAX5952 AddressFigure 4. 2-Wire Serial Interface Timing Details
SCL
SDAIN
tLOW
tHIGHtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITIONSTART CONDITION
tHD, STA
tSU, DAT
tHD, DAT
tSU, STAtHD, STAtSU, STO
Figure 5. 3-Wire Serial Interface Timing Details
SCL
SDAIN/SDA
tLOW
tHIGHtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITIONSTART CONDITION
tHD, STA
tSU, DAT
tHD, DAT
tSU, STAtHD, STAtSU, STO
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Serial AddressingEach transmission consists of a START condition (Figure
6) sent by a master, followed by the MAX5952 7-bit
slave address plus R/Wbit, a register address byte, one
or more data bytes, and finally a STOP condition.
START and STOP ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The STOP condition frees the
bus for another transmission.
Bit TransferEach clock pulse transfers one data bit (Figure 7). The
data on SDA must remain stable while SCL is high.
AcknowledgeThe acknowledge bit is a clocked 9th bit (Figure 8) that
the recipient uses to handshake receipt of each byte of
data. Thus each byte effectively transferred requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA (or the SDAOUT in the 3-wire
interface) during the acknowledge clock pulse, so that
the SDA line is stable low during the high period of the
clock pulse. When the master transmits to the MAX5952,
the MAX5952 generates the acknowledge bit. When the
MAX5952 transmits to the master, the master generates
the acknowledge bit.
Figure 6. START and STOP Conditions
STARTSTOP
SDA/
SDAIN
SCL
Figure 7. Bit Transfer
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF
DATA ALLOWED
Figure 8. Acknowledge
SCL
SDA
BY TRANSMITTER
CLOCK PULSE FOR ACKNOWLEDGEMENTSTART CONDITION
SDA
BY RECEIVER89
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-EthernetFigure 9. Slave Address
SDA
SCL0A3A2A1A00
MSBLSB
ACKR/W
Figure 10. Control Byte ReceivedAP0SLAVE ADDRESSCONTROL BYTE
ACKNOWLEDGE FROM MAX5952
ACKNOWLEDGE FROM MAX5952
D15D14D13D12D11D10D9D8CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
R/W
Slave AddressThe MAX5952 has a 7-bit long slave address (Figure
9). The bit following the 7-bit slave address (bit eight) is
the R/Wbit, which is low for a write command and high
for a read command.
010 always represents the first three bits (MSBs) of the
MAX5952 slave address. Slave address bits A3, A2,
A1, and A0 represent the states of the MAX5952’s A3,
A2, A1, and A0 inputs, allowing up to sixteen MAX5952
devices to share the bus. The states of the A3, A2, A1
and A0 latch in upon the reset of the MAX5952 into reg-
ister R11h. The MAX5952 monitors the bus continuous-
ly, waiting for a START condition followed by the
MAX5952’s slave address. When a MAX5952 recog-
nizes its slave address, the MAX5952 acknowledges
and is then ready for continued communication.
Global Addressing and Alert Response ProtocolThe global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the alert response address. When responding
to a global call, the MAX5952 puts out on the data line
its own address whenever its interrupt is active. So
does every other device connected to the SDAOUT line
that has an active interrupt. After every bit transmitted,
the MAX5952 checks that the data line effectively cor-
responds to the data it is delivering. If it is not, it then
backs off and frees the data line. This litigation protocol
always allows the part with the lowest address to com-
plete the transmission. The microcontroller can then
respond to the interrupt and take proper actions. The
MAX5952 does not reset its own interrupt at the end of
the alert response protocol. The microcontroller has to
do it by clearing the event register through their CoR
adresses or activating the CLR_INT pushbutton.
Message Format for Writing to the MAX5952A write to the MAX5952 comprises of the MAX5952’s
slave address transmission with the R/Wbit set to 0, fol-
lowed by at least one byte of information. The first byte
of information is the command byte (Figure 10). The
command byte determines which register of the
MAX5952 is written to by the next byte, if received. If
the MAX5952 detects a STOP condition after receiving
the command byte, the MAX5952 takes no further
action beyond storing the command byte. Any bytes
received after the command byte are data bytes. The
first data byte goes into the internal register of the
MAX5952 selected by the command byte. If the
MAX5952 transmits multiple data bytes before the
MAX5952 detects a STOP condition, these bytes store
in subsequent MAX5952 internal registers because the
control byte address auto-increments.
MAX5952
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
Message Format for ReadingThe MAX5952 reads using the MAX5952’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5952’s command byte by performing a write (Figure
11). The master now reads ‘n’ consecutive bytes from
the MAX5952, with the first data byte read from the regis-
ter addressed by the initialized command byte (Figure
12). When performing read-after-write verification,
remember to reset the command byte’s address
because the stored control byte address auto-incre-
ments after the write.
Operation with Multiple MastersWhen the MAX5952 operates on a 2-wire interface with
multiple masters, a master reading the MAX5952
should use repeated starts between the write which
sets the MAX5952’s address pointer, and the read(s)
that take the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5952’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5952’s address pointer then master 1’s read may
be from an unexpected location.
Command Address Auto-IncrementingAddress auto-incrementing allows the MAX5952 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5952
generally increments after each data byte is written or
read (Table 5). The MAX5952 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wrap-around of addresses.
Figure 11. Control and Single Data Byte ReceivedAAP0SLAVE ADDRESSCONTROL BYTEDATA BYTE
ACKNOWLEDGE FROM MAX5952
1 BYTE
AUTO-INCREMENT
MEMORY WORD ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
HOW CONTROL BYTE AND DATA BYTE MAP
INTO THE REGISTER
ACKNOWLEDGE FROM MAX5952ACKNOWLEDGE FROM MAX5952
R/W
Figure 12. ‘n’ Data Bytes ReceivedAAP0SLAVE ADDRESSCONTROL BYTEDATA BYTE
ACKNOWLEDGE FROM MAX5952
n BYTES
AUTO-INCREMENT
MEMORY WORD ADDRESS
D15D14D13D12D11D10D9D8D1D0D3D2D5D4D7D6
HOW CONTROL BYTE AND DATA BYTE MAP
INTO THE REGISTER
ACKNOWLEDGE FROM MAX5952ACKNOWLEDGE FROM MAX5952
R/W
Table 5. Auto-Increment Rules
COMMAND BYTE
ADDRESS RANGEAUTO-INCREMENT BEHAVIOR0x00 to 0x26Command address auto-increments
after byte read or written
0x26Command address remains at 0x26
after byte written or read
