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MAX5949AESA+MAXIMN/a3390avai-48V Hot-Swap Controllers with External RSENSE
MAX5949AESA+T |MAX5949AESATMAXIMN/a2416avai-48V Hot-Swap Controllers with External RSENSE
MAX5949BESA+ |MAX5949BESAMAXIMN/a450avai-48V Hot-Swap Controllers with External RSENSE


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MAX5949AESA+-MAX5949AESA+T-MAX5949BESA+
-48V Hot-Swap Controllers with External RSENSE
General Description
The MAX5949A/MAX5949B are hot-swap controllers that
allow a circuit card to be safely hot plugged into a live
backplane. The MAX5949A/MAX5949B operate from
-20V to -80V and are well-suited for -48V power systems.
These devices are pin and function compatible with the
LT4250 and pin compatible with the LT1640.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards preventing glitches on the power-supply
rail and damage to board connectors and components.
The MAX5949A/MAX5949B provide undervoltage, over-
voltage, and overcurrent protection. These devices
ensure the input voltage is stable and within tolerance
before applying power to the load.
Both the MAX5949A and MAX5949B protect a system
against overcurrent and short-circuit conditions by turn-
ing off the external MOSFET in the event of a fault con-
dition. The MAX5949A/MAX5949B also provide
protection against input voltage steps. During an input
voltage step, the MAX5949A/MAX5949B limit the cur-
rent drawn by the load to a safe level without turning off
power to the load.
Both devices feature an open-drain power-good status
output (PWRGDfor the MAX5949A or PWRGD for the
MAX5949B) that can be used to enable downstream
converters.
The MAX5949A/MAX5949B are available in an 8-pin SO
package. Both devices are specified for the extended
-40°C to +85°C temperature range.
Applications

Telecom Line Cards
Network Switches/Routers
Central-Office Line Cards
Server Line Cards
Base-Station Line Cards
Central-Office Switching
-48V Distributed Power Systems
Negative Power-Supply Controls
Features
Allow Safe Board Insertion and Removal
from a Live -48V Backplane
Pin and Function Compatible with LT4250L
(MAX5949A)
Pin Compatible with LT1640L (MAX5949A)Pin and Function Compatible with LT4250H
(MAX5949B)
Pin Compatible with LT1640H (MAX5949B)Circuit-Breaker Immunity to Input Voltage Steps
and Current Spikes
Withstand -100V Input Transients with No
External Components
Programmable Inrush and Short-Circuit Current
Limits
Operate from -20V to -80VProgrammable Overvoltage ProtectionProgrammable Undervoltage LockoutPower Up into a Shorted LoadPower-Good Control Output
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE

GATE
SENSEVEE
VDD
DRAINOV
PWRGD
(PWRGD)
TOP VIEW
MAX5949AMAX5949B
Pin Configuration
Ordering Information

19-3494; Rev 1; 8/11
PARTTEMP RANGEPIN-PACKAGE
MAX5949AESA+
-40°C to +85°C8 SO
MAX5949BESA+
-40°C to +85°C8 SO
Typical Operating Circuit and Selector Guide appear at end
of data sheet.

+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VEE= 0V, VDD= 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 5)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages are referenced to VEE, unless otherwise noted.)
Supply Voltage (VDD- VEE).................................-0.3V to +100V
PWRGD, PWRGD.................................................-0.3V to +100V
DRAIN (Note 1)........................................................-2V to +100V
PWRGD to DRAIN .............................................… -0.3V to +95V
PWRGD to VDD........................................................-95V to +85V
SENSE (Internally Clamped).................................-0.3V to +1.0V
GATE (Internally Clamped)....................................-0.3V to +18V
UV and OV..............................................................-0.3V to +60V
Current Through SENSE...................................................±40mA
Current into GATE...........................................................±300mA
Current into DRAIN.........................................-100mA to +20mA
Current into Any Other Pin................................................±20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)..................471mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIES

Operating Input Voltage RangeVDD2080V
Supply CurrentIDD(Note 3)0.72mA
GATE DRIVE AND CLAMPING CIRCUITS

GATE Pin Pullup CurrentIPUGate drive on, VGATE = VEE-30-45-60µA
GATE Pin Pulldown CurrentIPDGate drive off, VGATE = 2V, TA = +25°C245070mA
External Gate Drive∆VGATEVGATE - VEE, 20V ≤ VDD ≤ 80V1013.518V
GATE to VEE Clamp VoltageVGSCLMPVGATE - VEE, IGS = 30mA1516.418V
CIRCUIT BREAKER

Current-Limit Trip VoltageVCLVCL = VSENSE - VEE405060mV
SENSE Input Bias CurrentISENSEVSENSE = 50mV0-0.2-2µA
UNDERVOLTAGE LOCKOUT

Internal Undervoltage-Lockout
Voltage HighVUVLOHVDD increasing13.815.417.0V
Internal Undervoltage-Lockout
Voltage LowVUVLOLVDD decreasing11.813.415.0V
UV PIN

UV High ThresholdVUVHUV voltage increasing1.2401.2551.270V
UV Low ThresholdVUVLUV voltage decreasing1.1051.1251.145V
UV HysteresisVUVHY130mV
UV Input Bias CurrentIINUVVUV = VEE0-0.5µA
OV PIN

OV High ThresholdVOVHOV voltage increasing1.2351.2551.275V
OV Low ThresholdVOVLOV voltage decreasing1.2101.2351.255V
OV HysteresisVOVHY20mV
Note 1:
Test condition per Figure 1. DRAIN current must be limited to the specified 100mA maximum.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
ELECTRICAL CHARACTERISTICS (continued)

(VEE= 0V, VDD= 48V, TA= -40°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.) (Notes 2, 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN

DRAIN Input Bias CurrentIDRAINVDRAIN = 48V1080250µARAIN Thr eshol d for P ow er - G ood VDLVDRAIN - VEE threshold for power-good
condition, DRAIN decreasing1.11.42.0V
GATE High ThresholdVGH∆VGATE - VGATE threshold for power-good
condition, ∆VGATE - VGATE decreasing1.01.42.0V
PWRGD, PWRGD Output
LeakageIOHPWRGD (MAX5949A) = 80V, VDRAIN = 48V,
PWRGD (MAX5949B) = 80V, VDRAIN = 0V10µA
PWRGD Output Low VoltageVOLV PWRGD - VEE; VDRAIN - VEE < VDL,
ISINK = 5mA (MAX5949A)0.110.4V
PWRGD Output Low VoltageVOLVPWRGD - VDRAIN; VDRAIN = 5V,
ISINK = 1mA (MAX5949B)0.110.4V
AC PARAMETERS

OV High to GATE LowtPHLOVFigures 2a, 30.5µs
UV Low to GATE LowtPHLUVFigures 2a, 40.4µs
OV Low to GATE HightPLHOVFigures 2a, 34µs
UV High to GATE HightPLHVLFigures 2a, 45.5µs
SENSE High to GATE LowtPHLSENSEFigures 2a, 5a13µs
Current Limit to GATE LowtPHLCBFigures 2b, 5b350500650µs
MAX5949A, Figures 2a, 6a1.8DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
tPHLDL
MAX5949B, Figures 2a, 6a3.4
MAX5949A, Figures 2a, 6b1.6GATE High to PWRGD Low
GATE High to (PWRGD - DRAIN)
High
tPHLGH
MAX5949B, Figures 2a, 6b2.5
TURN-OFF

Latch-Off PeriodtOFF(Note 4)516478ms
Note 2:
All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE,
unless otherwise specified.
Note 3:
Current into VDDwith UV = 3V, OV = DRAIN = PWRGD = SENSE = VEE, GATE = open.
Note 4:
Minimum duration of GATE pulldown following a circuit-breaker fault. The circuit breaker can be reset during this time by
toggling UV low, but the GATE pulldown does not release until tOFFhas elapsed.
Note 5:
Limits are 100% tested at TA= +25°C and +85°C. Limits at -40°C are guaranteed by design.
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Typical Operating Characteristics

(VDD= 48V, VEE= 0V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX5949 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (604020
TA = +85°CTA = +25°C
TA = -40°C
GATE VOLTAGE vs. SUPPLY VOLTAGE

MAX5949 toc02
SUPPLY VOLTAGE (V)
GATE VOLTAGE (V)604020
TA = +85°C
TA = -45°CTA = +25°C
CURRENT-LIMIT TRIP VOLTAGE
vs. TEMPERATURE

MAX5949 toc03
TEMPERATURE (°C)
TRIP VOLTAGE (mV)3510-15
GATE PULLUP CURRENT
vs. TEMPERATURE
MAX5949 toc04
TEMPERATURE (°C)
GATE PULLUP CURRENT (3510-15
VGATE = 0V
GATE PULLDOWN CURRENT
vs. TEMPERATURE

MAX5949 toc05
TEMPERATURE (°C)
GATE PULLDOWN CURRENT (mA)3510-15
VGATE = 2V
PWRGD OUTPUT LOW VOLTAGE
vs. TEMPERATURE (MAX5949A)

MAX5920 toc06
PWRGD OUTPUT LOW VOLTAGE (mV)3510-15
IOUT = 1mA
PWRGD OUTPUT IMPEDANCE
vs. TEMPERATURE (MAX5949B)

MAX5949 toc07
OUTPUT IMPEDANCE (G25500-25
10,000
-50100
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSEest Circuits

100mA MAX
MAX5949_
PWRGD/PWRGD
VEE
VDD
DRAINGATE
TEST VOLTAGE
SENSE
Figure 1. -2V DRAIN Voltage Test Circuit
5kΩ
VOV
VUV
VSENSE
VDRAIN
48V
MAX5949A
MAX5949B
PWRGD/PWRGD
VEE
VDD
DRAIN
GATE
SENSE
Figure 2a. Test Circuit 1
VUV
48V
MAX5949A
MAX5949B
PWRGD/PWRGD
VEE
VDD
DRAIN
GATE
SENSE
IRF53020V
10kΩ
10Ω
0.1μF
10Ω
Figure 2b. Test Circuit 2
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Timing Diagrams

1.255VOV
tPHLOV0V
1.235V
tPLHOV
GATE
Figure 3. OV to GATE Timing
tPHLUV
1.125V1V
1.255V
tPLHUV
GATE
Figure 4. UV to GATE Timing
60mV
100mV
GATE
SENSE
VEE
tPHLSENSE
Figure 5a. SENSE to GATE Timing
tPHLCB
50mV
GATE
SENSE1V
Figure 5b. Active Current-Limit Threshold
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE
Timing Diagrams (continued)

DRAIN
PWRGD
VPWRGD - VDRAIN = 0V
PWRGD
DRAIN
VEE
VEE
VEE
tPHLDL
1.4V
1.4V
tPHLDL
Figure 6a. DRAIN to PWRGD/PWRGD Timing
∆VGATE - VGATE = 0V
GATE
PWRGD
VEE
∆VGATE - VGATE = 0V
GATE
PWRGD
VPWRGD - VDRAIN = 0V
1.4V
1.4V
tPHLGH
tPHLGH
Figure 6b. GATE to PWRGD/PWRGD Timing
LOGIC
GATE
DRIVER
500μs
DELAY
UVLOVCC AND
REFERENCE
GENERATOR
REF
VCC
REF
VDL
VEE
VGH
∆VGATE
50mV
VDD
PWRGD
PWRGD
MAX5949A
MAX5949B
OUTPUT DRIVE
Block Diagram
MAX5949A/MAX5949B
Detailed Description

The MAX5949A/MAX5949B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane without
hot-swap control, the bypass capacitors at the input of
the board’s power module or switching power supply
can draw large inrush currents as they charge. The
inrush currents can cause glitches on the system
power-supply rail and damage components on the
board.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards, preventing glitches on the power-supply
rail and damage to board connectors and components.
Both the MAX5949A and MAX5949B provide undervolt-
age, overvoltage, and overcurrent protection. The
MAX5949A/MAX5949B ensure the input voltage is sta-
ble and within tolerance before applying power to the
load. The devices also provide protection against input
voltage steps. During an input voltage step, the
MAX5949A/MAX5949B limit the current drawn by the
load to a safe level without turning off power to the load.
-48V Hot-Swap Controllers
with External RSENSE
Pin Description
PIN
MAX5949AMAX5949BNAMEFUNCTION
PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to VEE. PWRGD is latched low when VDRAIN - VEE ≤ VDL and VGATE > (ΔVGATE - VGH),
indicating a power-good condition. PWRGD is open drain otherwise.1PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD latches in a high-impedance state when VDRAIN - VEE ≤ VDL and
VGATE > (ΔVGATE - VGH), indicating a power-good condition. PWRGD is pulled low to
DRAIN otherwise.OV
Input Pin for Overvoltage Detection. OV is referenced to VEE. When OV is pulled above the
VOVH voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to VOVL.UV
Input Pin for Undervoltage Detection. UV is referenced to VEE. When UV is pulled above the
VUVH voltage, the GATE is enabled. When UV is pulled below VUVL, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below VUVL. The reset command can be issued immediately after a fault
condition; however, the device does not restart until a tOFF delay time has elapsed after
the fault.VEEDevice Negative Power-Supply Input. Connect to the negative power-supply rail.5SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to VEE to disable the current-
limiting feature.6GATEGate-Drive Output. Connect to the gate of the external n-channel MOSFET.7DRAINOutput-Voltage Sense Input. Connect to the output-voltage node (drain of the external
n-channel MOSFET).VDDPositive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the higher potential of the power-supply inputs.
Board Insertion
Figure7a shows a typical hot-swap circuit for -48V sys-
tems. When the circuit board first makes contact with
the backplane, the DRAIN to GATE capacitance (Cgd)
of Q1 pulls up the GATE voltage to roughly IVEE x Cgd /
(Cgd + Cgs)I. The MAX5949_ features an internal
dynamic clamp between GATE and VEEto keep the
gate-to-source voltage of Q1 low during hot insertion,
preventing Q1 from passing an uncontrolled current to
the load. For most applications, the internal dynamic
clamp between GATE and VEEof the MAX5949A/
MAX5949B eliminates the need for an external gate-to-
source capacitor C1. Resistor R3 limits the current into
the clamp circuitry during card insertion.
Power-Supply Ramping

The MAX5949_ can reside either on the backplane or
the removable circuit board (Figure 7a). Power is deliv-
ered to the load by placing an external n-channel
MOSFET pass transistor in the power-supply path.
After the circuit board is inserted into the backplane
and the supply voltage at VEEis stable and within the
undervoltage and overvoltage tolerance, the MAX5949_
turn on Q1. The MAX5949_ gradually turn on the exter-
nal MOSFET by charging the gate of Q1 with a 45µA
current source.
Capacitor C2 provides a feedback signal to accurately
limit the inrush current. The value of C2can be
calculated:
where CLis the total load capacitance, C3 + C4, and
IPUis the MAX5949_ gate pullup current.
Figure7b shows the inrush current waveform. The cur-
rent through C2 controls the GATE voltage. At the end
of the DRAIN ramp, the GATE voltage is charged to its
final value. The GATE-to-SENSE clamp limits the maxi-
mum VGSto about 18V under any condition.
Board Removal

If the card is removed from a live backplane, the output
capacitor on the card may not be immediately dis-
charged. While the output capacitor is discharging, the
MAX5949_ continues to operate as if the input supply
were still connected because the output capacitor tem-
porarily supplies operating current to the IC. If the cir-
cuit is connected as in Figure 7a, the voltage at the UV
pin falls below the VUVL, and the MAX5949_ turns off
the external MOSFET. If R4 in the circuit is connected
directly to the -48V return, the external MOSFET
remains on until the capacitor is discharged sufficiently
to drop the UV pin voltage to VUVL.IxCL
INRUSH2=
MAX5949A/MAX5949B
-48V Hot-Swap Controllers
with External RSENSE

VEESENSEGATEDRAIN
VDD
PWRGD
MAX5949B
-48V RTN
-48V
549kΩ
6.49kΩ
10kΩ
0.02Ω
1kΩ
10Ω
C1**
470nF
25V
IRF530
15nF
100V
GATE IN
VICOR
VI-J3D-CY
VIN+
VIN-
100μF
100V
0.1μF
100V
100μF
10V
10nF
-48V RTN
(SHORT PIN)
*DIODES INC. SMAT70A.
**OPTIONAL.
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