MAX5945EAX ,Quad Network Power Controller for Power-Over-LANApplicationsMIDSPAN 2 35 AUTOINT 3 34 OUT1Power-Sourcing Equipment (PSE)SCL 4 33 GATE1SDAOUT 5 32 S ..
MAX5945EAX+ ,Quad Network Power Controller for Power-Over-LANapplications. The MAX5945 is pin ♦ Wide Digital Power Input, V , Common-ModeDIGand function compati ..
MAX5946AETX ,Dual PCI Express, Hot-Plug Controllerapplications. The device provides hot-♦ Hot Swaps 12V, 3.3V, and 3.3V Auxiliary for 2 plug control ..
MAX5947AESA+ ,Positive High-Voltage, Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = +24V (MAX5947A/B/C), V = +48V (MAX5933A–MAX5933F), GND = 0V, T = -40 ..
MAX5947BESA ,Positive High-Voltage, Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = +24V (MAX5947A/B/C), V = +48V (MAX5933A–MAX5933F), GND = 0V, T = -40 ..
MAX5947BESA+ ,Positive High-Voltage, Hot-Swap Controllersfeatures suchBackplanesas a choice of active-high or active-low power-good out-puts (PWRGD/PWRGD), ..
MAZ8150G ,Silicon planar typeFeatures Package Extremely low noise voltage caused from the diode (2.4 V to Code 39V, 1/3 to 1 ..
MAZ8150-H ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8150-L ,Silicon planar typeFeatures•Extremely low noise voltage caused from the diode (2.4V to 39V,1/3 to 1/10 of our conventi ..
MAZ8150-M ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8160-H ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8160-L ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAX5945CAX-MAX5945EAX
Quad Network Power Controller for Power-Over-LAN
General DescriptionThe MAX5945 quad network power controller is designed
for use in IEEE 802.3af-compliant power-sourcing equip-
ment (PSE). The device provides power devices (PD) dis-
covery, classification, current-limit, and both DC and AC
load disconnect detections. The MAX5945 can be used
in either endpoint PSE (LAN switches/routers) or midspan
PSE (power injector) applications. The MAX5945 is pin
and function compatible with LTC4259A.
The MAX5945 can operate autonomously or be con-
trolled by software through an I2C*-compatible inter-
face. Separate input and output data lines (SDAIN and
SDAOUT) allow usage with optocouplers. The
MAX5945 is a slave device. Its four address inputs
allow 16 unique MAX5945 addresses. A separate INT
output and four independent shutdown inputs (SHD_)
allow fast response from a fault to port shutdown. A
RESETinput allows hardware reset of the device. A
special watchdog feature allows the hardware to grace-
fully take over control if the software crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 is fully software configurable and program-
mable. A class-overcurrent detection function enables
system power management to detect if a PD draws more
current than the allowable amount for its class. Other fea-
tures are input under/overvoltage lockout, overtempera-
ture protection, output-voltage slew-rate limit during
startup, power-good, and fault status. The MAX5945’s
programmability includes gate-charging current, current-
limit threshold, startup timeout, overcurrent timeout,
autorestart duty cycle, PD disconnect AC detection
threshold, and PD disconnect detection timeout.
The MAX5945 is available in a 36-pin SSOP package
and is rated for both extended (-40°C to +85°C) and
commercial (0°C to +70°C) temperature ranges.
ApplicationsPower-Sourcing Equipment (PSE)
Power-Over-LAN/Power-Over-Ethernet
Switches/Routers
Midspan Power Injectors
FeaturesIEEE 802.3af CompliantPin and Function Compatible with LTC4259AControls Four Independent, -48V-Powered
Ethernet Ports in Either Endpoint or Midspan PSE
ApplicationsWide Digital Power Input, VDIG, Common-Mode
Range: VEEto (AGND + 7.7V)PD Violation of Class Current ProtectionPD Detection and ClassificationProvides Both DC and AC Load Removal
DetectionsI2C-Compatible, 3-Wire Serial InterfaceFully Programmable and Configurable Operation
Through I2C InterfaceCurrent Foldback and Duty-Cycle-
Controlled/Programmable Current LimitShort-Circuit Protection with Fast Gate PulldownDirect Fast Shutdown Control CapabilityProgrammable Direct Interrupt OutputWatchdog Mode Enable Hardware Graceful
Takeover
MAX5945
Quad Network Power Controller
for Power-Over-LAN
Pin Configuration19-3428; Rev 1; 9/05
Ordering Information
Typical Operating Circuits appear at end of data sheet.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(Voltages referenced to VEE, unless otherwise noted.)
AGND, DGND, DET_, VDD, RESET, A3, A2, A1, A0, SHD_,
OSC_IN, SCL, SDAIN, OUT_ and AUTO............-0.3V to +80V
GATE_ (internally clamped, Note 1)....................-0.3V to +11.4V
SENSE_..................................................................-0.3V to +24V
VDD, RESET, A3, A2, A1, A0, SHD_, OSC_IN, SCL, SDAIN and
AUTO to DGND....................................................-0.3V to +7V
INTand SDAOUT to DGND....................................-0.3V to +12V
Maximum Current into INT, SDAOUT, DET_.......................80mA
Maximum Power Dissipation
36-Pin SSOP (derate 11.4mW/°C above +70°C).........941mW
Operating Temperature Ranges:
MAX5945EAX..................................................-40°C to +85°C
MAX5945CAX.....................................................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(AGND= +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE,unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
Note 1:GATE_ is internally clamped to 11.4V above VEE. Driving GATE_ higher than 11.4V above VEEmay damage the device.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)(AGND= +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE,unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
MAX5945
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)(AGND= +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE,unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
MAX5945
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)(AGND= +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE,unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
MAX5945
Quad Network Power Controller
for Power-Over-LAN
Note 2:Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and
Description section).
Note 3:Default values. The current-limit thresholds are programmed through the I2C-compatible serial interface (see the Register
Map and Description section).
Note 4:This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 5:AC disconnect works only if VDD- VDGND≥3V.
Note 6:tDISCcan also be programmed through the serial interface (R29h) (see the Register Map and Description section).
Note 7:RD= (VOUT_2 - VOUT_1) / (IDET_2 - IDET_1). VOUT_1, VOUT_2, IDET_2and IDET_1represent the voltage at OUT_ and the current
at DET_ during phase 1 and 2 of the detection.
Note 8:Default values. The startup and fault times can also be programmed through the I2C serial interface (see the Register Map
and Description section).
Note 9:Guaranteed by design. Not subject to production testing.
Typical Operating Characteristics(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, all registers = default setting,= +25°C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)(AGND= +32V to +60V, VEE= 0V, VDDto DGND = +3.3V, all voltages are referenced to VEE,unless otherwise noted. Typical
values are at AGND = +48V, DGND = +48V, VDD= (DGND + 3.3V), TA= +25°C. Currents are positive when entering the pin and
MAX5945
Quad Network Power Controller
for Power-Over-LAN
DIGITAL SUPPLY CURRENT
vs. INPUT VOLTAGEMAX5945 toc04
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
VEE UNDERVOLTAGE LOCKOUT
vs. TEMPERATURE
MAX5945 toc05
TEMPERATURE (°C)
UNDERVOLTAGE LOCKOUT (V)3510-15
GATE OVERDRIVE
vs. INPUT VOLTAGE
MAX5945 toc06
INPUT VOLTAGE (V)
GATE OVERDRIVE (V)52474237
GATE OVERDRIVE
vs. TEMPERATURE
MAX5945 toc07
TEMPERATURE (°C)
GATE OVERDRIVE (V)3510-15
SENSE TRIP VOLTAGE
vs. TEMPERATURE
MAX5945 toc08
TEMPERATURE (°C)
SENSE TRIP VOLTAGE (mV)3510-15
SENSE TRIP VOLTAGE
vs. INPUT VOLTAGE
MAX5945 toc09
INPUT VOLTAGE (V)
SENSE TRIP VOLTAGE (mV)52474237
FOLDBACK CURRENT-LIMIT
THRESHOLD vs. OUTPUT VOLTAGE
MAX5945 toc10
SENSE
- V
(mV)302010
ZERO-CURRENT DETECTION
THRESHOLD vs. TEMPERATURE
MAX5945 toc11
DETECTION THRESHOLD (mV)3510-15
Typical Operating Characteristics (continued)
(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, all registers = default setting,= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
OVERCURRENT TIMEOUT
(RLOAD = 240Ω TO 57Ω)MAX5945 toc12
20ms/div
IOUT
200mA/div
VEE
GATE 10V/div
INT
2V/div
(AGND - OUT)
20V/div
OVERCURRENT RESPONSE WAVEFORM
(RLOAD = 240Ω TO 57Ω)MAX5945 toc13
400µs/div
IOUT
200mA/div
GATE
10V/div
VEE
INT
2V/div
(AGND - OUT)
20V/div
SHORT-CIRCUIT RESPONSE TIMEMAX5945 toc14
20ms/div
IOUT
250mA/div
GATE
10V/div
VEE
(AGND - OUT)
20V/div
SHORT-CIRCUIT RESPONSE TIMEMAX5945 toc15
4µs/div
IOUT
5A/div
GATE
10V/div
VEE
(AGND - OUT)
20V/div
RESET TO OUTPUT TURN-OFF DELAYMAX5945 toc16
100µs/div
IOUT
200mA/div
GATE
10V/div
VEE
RESET
(AGND - OUT)
20V/div
ZERO-CURRENT DETECTION WAVEFORMMAX5945 toc17
100ms/div
IOUT
200mA/div
GATE
10V/div
INT
5V/div
(AGND - OUT)
20V/div
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, all registers = default setting,= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
OVERCURRENT RESTART DELAYMAX5945 toc18
400ms/div
IOUT
200mA/div
GATE
10V/div
VEE
(AGND - OUT)
20V/div
STARTUP WITH VALID PD
(25kΩ AND 0.1µF)MAX5945 toc19
100ms/div
IOUT
100mA/div
GATE_
VEE
(AGND - OUT)
20V/div
DETECTION WITH INVALID PD
(25kΩ AND 10µF)MAX5945 toc20
40ms/div
IOUT
1mA/div
(AGND - OUT)
2V/div
DETECTION WITH INVALID PD (15kΩ)MAX5945 toc21
100ms/div
IOUT
1mA/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (33kΩ)MAX5945 toc22
100ms/div
IOUT
1mA/div
(AGND - OUT)
5V/div
STARTUP IN MIDSPAN MODE
WITH VALID PD (25kΩ AND 0.1µF)MAX5945 toc23
100ms/div
IOUT
100mA/div
VEE
GATE_
10V/div
(AGND - OUT)
20V/div
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, all registers = default setting,= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (15kΩ)MAX5945 toc24
400ms/div
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (33kΩ)MAX5945 toc25
400ms/div
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH OUTPUT SHORTEDMAX5945 toc26
40ms/div
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 1)MAX5945 toc27
100ms/div
IOUT
1mA/div
VEE
GATE_
10V/div
(AGND - OUT)
5V/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 2)MAX5945 toc28
100ms/div
IOUT
2mA/div
GATE_
10V/div
(AGND - OUT)
5V/div
STARTUP WITH DIFFERENT PD CLASSESMAX5945 toc29
40ms/div
IOUT
10mA/div
(AGND - OUT)
5V/div
Typical Operating Characteristics (continued)(VEE= -48V, VDD= +3.3V, AUTO = AGND = DGND = 0V, RESET= SHD_= unconnected, RSENSE= 0.5Ω, all registers = default setting,= +25°C, unless otherwise noted.)
MAX5945
Quad Network Power Controller
for Power-Over-LAN
MAX5945
Detailed DescriptionThe MAX5945 four-port network power controller con-
trols -32V to -60V negative supply rail systems. Use the
MAX5945, which is compliant with the IEEE 802.3af
standard for PSE in power-over-LAN applications. The
MAX5945 provides PD discovery, classification, current
limit, both DC and AC load disconnect detections, and
other necessary functions for an IEEE 802.3af-compli-
ant PSE. The MAX5945 can be used in either endpoint
PSE (LAN switch/router) or midspan PSE (power injec-
tor) applications.
The MAX5945 is fully software-configurable and pro-
grammable with more than 25 internal registers. The
device features an I2C-compatible, 3-wire serial inter-
face and a class-overcurrent detection. The class-over-
current detection function enables system power man-
Quad Network Power Controller
for Power-Over-LAN
agement where it detects a PD that draws more current
than the allowable amount for its class. The MAX5945’s
extensive programmability enhances system flexibility
and allows for uses in other applications.
The MAX5945 has four different operating modes: auto
mode, semi-auto mode, manual mode, and shutdown
mode (see the Operation Modessection). A special
watchdog feature allows the hardware to gracefully
take over control if the software/firmware crashes. A
cadence timing feature allows the MAX5945 to be used
in midspan systems.
The MAX5945 provides input undervoltage lockout,
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output-voltage slew-rate
limit during startup, power-good status, and fault
status. The MAX5945’s programmability includes
gate-charging current, current-limit threshold, startup
timeout, overcurrent timeout, autorestart duty cycle, PD
disconnect AC detection threshold and PD disconnect
detection timeout.
The MAX5945 communicates with the system
microcontroller through an I2C-compatible interface.
The MAX5945 features separate input and output data
lines (SDAIN and SDAOUT) for use with optocoupler
isolation. The MAX5945 is a slave device. Its four
address inputs allow 16 unique MAX5945 addresses. A
separate INToutput and four independent shutdown
inputs (SHD_) allow fast interrupt signals between the
MAX5945 and the microcontroller. A RESETinput
allows hardware reset of the device.
ResetReset is a condition the MAX5945 enters after any of
the following conditions:After power-up (VEEand VDDrise above their UVLO
thresholds).Hardware reset. The RESETinput is driven low and
up high again any time after power-up.Software reset. Writing a 1 into R1Ah[4] any time
after power-up.Thermal shutdown.
During a reset, the MAX5945 resets its register map to
the reset state as shown in Table 30 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, changes at the AUTO and MIDSPAN
inputs are ignored. While the condition that caused the
reset persists (i.e., high temperature, RESETinput low,
or UVLO conditions) the MAX5945 will not acknowl-
edge any addressing from the serial interface.
Port Reset (R1Ah[3:0])Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
Operation ModesThe MAX5945 contains four independent but identical
state machines to provide reliable and real-time control
of the four network ports. Each state machine has four
different operating modes: auto, semi-auto, manual,
and shutdown. Auto mode allows the device to operate
automatically without any software supervision. Semi-
auto mode, upon request, continuously detects and
classifies a device connected to a port but does not
power up that port until instructed by software. Manual
mode allows total software control of the device and is
useful in system diagnostic. Shutdown mode terminates
all activities and securelyturns off power to the ports.
Switching between AUTO, SEMI, or MANUAL mode
does not take effect until the part finishes its current
task. When the port is setinto SHUTDOWN mode, all
the port operations are immediately stopped and the
port remains idle until SHUTDOWN is exited.
Automatic (AUTO) ModeEnter automatic (AUTO) mode by forcing the
AUTO input high prior to a reset, or by setting
R12h[P_ M1,P_M0] to [1,1] during normal operation
(see Tables 15 and 15a). In AUTO mode, the MAX5945
performs detection, classification, and powers up the
port automatically once a valid PD is detected at the
port. If a valid PD is not detected at the port, the
MAX5945 repeats the detection routine continuously
until a valid PD is detected.
Going into AUTO mode, the DET_EN and CLASS_EN
bits are set to high and stay high unless changed by
software. Using software to set DET_EN and/or
CLASS_EN low causes the MAX5945 to skip detection
and/or classification. As a protection, disabling the
detection routine in AUTO mode will not allow the corre-
sponding port to power up, unless the DET_BYP
(R23H[4]) is set to 1.
The AUTO status is latched into the register only during
a reset. Any changes to the AUTO input after reset is
ignored.
Semi-Automatic (SEMI) ModeEnter semi-automatic (SEMI) mode by setting
R12h[P_M1,P_M0] to [1,0] during normal operation
(see Tables 15 and 15a). In SEMI mode, the MAX5945,
upon request, performs detection and/or classification
repeatedly but does not power up the port(s), regard-
MAX5945
Quad Network Power Controller
for Power-Over-LAN
MAX5945Setting R19h[PWR_ON_] (Table 21) high immediately
terminates detection/classification routines and turns on
power to the port(s).
R14h[DET_EN_, CLASS_EN_] default to low in SEMI
mode. Use software to set R14h[DET_EN_,
CLASS_EN_] to high to start the detection and/or classi-
fication routines. R14h[DET_EN_, CLASS_EN_] are
reset every time the software commands a power-off of
the port (either through reset or PWR_OFF). In any other
case, the status of the bits is left unchanged (including
when the state machine turns off the power because a
load disconnect or a fault condition is encountered).
MANUAL ModeEnter MANUAL mode by setting R12h[P_M1,P_M0] to
[0,1] during normal operation (see Tables 15 and 15a).
MANUAL mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_ EN_]
and R14h[CLASS_EN_] start detection and classifica-
tion operations, respectively, and in that priority order.
After execution, the command is cleared from the regis-
ter(s). PWR_ON_ has highest priority.Setting PWR_ON_
high at any time causes the device to immediately enter
the powered mode. Setting DET_EN and CLASS_EN
high at the same time causes detection to be per-
formed first. Once in the powered state, the device
ignores DET_EN_ or CLASS_EN_ commands.
When switching to MANUAL mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become pushbutton rather than configuration bits (i.e.,
writing ones to these bits while in MANUAL mode com-
mands the device to execute one cycle of detection
and/or classification. The bits are reset back to zeros at
the end of the execution). Putting the MAX5945 into
shutdown mode immediately turns off power and halts
all operations to the corresponding port. The event and
status bits of the affected port(s) are also cleared. In
SHUTDOWN mode, the DET_EN_, CLASS_EN_, and
PWR_ON_ commands are ignored.
In SHUTDOWN mode, the serial interface operates
normally.
WatchdogR1Dh, R1Eh, and R1Fh registers control watchdog oper-
ation. The watchdog function, when enabled, allows the
MAX5945 to gracefully take over control or securely shut
down the power to the ports in case of software/firmware
crashes. Contact the factory for more details.
PD DetectionWhen PD detection is activated, the MAX5945 probes
the output for a valid PD. After each detection cycle,
the device sets the DET_END_ bit R04h/05h[3:0] high
and reports the detection results in the status registers
R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The
DET_END_ bit is reset to low when read through R05h
or after a port reset. Both DET_END_ bit status registers
are cleared after the port powers down.
A valid PD has a 25kΩdiscovery signature characteris-
tic as specified in the IEEE 802.3af standard. Table 1
shows the IEEE 802.3af specification for a PSE detect-
ing a valid PD signature (see the Typical Application
Circuit and Figure 2). The MAX5945 can probe and cat-
egorize different types of devices connected to the port
such as a valid PD, an open circuit, a low resistive load,
a high resistive load, a high capacitive load, a positive
DC supply, or a negative DC supply.
During detection, the MAX5945 turns off the external
MOSFET and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5945 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
An external diode, in series with the DET_ input,
restricts PD detection to the 1st quadrant as specified
by the IEEE 802.3af standard. To prevent damage to
non-PD devices and to protect itself from an output
short circuit, the MAX5945 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5945 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
Power Device Classification
(PD Classification)During the PD classification mode, the MAX5945 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both Class_END_ bit status registers are
cleared after the port powers down.
Quad Network Power Controller
for Power-Over-LAN
Table 2 shows the IEEE 802.3af requirement for a PSE
classifying a PD at the power interface (PI).
Powered StateWhen the part enters PWR MODE, the tSTARTand tDISC
checks if any other port is not turning on and if the
tFAULTtimer is zero. Another check is performed if the
ACD_EN bit is set, in this case OSC_FAIL bit must be
low (oscillator is okay) for the port to be powered.
If these conditions are met then the part enters startup
where it turns on power to the port. An internal signal,
POK_, is asserted high when VOUTis within 2V from
VEE. PGOOD_ status bits are set high if POK_ stays
high longer than tPGOOD. PGOOD immediately resets
when POK goes low.
The PWR_CHG bit sets when a port powers up or down.
PWR_EN sets when a port powers up and resets when a
port shuts down. The port shutdown timer lasts 0.5ms
and prevents other ports from turning off during that peri-
od, except in the case of emergency shutdowns (RESET
= L, RESET_IC = H, VEEUVLO, VDDUVLO, and TSHD).
The MAX5945 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., port 1 turns on first, port 2 second, port 3
third and port 4 fourth). Setting PWR_OFF_ high turns off
MAX5945
Quad Network Power Controller
for Power-Over-LAN
MAX5945
Overcurrent ProtectionA sense resistor (RS), connected between SENSE_ and
VEE, monitors the load current. Under all circum-
stances, the voltage across RSnever exceeds the
threshold VSU_LIM. If SENSE_ exceeds VSU_LIM, an
internal current-limiting circuit regulates the GATE volt-
age, limiting the current to ILIM= VSU_LIM / RS. During
transient conditions, if the SENSE_ voltage exceeds
VSU_LIM, a fast pulldown circuit activates to quickly
recover from the current overshoot. During startup, if
the current-limit condition persists, when the startup
timer, tSTART, times out, the port shuts off and the
STRT_FLT_ bit is set. In normal powered state, the
MAX5945 checks for overcurrent conditions as deter-
mined by VFLT_LIM= ~88% of VSU_LIM. The tFAULT
counter sets the maximum allowed continuous
overcurrent period. The tFAULTcounter increases when
VSENSE exceeds VFLT_LIMand decreases at a slower
pace when VSENSE drops below VFLT_LIM. A slower
decrement for the tFAULTcounter allows for detecting
repeated short-duration overcurrents. When the counter
reaches the tFAULTlimit, the MAX5945 powers off the
port and asserts the IMAX_FLT_ bit. For a continuous
overstress, a fault latches exactly after a period of
tFAULT. VSU_LIM, is programmable using R27h[4-7].
tFAULTis programmable using R16h[2-3] and R28[4-7].
After power-off due to an overcurrent fault, and if the
RSTR_EN bit is set, the tFAULTtimer is not immediately
reset but starts decrementing at the same slower pace.
The MAX5945 allows the port to be powered on only
when the tFAULTcounter is at zero. This feature sets an
automatic duty-cycle protection to the external MOSFET
to avoid overheating. The duty cycle is programmable
using R16h[6-7].
The MAX5945 continuously flags when the current
exceeds the maximum current allowed for the class as
indicated in the CLASS status register. When class
overcurrent occurs, the MAX5945 sets the IVC bit in
register R09h.
Foldback CurrentDuring startup and normal operation, an internal circuit
senses the voltage at OUT_ and reduces the current-
limit value when (VOUT_ - VEE) > 30V. The foldback
function helps to reduce the power dissipation on the
FET. The current limit eventually reduces to 1/3 of ILIM
when (VOUT_ - VEE) > 50V (see Figure 4).
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MOSFET Gate DriverConnect the gate of the external n-channel MOSFET to
GATE_. An internal 50µA current source pulls GATE_ to
(VEE+ 10V) to turn on the MOSFET. An internal 40µA
current source pulls down GATE_ to VEEto turn off the
MOSFET.
The pullup and pulldown current controls the maximum
slew rate at the output during turn-on or turn-off. The
pullup current (gate-charging current) is programmable
using R23h[5-7]. Use the following equation to set the
maximum slew rate:
where CGDis the total capacitance between GATE and
DRAIN of the external FET. Current limit and the capac-
itive load at the drain control the slew rate during start-
up. During current-limit regulation, the MAX5945
manipulates the GATE_ voltage to control the voltage at
SENSE_. A fast pulldown activates if SENSE_ over-
shoots the limit threshold. The fast pulldown current
increases with the amount of overshoot. The maximum
fast pulldown current is 100mA.
During turn-off, when the GATE voltage reaches a value
lower than 1.2V, a strong pulldown switch is activated
to keep the FET securely off.
Digital LogicVDDsupplies power for the internal logic circuitry. VDD
ranges from +1.71V to +3.7V and determines the logic
thresholds for the CMOS connections (SDAIN,
SDAOUT, SCL, AUTO, SHD_, A_). This voltage range
enables the MAX5945 to interface with a nonisolated
digital supply for compatibility with the internal logic.
The MAX5945 also features a VDDundervoltage lockout
(VDDUVLO) of +1.35V. A VDDUVLOcondition keeps the
MAX5945 in reset and the ports shut off. Bit 0 in the
supply event register shows the status of VDDUVLO
(Table 11) after VDDhas recovered. All logic inputs and
outputs reference to DGND. DGND and AGND are
completely isolated internally to the MAX5945. In a
completely isolated system, the digital signal can be
referenced indifferently to VAGNDor VEEor at voltages
even higher than AGND (up to 60V). VDD- VDGNDmust
be greater than 3.0V when VDGND≤(VEE+ 3.0V)
When using the AC disconnect detection feature,
AGND must be connected directly to DGND and VDD
must be greater than +3V. In this configuration, con-
nect DGND to AGND at a single point in the system as
close to MAX5945 as possible.
Hardware ShutdownSHD_shuts down the respective ports without using
the serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_low to
remove power.
InterruptThe MAX5945 contains an open-drain logic output (INT)
that goes low when an interrupt condition exists. R00h
and R01h (Tables 5 and 6) contain the definitions of the
interrupt registers. The mask register R01h determines
events that trigger an interrupt. As a response to an
interrupt, the controller reads the status of the event reg-
ister to determine the cause of the interrupt and takes
subsequent actions. Each interrupt event register also
contains a clear-on-read (CoR) register. Reading
through the CoR register address clears the interrupt.INTremains low when reading the interrupt through the
read-only addresses. For example, to clear a startup
fault on port 4 read address 09h (see Table 10). Use the
global pushbutton bit on register 1Ah (bit 7, Table 22) to
clear interrupts, or use a software or hardware reset.
Undervoltage and Overvoltage ProtectionThe MAX5945 contains several undervoltage and over-
voltage protection features. Table 11 in the Register Map
and Descriptionsection shows a detailed list of the
undervoltage and overvoltage protection features. An
internal VEEundervoltage lockout (VEEUVLO) circuit
keeps the MOSFET off and the MAX5945 in reset until
VAGND- VEEexceeds 29V for more than 3ms. An internal
VEEovervoltage (VEE_OV) circuit shuts down the ports
when (VAGND- VEE) exceeds 60V. The digital supply also
contains an undervoltage lockout (VDDUVLO).
MAX5945
Quad Network Power Controller
for Power-Over-LAN
MAX5945The MAX5945 also features three other undervoltage
and overvoltage interrupts: VEEundervoltage interrupt
(VEEUV), VDDundervoltage interrupt (VDDUV), and VDD
overvoltage interrupt (VDDOV). A fault latches into the
supply events register (Table 11) but the MAX5945 does
not shut down the ports with a VEEUV, VDDUV, or VDDOV.
DC Disconnect MonitoringSetting R13h[DCD_EN_] bits high enable DC load mon-
itoring during a normal powered state. If SENSE_ falls
below the DC load disconnect threshold, VDCTH, for
more than tDISC, the device turns off power and asserts
the LD_DISC_ bit of the corresponding port. tDISCis
programmable using R16h[0-1] and R27h[0-3].
AC Disconnect MonitoringThe MAX5945 features AC load disconnect monitoring.
Connect an external sine wave to OSC_IN. The oscilla-
tor requirements are:Frequency x VP-P= 200VP-Px Hz ±15%Positive peak voltage > +2VFrequency > 60HzA 100Hz ±10%, 2VP-P±5%, with +1.2V offset
(VPEAK= +2.2V, typ) is recommended.
The MAX5945 buffers and amplifies 3x the external
oscillator signal and sends the signal to DET_, where
the sine wave is AC coupled to the output. The
MAX5945 senses the presence of the load by monitor-
ing the amplitude of the AC current returned to DET_
(see the Functional Diagram).
Setting R13h[ACD_EN_] bits high enable AC load dis-
connect monitoring during the normal powered state. If
the AC current peak at the DET_ pin falls below IACTH
for more than tDISC, the device turns off power and
asserts the LD_DISC_ bit of the corresponding port.
IACTHis programmable using R23h[0-3].
An internal comparator checks for a proper amplitude
of the oscillator input. If the positive peak of the input
sinusoid falls below a safety value of 2V, OSC_FAIL
sets and the port shuts down. Power cannot be applied
to the ports when ACD_EN is set high and OSC_FAIL is
set high. Leave OSC_IN unconnected or connect it to
DGND when not using AC disconnect detection.
When using the AC disconnect detection feature, con-
nect AGND directly to DNGD as close as possible to
the IC. The MAX5945 also requires a VDDof greater
than +3V for this function. See the Typical Application
Circuitwith AC disconnect for other external compo-
nent requirements.
Thermal ShutdownIf the MAX5945 die temperature reaches +150°C, an
overtemperature fault generates and the MAX5945
shuts down and the MOSFETs turn off. The die temper-
ature of the MAX5945 must cool down below +130°C to
remove the overtemperature fault condition. After a
thermal shutdown, the part is reset.
Address InputsA3, A2, A1, and A0 represent the four LSBs of the chip
address, the complete 7-bit chip address (see Table 3).
The four LSBs latch on the low-to-high transition ofRESETor after a power-supply start (either on VDDor
VEE). Address inputs default high through an internal
50kΩpullup resistor to VDD. The MAX5945 also
responds to the call through a global address 60h (see
the Global Addressing and Alert Response Protocol
section).
2C-Compatible Serial InterfaceThe MAX5945 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire or 3-
wire interface. The interface uses a serial data input line
(SDAIN), a serial data output line (SDAOUT), and a ser-
ial clock line (SCL) to achieve bidirectional communica-
tion between master(s) and slave(s). A master (typically
a microcontroller) initiates all data transfers to and from
the MAX5945, and generates the SCL clock that syn-
chronizes the data transfer. In most applications, con-
nect the SDAIN and the SDAOUT lines together to form
the serial data line (SDA).
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
The MAX5945 SDAIN line operates as an input. The
MAX5945 SDAOUT operates as an open-drain output.
A pullup resistor, typically 4.7kΩ, is required on
SDAOUT. The MAX5945 SCL line operates only as an
input. A pullup resistor, typically 4.7kΩ, is required on
SCL if there are multiple masters, or if the master in a
single-master system has an open-drain SCL output.
Serial AddressingEach transmission consists of a START condition (Figure
7) sent by a master, followed by the MAX5945 7-bit slave
address plus R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
Quad Network Power Controller
for Power-Over-LAN
Start and Stop ConditionsBoth SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The stop condition frees the bus
for another transmission.
MAX5945
Quad Network Power Controller
for Power-Over-LAN
MAX5945
Bit TransferEach clock pulse transfers one data bit (Figure 8). The
data on SDA must remain stable while SCL is high.
AcknowledgeThe acknowledge bit is a clocked 9th bit (Figure 9),
which the recipient uses as a handshake receipt of each
byte of data. Thus each byte effectively transferred
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA (or the SDAOUT
in the 3-wire interface) during the acknowledge clock
pulse, so the SDA line is stable low during the high peri-
od of the clock pulse. When the master transmits to the
MAX5945, the MAX5945 generates the acknowledge bit.
When the MAX5945 transmits to the master, the master
generates the acknowledge bit.
Slave AddressThe MAX5945 has a 7-bit long slave address (Figure
10). The bit following the 7-bit slave address (bit eight)
is the R/W bit, which is low for a write command and
high for a read command.
010 always represent the first three bits (MSBs) of the
MAX5945 slave address. Slave address bits A3, A2,
A1, and A0 represent the states of the MAX5945’s A3,
A2, A1, and A0 inputs, allowing up to sixteen MAX5945
devices to share the bus. The states of the A3, A2, A1,
and A0 latch in upon the reset of the MAX5945 into reg-
ister R11h. The MAX5945 monitors the bus continuous-
ly, waiting for a START condition followed by the
MAX5945’s slave address. When the MAX5945 recog-
nizes its slave address, it acknowledges and is then
ready for continued communication.
Global Addressing and Alert Response ProtocolThe global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the alert response address. When responding to
a global call, the MAX5945 puts out on the data line its
own address whenever its interrupt is active and so does
every other device connected to the SDAOUT line that
has an active interrupt. After every bit is transmitted, the
MAX5945 checks that the data line effectively corre-
sponds to the data it is delivering. If it is not, it then backs
off and frees the data line. This litigation protocol always
allows the part with the lowest address to complete the
transmission. The microcontroller can then respond to
the interrupt and take proper actions. The MAX5945
does not reset its own interrupt at the end of the alert
response protocol. The microcontroller has to do it by
clearing the event register through their CoR addresses
or activating the CLR_INT pushbutton.
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Message Format for Writing the MAX5945A write to the MAX5945 comprises of the MAX5945’s
slave address transmission with the R/W bit set to 0, fol-
lowed by at least one byte of information. The first byte
of information is the command byte (Figure 11). The
command byte determines which register of the
MAX5945 is written to by the next byte, if received. If
the MAX5945 detects a STOP condition after receiving
the command byte, then the MAX5945 takes no further
action beyond storing the command byte. Any bytes
received after the command byte are data bytes. The
first data byte goes into the internal register of the
MAX5945 selected by the command byte. If the
MAX5945 transmits multiple data bytes before the
MAX5945 detects a STOP condition, these bytes store
in subsequent MAX5945 internal registers because the
control byte address auto-increments.
Any bytes received after the control byte are data
bytes. The first data byte goes into the internal register
of the MAX5945 selected by the control byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are stored in subse-
quent MAX5945 internal registers because the control
byte address auto-increments.
MAX5945
Quad Network Power Controller
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MAX5945
Message Format for ReadingThe MAX5945 reads using the MAX5945’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5945’s command byte by performing a write
(Figure 12). The master now reads ‘n’ consecutive
bytes from the MAX5945, with the first data byte read
from the register addressed by the initialized command
byte (Figure 13). When performing read-after-write veri-
fication, remember to reset the command byte’s
address because the stored control byte address auto-
increments after the write.
Operation with Multiple MastersWhen the MAX5945 operates on a 2-wire interface with
multiple masters, a master reading the MAX5945
should use repeated starts between the write that sets
the MAX5945’s address pointer, and the read(s) that
takes the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5945’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5945’s address pointer then master 1’s read may
be from an unexpected location.
Command Address Auto-IncrementingAddress auto-incrementing allows the MAX5945 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5945
generally increments after each data byte is written or
read (Table 4). The MAX5945 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wrap-around of addresses.
Register Map And DescriptionThe interrupt register (Table 5) summarizes the event
register status and is used to send an interrupt signal
(INTgoes low) to the controller. Writing a 1 to R1Ah[7]
clears all interrupt and events registers. A reset sets
R00h to 00h.
INT_EN (R17h[7]) is a global interrupt mask (Table 6).
The MASK_ bits activate the corresponding interrupt
bits in register R00h. Writing a 0 to INT_EN (R17h[7])
disables the INToutput.
A reset sets R01h to AAA00A00b, where A is the state
of the AUTO input prior to the reset.
The power event register (Table 7)records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content will
be cleared. A reset sets R02h/R03h = 00h.
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port.
A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1
in any of the DET_END_ bits forces R00h[3] to 1. As
with any other events register, the detect event register
(Table 8)has two addresses. When read through the
R04h address, the content of the register is left
unchanged. When read through the CoR R05h
address, the register content will be cleared. A reset
sets R04h/R05h = 00h.
LD_DISC_ is set high whenever the corresponding port
shuts down due to detection of load removal.
IMAX_FLT_ is set high when the port shuts down due to
an extended overcurrent event after a successful start-
up. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1.
A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1.
As with any of the other events register, the fault event
register (Table 9)has two addresses. When read
through the R06h address, the content of the register is
left unchanged. When read through the CoR R07h
address, the register content will be cleared. A reset
sets R06h/R07h = 00h.
Quad Network Power Controller
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