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MAX5895EGK+D |MAX5895EGKDMAXIMN/a100avai16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs


MAX5895EGK+D ,16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894 14 500 CMOSBase Stations: 3G Multicarrier UMTS, CDMA, and GSMMAX5895 16 500 CMO ..
MAX5898EGK+D ,16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS InputsApplicationsBase Stations: 3G Multicarrier UMTS, CDMA, and GSMSimplified DiagramBroadband Wireless ..
MAX5900AAETT+T ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersApplications Pin ConfigurationTelecom Line Cards Network Switches Requires No External Sense Resis ..
MAX5900AAEUT-T ,100 V, SOT23 simple swapper hot-swap controllerELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAX5900ABEUT+ ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAX5900ACEUT+T ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersELECTRICAL CHARACTERISTICS(V = -9V to -100V, GND = 0, ON/OFF open circuit, T = -40°C to +85°C, unle ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8056-M ,Silicon planar typeFeatures•Extremely low noise voltage caused from the diode (2.4V to 39V,1/3 to 1/10 of our conventi ..
MAZ8062 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8062 ,Small-signal deviceElectrical Characteristics T = 25°C aParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8062-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..


MAX5895EGK+D
16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS Inputs
General Description
The MAX5895 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for
high-performance, wideband single- and multicarrier
transmit applications. The device integrates a selectable
2x/4x/8x interpolating filter, a digital quadrature modula-
tor, and dual 16-bit high-speed DACs on a single IC. At
30MHz output frequency and 500Msps update rate, the
in-band SFDR is 88dBc while consuming 1.1W. The
device also delivers 71dB ACLR for four-carrier WCDMA
at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease
reconstruction filter requirements and enhance the
passband dynamic performance. Individual offset and
gain programmability allow the user to calibrate out local
oscillator (LO) feedthrough and sideband suppression
errors generated by analog quadrature modulators.
The MAX5895 features a fIM/4 digital image-reject mod-
ulator. This modulator generates a quadrature-modulat-
ed IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM/2 or fIM/4.
The MAX5895 features a standard 1.8V CMOS, 3.3V tol-
erant data input bus for easy interface. A 3.3V SPI™ port
is provided for mode configuration. The programmable
modes include the selection of 2x/4x/8x interpolating fil-
ters, fIM/2, fIM/4 or no digital quadrature modulation with
image rejection, channel gain and offset adjustment, and
offset binary or two’s complement data interface.
Pin-compatible 12- and 14-bit devices are also available.
Refer to the MAX5894 data sheet for the 14-bit version
and the MAX5893 data sheet for the 12-bit version.
Applications

Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
Features
71dB ACLR at fOUT= 61.44MHz (Four-Carrier
WCDMA)
Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (fOUT= 122MHz)
Noise Spectral Density = -158dBFS/Hz at
fOUT= 16MHz
92dBc SFDR at Low-IF Frequency (10MHz)90dBc SFDR at High-IF Frequency (50MHz)Low Power: 511mW (fCLK= 100MHz)User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 99dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM/2, or
fIM/4
Selectable Output Filter: Lowpass or Highpass
Channel Gain and Offset Adjustment
EV Kit Available (Order the MAX5895 EV Kit)
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
PARTRESOLUTION
(BITS)
DAC UPDATE
RATE (Msps)
INPUT
LOGIC

MAX589312500CMOS
MAX589414500CMOS
MAX589516500CMOS
MAX589816500LVDS
PARTTEMP RANGEPIN-PACKAGE

MAX5895EGK-D-40°C to +85°C68 QFN-EP*
MAX5895EGK+D-40°C to +85°C68 QFN-EP*
Selector Guide
Ordering Information

A SYNCH
AND DEMUX
DACDATA
PORT A
DATA
PORT B
DATACLK
OUTI
OUTQ
MODULA
TOR
INTERPOLA
TING
FIL
TERS
1x/2x/4x
INTERPOLA
TING
FIL
TERS
DAC
Simplified Diagram

19-3545; Rev 2; 10/08
Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of the Telecommunications
Industry Association.
D = Dry pack.
*EP = Exposed pad.
+Denotes a lead-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DVDD1.8, AVDD1.8to GND, DACREF..................-0.3V to +2.16V
AVDD3.3, AVCLK, DVDD3.3to GND, DACREF........-0.3V to +3.9V
DATACLK, A0–A15, B0–B13,
SELIQ/B15, DATACLK/B14, CS, RESET, SCLK,
SDI and SDO to GND, DACREF......-0.3V to (DVDD3.3+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK+ 0.3V)
REFIO, FSADJ to GND, DACREF........-0.3V to (AVDD3.3+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AVDD3.3+ 0.3V)
SDO, DATACLK, DATACLK/B14 Continuous Current..........8mA
Continuous Power Dissipation (TA= +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1)...................................................................3333.3mW
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Thermal Resistance θJC(Note 1)....................................0.8°C/W
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCE

Resolution16Bits
Differential NonlinearityDNL±1LSB
Integral NonlinearityINL±3LSB
Offset ErrorOS-0.025±0.003+0.025%FS
Offset Drift±0.03ppm/°C
Full-Scale Gain ErrorGEFS-4±0.6+4%FS
Gain-Error Drift±110ppm/°C
Full-Scale Output CurrentIOUTFS220mA
Output Compliance-0.5+1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCE

Maximum Clock FrequencyfCLK500MHz
Minimum Clock FrequencyfCLK1MHz
Maximum DAC Update RatefDACfDAC = fCLK or fDAC = fCLK/2500Msps
Minimum DAC Update RatefDACfDAC = fCLK or fDAC = fCLK/21Msps
Maximum Input Data RatefDATA125MWps
No interpolation-157
2x interpolation-158
fDATACLK = 125MHz,
fOUT = 16MHz, fOFFSET
= 10MHz, -12dBFS4x interpolation-157Noise Spectral Density
fDATACLK = 125MHz,
fOUT = 16MHz, fOFFSET
= 10MHz, 0dBFS
4x interpolation-149
dBFS/
Note 1:
Thermal resistance based on a multilayer board with 4 x 4 via array in exposed pad area.
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

fOUT = 10MHz90
fOUT = 30MHz85fDATACLK = 125MHz,
interpolation off, 0dBFS
fOUT = 50MHz73
fOUT = 10MHz7790
fOUT = 30MHz89fDATACLK = 125MHz,
2x interpolation, 0dBFS
fOUT = 50MHz86
fOUT = 10MHz92
fOUT = 30MHz88
In-Band SFDR
(DC to fDATA/2)SFDR
fDATACLK = 125MHz,
4x interpolation, 0dBFS
fOUT = 50MHz90
dBc
No interpolation-103
2x interpolation-103
fDATACLK = 125MHz,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS4x interpolation-103
2x interpolation,
fIM/4 complex
modulation
fDATACLK = 125MHz,
fOUT1 = 79MHz, fOUT2
= 80MHz, -6.1dBFS4x interpolation,
fIM/4 complex
modulation
fDATACLK = 62.5MHz,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS
8x interpolation-100
fDATACLK = 62.5MHz,
fOUT1 = 69MHz, fOUT2
= 70MHz, -6.1dBFS
8x interpolation,
fIM/4 complex
modulation
Two-Tone IMDTTIMD
fDATACLK = 62.5MHz,
fOUT1 = 179MHz, fOUT2
= 180MHz, -6.1dBFS
8x, highpass
interpolation,
fIM/4 complex
modulation
dBc
Four-Tone IMDFTIMD
fDATACLK = 125MHz, fOUT spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
-97dBc
4x interpolation80fDATACLK = 61.44MHz,
fOUT = baseband8x interpolation79
fDATACLK =
122.88MHz, fOUT =
61.44MHz
2x interpolation,
fIM/4 complex
modulationACLR for WCDMA
(Note 3)ACLR
fDATACLK =
122.88MHz, fOUT =
122.88MHz
4x interpolation,
fIM/4 complex
modulation
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Output Propagation DelaytPD1x interpolation (Note 4)2.9ns
Output Rise TimetRISE10% to 90% (Note 5)0.75ns
Output Fall TimetFALL10% to 90% (Note 5)1.0ns
Output Settling TimeTo 0.5% (Note 5)11ns
Output Bandwidth-1dB bandwidth (Note 6)240MHz
Passband WidthRipple < -0.01dB0.4 x
fDATA
0.604 x fDATA, 2x interpolation100
0.604 x fDATA, 4x interpolation100Stopband Rejection
0.604 x fDATA, 8x interpolation100
1x interpolation22
2x interpolation70
4x interpolation146Data Latency
8x interpolation311
Clock
Cycles
DAC INTERCHANNEL MATCHING

Gain Match∆GainfOUT = DC - 80MHz, IOUTFS = 20mA±0.1dB
Gain-Match Tempco∆Gain/°CIOUTFS = 20mA±0.02ppm/°C
Phase Match∆PhasefOUT = 60MHz, IOUTFS = 20mA±0.13Deg
Phase-Match Tempco∆Phase/°CfOUT = 60MHz, IOUTFS = 20mA±0.006Deg/°C
DC Gain MatchIOUTFS = 20mA-0.2±0.04+0.2dB
Channel-to-Channel CrosstalkfOUT = 50MHz, fDAC = 250MHz, 0dBFS-95dB
REFERENCE

Reference Input Range0.1251.250V
Reference Output VoltageVREFIOInternal reference1.141.201.27V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage Drift±50ppm/°C
CMOS LOGIC INPUT/OUTPUT (A15–A0, SELIQ/B15, DATACLK/B14, B13–B0, DATACLK)

Input High VoltageVIH0.7 x
DVDD1.8V
Input Low VoltageVIL0.3 x
DVDD1.8V
Input CurrentIIN±1±20µA
Input CapacitanceCIN3pF
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Output High VoltageVOH200µA load0.8 xV D D 3 .3V
Output Low VoltageVOL200µA load0.2 xV D D 3.3V
Output Leakage CurrentThree-state1µA
Rise/Fall TimeCLOAD = 10pF, 20% to 80%1.5ns
CLOCK INPUT (CLKP, CLKN)

Sine-wave input> 1.5Differential Input Voltage SwingVDIFFSquare-wave input> 0.5VP-P
Differential Input Slew Rate> 100V/µs
Common-Mode VoltageVCOMAC-coupledAVCLK/2V
Input ResistanceRCLK5kΩ
Input CapacitanceCCLK3pF
Minimum Clock Duty Cycle45%
Maximum Clock Duty Cycle55%
CLKP/CLKN, DATACLK TIMING (Figure 4, Notes 7, 8)

CLK to DATACLK DelaytDDATACLK output mode, CLOAD = 10pF6.2ns
Capturing rising edge1.0Data Hold Time, DATACLK
Input/Output (Pin 14)tDHCapturing falling edge2.1ns
Capturing rising edge0.4Data Setup Time, DATACLK
Input/Output (Pin 14)tDSCapturing falling edge-0.7ns
Capturing rising edge1.0Data Hold Time, DATACLK/B14
Input/Output (Pin 27)tDHCapturing falling edge2.3ns
Capturing rising edge0.2Data Setup Time, DATACLK/B14
Input/Output (Pin 27)tDSCapturing falling edge-0.4ns
SERIAL-PORT INTERFACE TIMING (Figure 3, Note 7)

SCLK FrequencyfSCLK10MHz
CS Setup TimetSS2.5ns
Input Hold TimetSDH0ns
Input Setup TimetSDS4.5ns
Data Valid DurationtSDV6.516.5ns
ELECTRICAL CHARACTERISTICS (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIES

Digital Supply VoltageDVDD1.81.711.81.89V
Digital I/O Supply VoltageDVDD3.33.03.33.6V
Clock Supply VoltageAVCLK3.1353.33.465V
AVDD3.33.1353.33.465Analog Supply VoltageAVDD1.81.711.81.89V
IAVDD3.3fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz, DATACLK output mode110130
Analog Supply Current
IAVDD1.8fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz, DATACLK output mode2732
Digital Supply CurrentIDVDD1.8fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz, DATACLK output mode225250mA
Digital I/O Supply CurrentIDVDD3.3fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz, DATACLK output mode2132mA
Clock Supply CurrentIAVCLKfCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz, DATACLK output mode35mA
Total Power DissipationPTOTAL511mW
AVDD3.3450
AVDD1.81
DVDD1.810
DVDD3.3100
Power-Down Current
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
AVCLK1
AVDD3.3 Power-Supply Rejection
RatioPSRRA(Note 9)0.125%FS/V
ELECTRICAL CHARACTERISTICS (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ωdouble-terminated outputs, external reference at 1.25V, TA= -40°C to +85°C, unless otherwise noted. Typical values are
at TA= +25°C, unless otherwise noted.) (Note 2)
Note 2:
All specifications are 100% tested at TA≥+25°C. Specifications at TA< +25°C are guaranteed by design and
characterization data.
Note 3:
3.84MHz bandwidth, single carrier.
Note 4:
Excludes data latency.
Note 5:
Measured single-ended into a 50Ωload.
Note 6:
Excludes sin(x)/x rolloff.
Note 7:
Guaranteed by design and characterization.
Note 8:
Setup and hold time specifications characterized with 3.3V CMOS logic levels.
Note 9:
Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, NO INTERPOLATION

MAX5895 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)40302010
-0.1dBFS
-12dBFS-0.1dBFS
-6dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 2x INTERPOLATION

MAX5895 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
-0.1dBFS-6dBFS
-12dBFS
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 2x INTERPOLATION

MAX5895 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 2x INTERPOLATION

MAX5895 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-6dBFS
-0.1dBFS-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 4x INTERPOLATION

MAX5895 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
-0.1dBFS-6dBFS
-12dBFS
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 4x INTERPOLATION

MAX5895 toc06
OUTPUT FREQUENCY (MHz)
SFDR (dBc)302010
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
-6dBFS-0.1dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 4x INTERPOLATION

MAX5895 toc07
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
-0.1dBFS
-6dBFS
-12dBFS
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125MWps, 4x INTERPOLATION

MAX5895 toc08
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 187.5MHz
-6dBFS-0.1dBFS
-12dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125MWps, NO INTERPOLATION

MAX5895 toc09
TWO-TONE IMD (-dBc)302010
1MHz CARRIER SPACING
-12dBFS
-6dBFS
-9dBFS
Typical Operating Characteristics

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125MWps, NO INTERPOLATION

MAX5895 toc09
CENTER FREQUENCY (MHz)
TWO-TONE IMD (-dBc)302010
1MHz CARRIER SPACING
-12dBFS
-6dBFS
-9dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125MWps, 4x INTERPOLATION

MAX5895 toc11
CENTER FREQUENCY (MHz)
TWO-TONE IMD (-dBc)
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-12dBFS
-6dBFS
-9dBFS
GAIN MISMATCH vs. TEMPERATURE
fDATA = 125MWps, 2x INTERPOLATION

MAX5895 toc12
TEMPERATURE (°C)
GAIN MISMATCH (dB)3510-15
fOUT = 22.7MHz
AOUT = -6dBFS
MULTITONE POWER RATIO PLOT
fDATA = 125MWps, 2x INTERPOLATION

MAX5895 toc13
OUTPUT POWER (dBm)
fCENTER = 35.7MHz, 1MHz TONE SPACING
AOUT1 THROUGH AOUT8 = -18dBFS,
SPAN = 25MHz
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE

MAX5895 toc14
DIGITAL INPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5895 toc15
INL (LSB)
DIGITAL INPUT CODE
SUPPLY CURRENTS vs. DAC UPDATE RATE
2x INTERPOLATION, fOUT = 5MHz

MAX5895 toc16
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENTS vs. DAC UPDATE RATE
4x INTERPOLATION, fOUT = 5MHz

MAX5895 toc17
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
SUPPLY CURRENTS vs. DAC UPDATE RATE
8x INTERPOLATION, fOUT = 5MHz

MAX5895 toc18
SUPPLY CURRENT (mA)
1.8V TOTAL
3.3V TOTAL
Typical Operating Characteristics (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
NOISE DENSITY vs. DAC UPDATE RATE
fOUT = 16MHz, 10MHz OFFSET

MAX5895 toc19
fDAC (MHz)
NOISE DENSITY (dBFS/Hz)
2x, 4x, AND 8x INTERPOLATION
AOUT = -12dBFS
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 122.88MWps, 4x INTERPOLATION

MAX5895 toc20
fCENTER (MHz)
ACLR (dB)
SINGLE-CARRIER
ALTERNATE CHANNEL
SINGLE-CARRIER
ADJACENT CHANNEL
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 76.8MWps, 4x INTERPOLATION

MAX5895 toc21
fCENTER (MHz)
ACLR (dB)40
SINGLE-CARRIER
ALTERNATE CHANNEL
SINGLE-CARRIER
ADJACENT CHANNEL
FOUR-CARRIER
ALTERNATE CHANNEL
FOUR-CARRIER
ADJACENT CHANNEL
MAX5895 toc22
OUTPUT POWER (dBm)
WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44MWps, 8x INTERPOLATION
fCENTER = 61.44MHz, SPAN = 25.5MHz
ACLR2 = 77dBACLR1 = 76dBCARRIER = -11dBmACLR1 = 75dBACLR2 = 76dB
FOUR-CARRIER WCDMA ACLR SPECTRAL PLO
fDATA = 61.44MWps, 8x INTERPOLATION

MAX5895 toc23
OUTPUT POWER (dBm)
fCENTER = 61.44MHz, SPAN = 40.6MHz
ACLR2 = 74dBACLR1 = 73dBCARRIER = -17dBmACLR1 = 72dBACLR2 = 72dB
WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88MWps, 4x INTERPOLATION

MAX5895 toc24
OUTPUT POWER (dBm)
fCENTER = 122.88MHz, SPAN = 25.5MHz
ACLR2 = 73dBACLR1 = 71dBCARRIER = -14dBmACLR1 = 70dBACLR2 = 72dB
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88MWps, 4x INTERPOLATION

MAX5895 toc25
OUTPUT POWER (dBm)
fCENTER = 122.88MHz, SPAN = 40.6MHz
ACLR2 = 67dBACLR1 = 66dBCARRIER = -20dBmACLR1 = 66dBACLR2 = 67dB
Typical Operating Characteristics (continued)

(DVDD1.8= AVDD1.8= 1.8V, AVCLK= AVDD3.3= DVDD3.3= 3.3V, modulator off, 2x interpolation, output is transformer-coupled to
50Ωload, TA= +25°C, unless otherwise noted.)
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Pin Description
PINNAMEFUNCTION
CLKPNoninverting Differential Clock InputCLKNInverting Differential Clock Input
3, 4, 5N.C.Internally Connected. Do not connect.
6, 21, 30, 37DVDD1.8Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
7–12, 15–20,
22–25A15–A0
A-Port Data Inputs.
Dual-port mode:
I-channel data input. Data is latched on the rising/falling edge (programmable) of the DATACLK.
Single-port mode:
I-channel and Q-channel data input, with SELIQ.
13, 44DVDD3.3CMOS I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.DATACLKProgrammable Data Clock Input/Output. See the DATACLK Modes section for details.SELIQ/B15
Select I/Q-Channel Input or B-Port MSB Input.
Single-port mode:
If SELIQ = LOW, data is latched into Q-channel on the rising/falling edge (programmable) of
the DATACLK.
If SELIQ = HIGH, data is latched into I-channel on the rising/falling edge (programmable) of the
DATACLK.
Dual-port mode:
Q-channel MSB input.DATACLK/B14
Alternate DATACLK Input/Output or B-Port Bit 14 Input.
Single-port mode:
See the DATACLK Modes section for details.
Dual-port mode:
Q-channel bit 14 input.
If unused connect to GND.
28, 29, 31–36,
38–43B13–B0
B-Port Data Bits 13–0.
Dual-port mode:
Q-channel inputs. Data is latched on the rising/falling (programmable) edge of the DATACLK.
Single-port mode:
Connect to GND.SDOSerial-Port Data OutputSDISerial-Port Data InputSCLKSerial-Port Clock Input. Data on SDI is latched on the rising edge of SCLK.CSSerial-Port Interface Select. Drive CS low to enable serial-port interface.RESETReset Input. Set RESET low during power-up.REFIOReference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground
connection.
FSADJFull-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF.
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Pin Description (continued)
Functional Diagram
PINNAMEFUNCTION

53, 67AVDD1.8Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
54, 56, 59, 61,
64, 66GNDGround
55, 60, 65AVDD3.3Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.OUTQNInverting Differential DAC Current Output for Q-ChannelOUTQPNoninverting Differential DAC Current Output for Q-ChannelOUTINInverting Differential DAC Current Output for I-ChannelOUTIPNoninverting Differential DAC Current Output for I-ChannelAVCLKClock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.EPExposed Pad. Must be connected to GND through a low-impedance path.
IDAC
OUTIP
OUTIN
QDAC
OUTQP
OUTQN
SELIQ
A0–A15
B0–B15
DATACLK
SERIAL INTERFACE
CONTROL REGISTERS
REFERENCE
MODULATOR
CLOCK BUFFERS
AND DIVIDERS
CLKPCLKN
RESET
fCLK
fDAC
fDAC
DAT
A SYNCHAND DEMUX
MUXII
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
INTERPOLA
TING
FIL
TER
MUX
MUX
MUX
DIGITAL
OFFSET
ADJUST
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST/2
SDOSDICSSCLKDACREFFSADJREFIO∑
fIM/2, fIM/4
DIGITAL
GAIN
ADJUST/2
MAX5895
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Detailed Description

The MAX5895 dual, 500Msps, high-speed, 16-bit, cur-
rent-output DAC provides superior performance in
communication systems requiring low-distortion ana-
log-signal reconstruction. The MAX5895 combines two
DAC cores with 8x/4x/2x/1x programmable digital inter-
polation filters, a digital quadrature modulator, an SPI-
compatible serial interface for programming the device,
and an on-chip 1.20V reference. The full-scale output
current range is programmable from 2mA to 20mA to
optimize power dissipation and gain control.
Each channel contains three selectable interpolating fil-
ters making the MAX5895 capable of 1x, 2x, 4x, or 8x
interpolation, which allows for low-input and high-out-
put data rates. When operating in 8x interpolation
mode, the interpolator increases the DAC conversion
rate by a factor of eight, providing an eight-fold
increase in separation between the reconstructed
waveform spectrum and its first image. The MAX5895
accepts either two’s complement or offset binary input
data format and can operate from either a single- or
dual-port input bus.
The MAX5895 includes modulation modes at fIM/2 and
fIM/4, where fIMis the data rate at the input of the modula-
tor. If 2x interpolation is used, this data rate is 2x the input
data rate. If 4x or 8x interpolation is used, this data rate is
4x the input data rate. Table 1 summarizes the modulator
operating data rates for dual-port mode.
The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultane-
ously will automatically power down the digital interpo-
lator filters. Note the SPI section is always active.
The analog and digital sections of the MAX5895 have
separate power-supply inputs (AVDD3.3, AVDD1.8,
AVCLK, DVDD3.3, and DVDD1.8), which minimize noise
coupling from one supply to the other. AVDD1.8and
DVDD1.8operate from a typical 1.8V supply, and all
other supply inputs operate from a typical 3.3V supply.
Serial Interface

The SPI-compatible serial interface programs the
MAX5895 registers. The serial interface consists of the
CS, SDI, SCLK, and SDO. Data is shifted into SDI on
the rising edge of the SCLK when CSis low. When CS
is high, data presented at SDI is ignored and SDO is in
high-impedance mode.Note: CSmust transition high
after each read/write operation.
SDO is the serial data
output for reading registers to facilitate easy debug-
ging during development. SDI and SDO can be con-
nected together to form a 3-wire serial interface bus or
remain separate and form a 4-wire SPI bus.
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5895 only. The second byte is a data
byte and can be written to or read from the MAX5895.
Table1. Quadrature Modulator Operating Data Rates (fIMis the Data Rate at the Input of
the Modulator) for Dual-Port Mode
INTERPOLATION RATEMODULATION MODE (fLO)MODULATION FREQUENCY
RELATIVE TO fDAC
MODULATION FREQUENCY
RELATIVE TO fDATA

fIM/2fDAC/2fDATA/21xfIM/4fDAC/4fDATA/4
fIM/2fDAC/2fDATA2xfIM/4fDAC/4fDATA/2
fIM/2fDAC/22 x fDATA4xfIM/4fDAC/4fDATA
fIM/2fDAC/42 x fDATA8xfIM/4fDAC/8fDATA
When writing to the MAX5895, data is shifted into SDI;
data is shifted out of SDO in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-
first mode, both the control byte and data byte are shifted
LSB in first. Figures 1 and 2 show the SPI serial interface
operation in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

Figure1. SPI Serial Interface Write Cycle, MSB-First Mode
SCLK
SDI
SDO003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N - 1
DATA N - 2003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N
DATA N - 1003210
HIGH
IMPEDANCE
IGNORED
ADDRESSDATA
READ CYCLE N + 1
DATA N000A3A2A1A0D7D6D5D4D3D2D1D0
SCLK
SDI
SDOHIGH IMPEDANCE
Figure2. SPI Serial Interface Read Cycle, MSB-First Mode
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs

tSS
SCLK
SDI
tSDStSDH
tSDV
SDO
Figure3. SPI Serial-Interface Timing Diagram
MAX5895
Programming Registers

Programming its registers with the SPI serial interface
sets the MAX5895 operation modes. Table2 shows all
of the registers. The following are descriptions of each
register.
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
ADDBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

00hUnused0 = MSB first
1 = LSB first
Software Reset
0 = Normal

1 = Reset all
registers
Interpolator
Power-Down
0 = Normal

1 = Power-down
IDAC Power-
Down
0 = Normal

1 = Power-down
QDAC Power-
Down
0 = Normal

1 = Power-down
Unused
01h
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation

Third
Interpolation
Filter
Configuration
0 = Lowpass

1 = Highpass
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = fIM/2
10 = fIM/4

11 = fIM/4
Mixer Modulation
Mode
0 = Complex
1 = Real

Modulation
Sign
0 = e-jω

1 = e+jω
Unused
02h
0 = Two’s
complement
input data

1 = Offset
binary input
data
0 = Single
port (A),
interleaved
I/Q

1 = Dual port
I/Q input
0 = Clock output
on DATACLK

1 = Clock output
on DATA CLK/B14
0 = Input data
latched on
rising clock
edge

1 = Input data
latched on falling
clock edge
0 = Data clock
input enabled

1 = Data clock
output enabled
Data
Synchronizer
0 = Enabled

1 = Disabled
Unused
03hUnused
04h8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
05hUnused4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
06h10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in 07h register. Default: 000h
07h
IDAC IOFFSET
Direction
0 = Current on
OUTIN

1 = Current on
OUTIP
Unused
IDAC Offset
Adjustment
Bit 1
(see 06h
register)
IDAC Offset
Adjustment
Bit 0
(see 06h
register)
08h8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
09hUnused4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
0Ah10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in 0Bh register. Default: 000h
0Bh
QDAC
IOFFSET
Direction
0 = Current on
OUTQN

1 = Current on
OUTQP
Unused
QDAC Offset
Adjustment
Bit 1
(see 0Ah
register)
QDAC Offset
Adjustment
Bit 0
(see 0Ah
register)
0ChReserved, do not write to these bits.
0DhReserved, do not write to these bits.
0EhReserved, do not write to these bits.
Table2. MAX5895 Programmable Registers

Conditions in boldare default states after reset.
MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
Address 00h

Bit 6Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port will use LSB first
address/data format.
Bit 5When set to a logic 1, all registers reset to
their default state (this bit included).
Bit 4Logic 1 stops the clock to the digital interpo-
lators. DAC outputs hold last value prior to
interpolator power-down.
Bit 3IDAC power-down mode. A logic 1 to this bit
powers down the IDAC.
Bit 2QDAC power-down mode. A logic 1 to this bit
powers down the QDAC.
Note:
If both bit 2 and bit 3 are 1, the MAX5895 is in
full-power-down mode, leaving only the serial interface
active.
Address 01h

Bits 7, 6Configure the interpolation filters according
to the following table:1x (no interpolation)2x4x8x (default)
Bit 5Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Bits 4, 3Configure the modulation frequency accord-
ing to the following table:No modulationfIM/2 modulationfIM/4 modulation (default)fIM/4 modulation
where fIMis the data rate at the input of the
modulator.
Bit 2Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only avail-
able for fIM/4 modulation.
Bit 1 Quadrature modulator sign inversion. With I-
channel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw(default), cancelling the upper image
when used with an external quadrature mod-
ulator. A logic 1 sets the complex modulation
to be e+jw, cancelling the lower image when
used with an external quadrature modulator.
Address 02h

Bit 7Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Bit 6Logic 0 (default) configures the data bus for
single-port, interleaved I/Q data. I and Q data
enter through one 16-bit bus. Logic 1 config-
ures the data bus for dual-port I/Q data. I and
Q data enter on separate buses.
Bit 5Logic 0 (default) configures the data clock
for pin 14. A logic 1 configures the data clock
for pin 27 (DATACLK/B14).
Bit 4Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Bit 3Logic 0 (default) configures the DATACLK
pin (pin 14 or pin 27) to be an input. A logic 1
configures the DATACLK pin to be an output.
Bit 2Logic 0 (default) enables the data synchro-
nizer circuitry. A logic 1 disables the data
synchronizer circuitry.
Address 03h

Bits 7–0Unused.
Address 04h

Bits 7–0These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustmentsection). Bit
7 is the MSB. Default is all zeros.
Address 05h

Bits 3–0These four bits define the binary number for
the coarse-gain adjustment of the IDAC full-
scale current (see the Gain Adjustmentsec-
tion). Bit 3 is the MSB. Default is all ones.
Address 06h, Bits 7 to 0; Address 07h, Bit 1 and Bit 0

These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
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