MAX5891EGK+D ,16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS InputsApplicationsFunctional Diagram● Base Stations: Single/Multicarrier UMTS, CDMA, GSM● Communication ..
MAX5894EGK+D ,14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894 14 500 CMOSBase Stations: 3G UMTS, CDMA, and GSMMAX5895 16 500 CMOSBroadband Wi ..
MAX5895EGK ,16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894** 14 500 CMOSBase Stations: 3G Multicarrier UMTS, CDMA, and GSMMAX5895 16 500 C ..
MAX5895EGK+D ,16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894 14 500 CMOSBase Stations: 3G Multicarrier UMTS, CDMA, and GSMMAX5895 16 500 CMO ..
MAX5898EGK+D ,16-Bit, 500Msps, Interpolating and Modulating Dual DAC with Interleaved LVDS InputsApplicationsBase Stations: 3G Multicarrier UMTS, CDMA, and GSMSimplified DiagramBroadband Wireless ..
MAX5900AAETT+T ,-100V, SOT23/TDFN, Simple Swapper Hot-Swap ControllersApplications Pin ConfigurationTelecom Line Cards Network Switches Requires No External Sense Resis ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8056-M ,Silicon planar typeFeatures•Extremely low noise voltage caused from the diode (2.4V to 39V,1/3 to 1/10 of our conventi ..
MAZ8062 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8062 ,Small-signal deviceElectrical Characteristics T = 25°C aParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8062-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAX5891EGK+D
16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
General DescriptionThe MAX5891 advanced 16-bit, 600Msps, digital-to-
analog converter (DAC) meets the demanding perfor-
mance requirements of signal synthesis applications
found in wireless base stations and other communications
applications. Operating from 3.3V and 1.8V supplies, the
MAX5891 DAC supports update rates of 600Msps using
high-speed LVDS inputs while consuming only 298mW
of power and offers exceptional dynamic performance
such as 80dBc spurious-free dynamic range (SFDR) at
fOUT = 30MHz.
The MAX5891 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal levels with a double-terminated 50Ω load. The MAX5891
features an integrated 1.2V bandgap reference and
control amplifier to ensure high-accuracy and low-noise
performance. A separate reference input (REFIO) allows
for the use of an external reference source for optimum
flexibility and improved gain accuracy.
The MAX5891 digital inputs accept LVDS voltage levels,
and the flexible clock input can be driven differentially or
single-ended, AC- or DC-coupled. The MAX5891 is avail-
able in a 68-pin QFN package with an exposed paddle
(EP) and is specified for the extended (-40°C to +85°C)
temperature range.
Refer to the MAX5890 and MAX5889 data sheets for pin-
compatible 14-bit and 12-bit versions of the MAX5891.
Applications●Base Stations: Single/Multicarrier UMTS, CDMA, GSM●Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave●Direct Digital Synthesis (DDS)●Cable Modem Termination Systems (CMTS)●Automated Test Equipment (ATE)●Instrumentation
Features●600Msps Output Update Rate●Low Noise Spectral Density: -163dBFS/Hz at
fOUT = 36MHz●Excellent SFDR and IMD Performance SFDR = 80dBc at fOUT = 30MHz (to Nyquist) SFDR = 71dBc at fOUT = 130MHz (to Nyquist) IMD = -95dBc at fOUT = 30MHz IMD = -70dBc at fOUT = 130MHz●ACLR = 73dB at fOUT = 122.88MHz●2mA to 20mA Full-Scale Output Current●LVDS-Compatible Digital Inputs●On-Chip 1.2V Bandgap Reference●Low 298mW Power Dissipation at 600Msps●Compact (10mm x 10mm) QFN-EP Package●Evaluation Kit Available (MAX5891EVKIT)
Pin Configuration appears at end of data sheet.*EP = Exposed paddle.
+ = Lead-free package.
D = Dry pack.
PARTTEMP RANGEPIN-PACKAGEPKG
CODEMAX5891EGK-D-40°C to +85°C68 QFN-EP*G6800-4
MAX5891EGK+D-40°C to +85°C68 QFN-EP*G6800-4
PARTRESOLUTION
(BITS)
UPDATE RATE
(Msps)LOGIC INPUTMAX588912600LVDS
MAX589014600LVDS
MAX589116600LVDS
MAX58911.2V
REFERENCE
REFIO
DACREF
FSADJ
CLK
INTERFACE
600MHz
16-BIT DACLATCHLVDS
RECEIVER
D0–D15
LVDS DATA
INPUTS
POWER
DOWN
CLKP
CLKN
OUTP
OUTN
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Functional Diagram
Selector Guide
Ordering Information
EVALUATION KIT AVAILABLE
AVDD1.8, DVDD1.8 to AGND, DGND, DACREF,
and CGND ......................................................-0.3V to +2.16V
AVDD3.3, DVDD3.3, AVCLK to AGND, DGND,
DACREF, and CGND........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND .........................-0.3V to (AVDD3.3 + 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND ......................................-1.2V to (AVDD3.3 + 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND ........................................-0.3V to (AVCLK + 0.3V)
PD to AGND, DGND, DACREF,
and CGND .....................................-0.3V to (DVDD3.3 + 0.3V)
Digital Data Inputs (D0N–D15N, D0P–D15P) to AGND,
DGND, DACREF, and CGND ........-0.3V to (DVDD1.8 + 0.3V)
Continuous Power Dissipation (TA = +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C) ..3333mWThermal Resistance θJA (Note 1) ...................................24°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed
by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.)
Note 1: Thermal resistance based on a multilayer board with 4x4 via array in exposed paddle area.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution16Bits
Integral NonlinearityINLMeasured differentially±3.8LSB
Differential NonlinearityDNLMeasured differentially±2.8LSB
Offset ErrorOS-0.02±0.001+0.02%FS
Full-Scale Gain ErrorGEFSExternal reference-4±1+4%FS
Gain-Drift TempcoInternal reference±130ppm/°CExternal reference±100
Full-Scale Output CurrentIOUT220mA
Output ComplianceSingle-ended-1.0+1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
Output Leakage CurrentPD = high, power-down mode±1µA
DYNAMIC PERFORMANCEMaximum DAC Update Rate600Msps
Minimum DAC Update Rate1Msps
Noise Spectral DensityN
fCLK = 500MHz,
-12dBFS, 20MHz
offset from the
carrier
fOUT = 36MHz
AFULL-SCALE = -3.5dBm-163
dBFS/Hz
fOUT = 151MHz
AFULL-SCALE = -6.4dBm-155
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed
by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSpurious-Free
Dynamic Range to
Nyquist
SFDR
fCLK = 200MHz,
0dBFS (Note 2)
fOUT = 16MHz89
dBc
fOUT = 30MHz85
fCLK = 200MHz,
-12dBFS (Note 2)
fOUT = 16MHz79
fOUT = 30MHz81
fCLK = 500MHz,
0dBFS
fOUT = 16MHz (Note 3)7681
fOUT = 30MHz (Note 2)80
fOUT = 130MHz (Note 2)71
fOUT = 200MHz (Note 2)56
Two-Tone IMDTTIMD
fCLK = 500MHz
fOUT1 = 29MHz,
fOUT2 = 30MHz,
-6.5dBFS per tone
dBc
fCLK = 500MHz
fOUT1 = 129MHz,
fOUT2 = 130MHz,
-6.5dBFS per tone
Adjacent Channel
Leakage Power RatioACLR
WCDMA single
carrier
fCLK = 491.52MHz,
fOUT = 30.72MHz82
fCLK = 491.52MHz,
fOUT = 122.88MHz73
WCDMA four
carriers
fCLK = 491.52MHz,
fOUT = 30.72MHz74
fCLK = 491.52MHz,
fOUT = 122.88MHz67
Output BandwidthBW-1dB(Note 4)1000MHz
REFERENCEInternal Reference Voltage RangeVREFIO1.141.21.26V
Reference Input Voltage RangeVREFIOCRUsing external reference0.101.21.32V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage Temperature
DriftTCOREF±30ppm/°C
ANALOG OUTPUT TIMING (Figure 3)Output Fall TimetFALL90% to 10% (Note 5)0.4ns
Output Rise TimetRISE10% to 90% (Note 5)0.4ns
Output Propagation DelaytPDReference to data latency (Note 5)2.5ns
Output Settling TimeTo 0.025% of the inal value (Note 5)11ns
Glitch ImpulseMeasured differentially1pV●s
Output NoiseNOUTIOUT = 2mA 30pA/√HzIOUT = 20mA30
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Electrical Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed
by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICSInput Data Rate600Mwps
Data Latency5.5Clock
cycles
Data to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 6)-1.5ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 6)2.6ns
Clock FrequencyfCLKCLKP, CLKN600MHz
Minimum Clock Pulse-Width HightCHCLKP, CLKN0.6ns
Minimum Clock Pulse-Width LowtCLCLKP, CLKN0.6ns
Turn-On TimetSHDNExternal reference, PD falling edge to output
settle within 1%350µs
CMOS LOGIC INPUT (PD)Input Logic High VIH0.7 x
DVDD3.3V
Input Logic LowVIL0.3 x
DVDD3.3V
Input CurrentIIN-10±1.8+10µA
Input CapacitanceCIN3pF
LVDS INPUTSDifferential Input HighVIHLVDS(Notes 6, 7, 8)+100+1000mV
Differential Input LowVILLVDS(Notes 6, 7, 8)-1000-100mV
Internal Common-Mode BiasVICMLVDS1.1251.375V
External Common-Mode ToleranceVECMLVDS(Notes 6, 8)0.8VDD1.8
- 0.15V
Differential Input ResistanceRIDLVDS110Ω
Common-Mode Input ResistanceRICMLVDS3.2kΩ
Input CapacitanceCINLVDS3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)Clock Common-Mode VoltageCLKP and CLKN are internally biasedAVCLK/2V
Minimum Differential Input
Voltage Swing0.5VP-P
Minimum Common-Mode Voltage1V
Maximum Common-Mode Voltage1.9V
Input ResistanceRCLKSingle-ended5kΩ
Input CapacitanceCCLK3pF
POWER SUPPLIESAnalog Supply Voltage RangeAVDD3.33.1353.33.465V
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Electrical Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = -40°C to +85°C, unless otherwise noted. Specifications at TA ≥ +25°C are guaranteed
by production testing. Specifications at TA < +25°C are guaranteed by design and characterization. Typical values are at TA = +25°C.)
Note 2: Parameter tested with input data pattern based on 16,384 data points. fOUT has been chosen so the corresponding input
pattern contains prime number of fOUT cycles and is a nonrepetitive sequence. fOUT has been rounded to the nearest MHz
number in both the Electrical Characteristics table and Typical Operating Characteristics.
Note 3: Parameter tested exactly at fOUT = 16.204833984375MHz and with a clock frequency of 500MHz at an output amplitude of 0dBFS.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5891.
Note 5: Parameter measured single-ended with 50Ω double-terminated outputs.
Note 6: Not production tested. Guaranteed by design.
Note 7: Differential input voltage defined as VD_P - VD_N.
VD_N
VD_P
VIHLVDSVILLVDS
Note 8: Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDigital Supply Voltage RangeDVDD3.33.1353.33.465VDVDD1.81.7101.81.890
Analog Supply Current
IAVDD3.3
fCLK = 100MHz, fOUT = 16MHz 26.5
fCLK = 500MHz, fOUT = 16MHz26.528.5
fCLK = 600MHz, fOUT = 16MHz26.5
IAVDD1.8
fCLK = 100MHz, fOUT = 16MHz11.3
fCLK = 500MHz, fOUT = 16MHz5058
fCLK = 600MHz, fOUT = 16MHz61
Clock Supply CurrentIAVCLK
fCLK = 100MHz, fOUT = 16MHz2.8fCLK = 500MHz, fOUT = 16MHz2.83.6
fCLK = 600MHz, fOUT = 16MHz2.8
Digital Supply Current
IDVDD3.3
fCLK = 100MHz, fOUT = 16MHz0.2
fCLK = 500MHz, fOUT = 16MHz0.20.5
fCLK = 600MHz, fOUT = 16MHz0.2
IDVDD1.8
fCLK = 100MHz, fOUT = 16MHz10.6
fCLK = 500MHz, fOUT = 16MHz4450
fCLK = 600MHz, fOUT = 16MHz50.5
Total Power DissipationPDISS
fCLK = 100MHz, fOUT = 16MHz137fCLK = 500MHz, fOUT = 16MHz267301
fCLK = 600MHz, fOUT = 16MHz298
Power-down, clock static low,
data input static13µW
Power-Supply Rejection RatioPSRR(Note 9)±0.025%FS
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Electrical Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)MAX5891 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)604050203010
-6dBFS0dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 500MHz)MAX5891 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
-6dBFS
0dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 600MHz)MAX5891 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
-6dBFS
0dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(fCLK = 500MHz, IOUT = 20mA, 10mA, 5mA)MAX5891 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
10mA
20mA
5mA
TWO-TONE INTERMODULATION DISTORTION
vs. OUTPUT FREQUENCY
(fCLK = 500MHz, 1MHz CARRIER SPACING)MAX5891 toc06
OUTPUT FREQUENCY (MHz)
TTIMD (dBc)
-12dBFS
-6.5dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)MAX5891 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)35201025155
-6dBFS0dBFS-12dBFS
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference VREFIO = 1.2V, output load 50Ω double-terminated,
transformer-coupled output, IOUT = 20mA, TA = +25°C, unless otherwise noted.)
SINGLE-CARRIER WCDMA ACLR
(fCLK = 491.52MHz)OUTPUT POWER (dBm)
MAX5891 toc07
ACLR = 72.3dBfCENTER = 122.88MHz
2.5MHz/div
FOUR-CARRIER WCDMA ACLR
(fCLK = 491.52MHz)
MAX5891 toc08
4.06MHz/div
OUTPUT POWER (dBm)
ACLR = 67.3dB
fCENTER = 122.88MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE (fCLK = 500MHz)
MAX5891 toc09
TEMPERATURE (°C)
SFDR (dBc)3510-15
fOUT = 10MHz
fOUT = 100MHzfOUT = 50MHz
INTEGRAL NONLINEARITYMAX5891 toc10
DIGITAL INPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX5891 toc11
DIGITAL INPUT CODE
DNL (LSB)
TOTAL POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 16MHz, AOUT = 0dBFS)
MAX5891 toc12
CLOCK FREQUENCY (MHz)
POWER DISSIPATION (mW)
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Typical Operating Characteristics (continued)
PINNAMEFUNCTION1, 3, 5, 7, 9,
46, 48, 50, 52,
54, 56, 58, 60,
63, 65, 67
D4N, D3N, D2N, D1N,
D0N, D15N, D14N,
D13N, D12N, D11N,
D10N, D9N, D8N,
D7N, D6N, D5N
Differential Negative LVDS Inputs. Data bits D0–D15 (offset binary format).
2, 4, 6, 8, 45,
47, 49, 51, 53,
55, 57, 59, 62,
64, 66, 68
D3P, D2P, D1P, D0P,
D15P, D14P, D13P,
D12P, D11P, D10P,
D9P, D8P, D7P, D6P,
D5P, D4P
Differential Positive LVDS Inputs. Data bits D0–D15 (offset binary format).DGNDDigital Ground. Ground return for DVDD3.3 and DVDD1.8.
15, 20, 23, 24,
27, 30, 33AGNDAnalog Ground. Ground return for AVDD3.3 and AVDD1.8.DVDD3.3Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to DGND.PDPower-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2µA pulldown.
13, 42, 43, 44N.C.No Connection. Leave loating or connect to AGND.
14, 21, 22, 25,
26, 31, 32AVDD3.3Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to AGND.REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a
0.1µF capacitor to AGND. REFIO can be driven with an external reference source.FSADJ
Full-Scale Current Adjustment. Connect an external resistor RSET between FSADJ and
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
VREF/RSET.DACREFCurrent-Set Resistor Return Path. Internally connected to ground, but do not use as ground
connection.
19, 34, 35AVDD1.8Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to AGND.OUTNComplementary DAC Output. Negative terminal for current output.OUTPDAC Output. Positive terminal for current output.
36, 41AVCLKClock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to CGND.
37, 40CGNDClock Supply GroundCLKNComplementary Converter Clock Input. Negative input terminal for differential converter
clock.CLKPConverter Clock Input. Positive input terminal for differential converter clock.DVDD1.8Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to DGND.EPExposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
MAX589116-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Pin Description
