MAX5889EGK+D ,12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS InputsApplicationsD = Dry pack.+Denotes lead-free package.Base Stations: Single-Carrier UMTS, Functional ..
MAX5890EGK+D ,14-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS InputsApplicationsFunctional DiagramBase Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fi ..
MAX5891EGK ,16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS InputsApplicationsBase Stations: Single/Multicarrier UMTS, MAX5891CDMA, GSM OUTPCommunications: Fixed Bro ..
MAX5891EGK+D ,16-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS InputsApplicationsFunctional Diagram● Base Stations: Single/Multicarrier UMTS, CDMA, GSM● Communication ..
MAX5894EGK+D ,14-Bit, 500Msps, Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894 14 500 CMOSBase Stations: 3G UMTS, CDMA, and GSMMAX5895 16 500 CMOSBroadband Wi ..
MAX5895EGK ,16-Bit, 500Msps Interpolating and Modulating Dual DAC with CMOS InputsApplicationsMAX5894** 14 500 CMOSBase Stations: 3G Multicarrier UMTS, CDMA, and GSMMAX5895 16 500 C ..
MAZ8051M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8056-M ,Silicon planar typeFeatures•Extremely low noise voltage caused from the diode (2.4V to 39V,1/3 to 1/10 of our conventi ..
MAZ8062 ,Small-signal deviceAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAX5889EGK+D
12-Bit, 600Msps, High-Dynamic-Performance DAC with LVDS Inputs
General DescriptionThe MAX5889 advanced 12-bit, 600Msps, digital-to-
analog converter (DAC) meets the demanding perfor-
mance requirements of signal synthesis applications
found in wireless base stations and other communica-
tions applications. Operating from 3.3V and 1.8V sup-
plies, the MAX5889 DAC supports update rates of
600Msps using high-speed LVDS inputs while consum-
ing only 292mW of power and offers exceptional
dynamic performance such as 79dBc spurious-free
dynamic range (SFDR) at fOUT= 30MHz.
The MAX5889 utilizes a current-steering architecture that
supports a 2mA to 20mA full-scale output current range,
and produces -2dBm to -22dBm full-scale output signal
levels with a double-terminated 50Ωload. The MAX5889
features an integrated 1.2V bandgap reference and con-
trol amplifier to ensure high-accuracy and low-noise per-
formance. A separate reference input (REFIO) allows for
the use of an external reference source for optimum flexi-
bility and improved gain accuracy.
The MAX5889 digital inputs accept LVDS voltage lev-
els, and the flexible clock input can be driven differen-
tially or single-ended, AC- or DC-coupled. The
MAX5889 is available in a 68-pin QFN package with an
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.
Refer to the MAX5891 and MAX5890 data sheets for pin-
compatible 16-bit and 14-bit versions of the MAX5889.
ApplicationsBase Stations: Single-Carrier UMTS,
CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features600Msps Output Update RateLow-Noise Spectral Density: -157dBFS/Hz at
fOUT= 36MHzExcellent SFDR and IMD Performance
SFDR = 79dBc at fOUT= 30MHz (to Nyquist)
SFDR = 67dBc at fOUT= 130MHz (to Nyquist)
IMD = -95dBc at fOUT= 30MHz
IMD = -70dBc at fOUT= 130MHz ACLR = 72dB at fOUT= 122.88MHz2mA to 20mA Full-Scale Output CurrentLVDS-Compatible Digital InputsOn-Chip 1.2V Bandgap ReferenceLow 292mW Power Dissipation at 600MspsCompact (10mm x 10mm) QFN-EP PackageEvaluation Kit Available (MAX5891EVKIT)
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Ordering Information19-3620; Rev 1; 3/07
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX5889EGK-D-40°C to +85°C68 QFN-EP*G6800-4
MAX5889EGK+D-40°C to +85°C68 QFN-EP*G6800-4
MAX5889
1.2V
REFERENCE
REFIO
DACREF
FSADJ
CLK
INTERFACE
600MHz
12-BIT DACLATCHLVDS
RECEIVER
D0–D11
LVDS DATA
INPUTS
POWER
DOWN
CLKP
CLKN
OUTP
OUTN
Functional Diagram
PARTRESOLUTION
(BITS)
UPDATE RATE
(Msps)LOGIC INPUTMAX588912600LVDS
MAX589014600LVDS
MAX589116600LVDS
Selector Guide*EP = Exposed paddle.
D = Dry pack.
+Denotes lead-free package.
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-terminat-
ed, transformer-coupled output, IOUT= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥+25°C are guar-
anteed by production testing. Specifications at TA< +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD1.8, DVDD1.8to AGND, DGND, DACREF,
and CGND.......................................................-0.3V to +2.16V
AVDD3.3, DVDD3.3, AVCLKto AGND, DGND,
DACREF, and CGND.........................................-0.3V to +3.9V
REFIO, FSADJ to AGND, DACREF,
DGND, and CGND..........................-0.3V to (AVDD3.3+ 0.3V)
OUTP, OUTN to AGND, DGND, DACREF,
and CGND.......................................-1.2V to (AVDD3.3+ 0.3V)
CLKP, CLKN to AGND, DGND, DACREF,
and CGND..........................................-0.3V to (AVCLK+ 0.3V)
PD to AGND, DGND, DACREF,
and CGND.......................................-0.3V to (DVDD3.3+ 0.3V)
Digital Data Inputs (D0N–D11N, D0P–D11P) to AGND,
DGND, DACREF, and CGND..........-0.3V to (DVDD1.8+ 0.3V)
Continuous Power Dissipation (TA= +70°C) (Note 1)
68-Pin QFN-EP (derate 28.6mW/°C above +70°C)....3333mW
Thermal Resistance θJA (Note 1) ....................................24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution12Bits
Integral NonlinearityINLMeasured differentially±0.25LSB
Differential NonlinearityDNLMeasured differentially±0.15LSB
Offset ErrorOS-0.020.001+0.02%FS
Full-Scale Gain ErrorGEFSExternal reference-4±1+4%FS
Internal reference±130Gain-Drift TempcoExternal reference±100ppm/°C
Full-Scale Output CurrentIOUT220mA
Output ComplianceSingle-ended-1.0+1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
Output Leakage CurrentPD = high, power-down mode±1µA
DYNAMIC PERFORMANCEMaximum DAC Update Rate600Msps
Minimum DAC Update Rate1Msps
fOUT = 36MHz,
AFULL-SCALE = -3.5dBm-157
Noise Spectral DensityN
fCLK = 500MHz,
-12dBFS, 20MHz
offset from the
carrier
fOUT = 151MHz,
AFULL-SCALE = -6.4dBm-152
dBFS/Hz
Note 1:Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-terminat-
ed, transformer-coupled output, IOUT= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥+25°C are guar-
anteed by production testing. Specifications at TA< +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 16MHz88fCLK = 200MHz,
0dBFSfOUT = 30MHz85
fOUT = 16MHz78fCLK = 200MHz,
-12dBFSfOUT = 30MHz77
fOUT = 16MHz7681
fOUT = 30MHz80
fOUT = 130MHz71
Spurious-Free
Dynamic Range to
Nyquist
SFDR
fCLK = 500MHz,
0dBFS
fOUT = 200MHz54
dBc
fCLK = 500MHz
fOUT1 = 29MHz,
fOUT2 = 30MHz,
-6.5dBFS per tone
Two-Tone IMDTTIMD
fCLK = 500MHz
fOUT1 = 129MHz,
fOUT2 = 130MHz,
-6.5dBFS per tone
dBc
fCLK = 491.52MHz,
fOUT = 30.72MHz80
WCDMA single
carrierfCLK = 491.52MHz,
fOUT = 122.88MHz72
fCLK = 491.52MHz,
fOUT = 30.72MHz72
Adjacent Channel
Leakage Power RatioACLR
WCDMA four carriers
fCLK = 491.52MHz,
fOUT = 122.88MHz67
Output BandwidthBW-1dB(Note 2)1000MHz
REFERENCEInternal Reference Voltage RangeVREFIO1.141.21.26V
Reference Input Voltage RangeVREFIOCRUsing external reference0.101.21.32V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage Temperature
DriftTCOREF±30ppm/°C
ANALOG OUTPUT TIMING (Figure 3)Output Fall TimetFALL90% to 10% (Note 3)0.4ns
Output Rise TimetRISE10% to 90% (Note 3)0.4ns
Output Propagation DelaytPDReference to data latency (Note 3)2.5ns
Output Settling TimeTo 0.025% of the final value (Note 3)11ns
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-terminat-
ed, transformer-coupled output, IOUT= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥+25°C are guar-
anteed by production testing. Specifications at TA< +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSGlitch ImpulseMeasured differentially1pV•s
IOUT = 2mA30Output NoiseNOUTIOUT = 20mA30pA/√Hz
TIMING CHARACTERISTICSInput Data Rate600MWps
Data Latency5.5Clock
cycles
Data to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 4)-1.5ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 4)2.6ns
Clock FrequencyfCLKCLKP, CLKN600MHz
Minimum Clock Pulse-Width HightCHCLKP, CLKN0.6ns
Minimum Clock Pulse-Width LowtCLCLKP, CLKN0.6ns
Turn-On TimetSHDNExternal reference, PD falling edge to
output settle within 1%350µs
CMOS LOGIC INPUT (PD)Input Logic HighVIH0.7 x
DVDD3.3V
Input Logic LowVIL0.3 x
DVDD3.3V
Input CurrentIIN-10±1.8+10µA
Input CapacitanceCIN3pF
LVDS INPUTSDifferential Input HighVIHLVDS(Notes 6, 7, 8)+100+1000mV
Differential Input LowVILLVDS(Notes 6, 7, 8)-1000-100mV
Internal Common-Mode BiasVICMLVDS1.1251.375V
Differential Input ResistanceRIDLVDS110Ω
Common-Mode Input ResistanceRICMLVDS3.2kΩ
Input CapacitanceCINLVDS3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)Clock Common-Mode VoltageCLKP and CLKN are internally biasedAVCLK / 2V
Minimum Differential Input
Voltage Swing0.5VP-P
Minimum Common-Mode Voltage1V
Maximum Common-Mode
Voltage1.9V
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Note 2:This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5889.
Note 3:Parameter measured single-ended with 50Ωdouble-terminated outputs.
Note 4:Not production tested. Guaranteed by design.
Note 5:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltages.
Note 6:Not production tested. Guaranteed by design.
Note 7:Differential input voltage defined as VD_P- VD_N.
Note 8:Combination of logic-high/-low and common-mode voltages must not exceed absolute maximum rating for D_P/D_N inputs.
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-terminat-
ed, transformer-coupled output, IOUT= 20mA, TA= -40°C to +85°C, unless otherwise noted. Specifications at TA≥+25°C are guar-
anteed by production testing. Specifications at TA< +25°C are guaranteed by design and characterization. Typical values are at TA
= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput ResistanceRCLKSingle-ended5kΩ
Input CapacitanceCCLK3pF
POWER SUPPLIESAVDD3.33.1353.33.465Analog Supply Voltage RangeAVDD1.81.7101.81.890V
Clock Supply Voltage RangeAVCLK3.1353.33.465V
DVDD3.33.1353.33.465Digital Supply Voltage RangeDVDD1.81.7101.81.890V
fCLK = 100MHz, fOUT = 16MHz26.5
fCLK = 500MHz, fOUT = 16MHz26.528.5IAVDD3.3
fCLK = 600MHz, fOUT = 16MHz26.5
fCLK = 100MHz, fOUT = 16MHz11.3
fCLK = 500MHz, fOUT = 16MHz5058
Analog Supply Current
IAVDD1.8
fCLK = 600MHz, fOUT = 16MHz60
fCLK = 100MHz, fOUT = 16MHz2.8
fCLK = 500MHz, fOUT = 16MHz2.83.6Clock Supply CurrentIAVCLK
fCLK = 600MHz, fOUT = 16MHz2.8
fCLK = 100MHz, fOUT = 16MHz0.2
fCLK = 500MHz, fOUT = 16MHz0.20.5IDVDD3.3
fCLK = 600MHz, fOUT = 16MHz0.2
fCLK = 100MHz, fOUT = 16MHz10.2
fCLK = 500MHz, fOUT = 16MHz4248
Digital Supply Current
IDVDD1.8
fCLK = 600MHz, fOUT = 16MHz48
fCLK = 100MHz, fOUT = 16MHz137
fCLK = 500MHz, fOUT = 16MHz263297
fCLK = 600MHz, fOUT = 16MHz292
Total Power DissipationPDISS
Power-down, clock static low,
data input static13µW
Power-Supply Rejection RatioPSRR(Note 5)±0.025%FS
VD_N
VD_P
VIHLVDSVILLVDS
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
Typical Operating Characteristics(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-termi-
nated, transformer-coupled output, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)MAX5889 toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)2010
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)MAX5889 toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)604050203010
0dBFS
-6dBFS-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 500MHz)MAX5889 toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
-6dBFS
-12dBFS
0dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 600MHz)MAX5889 toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
0dBFS
-6dBFS
-12dBFS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(fCLK = 500MHz, IOUT = 20mA, 10mA, 5mA)MAX5889 toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
20mA
10mA
5mA
0dBFS
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
TWO-TONE INTERMODULATION DISTORTION
vs. OUTPUT FREQUENCY
(fCLK = 500MHz, 1MHz CARRIER SPACING)MAX5889 toc06
OUTPUT FREQUENCY (MHz)
TTIIMD (dBc)
-6.5dBFS
-12dBFS
SINGLE-CARRIER WCDMA ACLR
(fCLK = 491.52MHz)OUTPUT POWER (dBm)
MAX5889 toc07
2.55MHz/div
ACLR = 72.0dB
fCENTER = 122.88MHz
FOUR-CARRIER WCDMA ACLR
(fCLK = 491.52MHz) MAX5889 toc08
4.06MHz/div
OUTPUT POWER (dBm)
ACLR = 67.4dB
fCENTER = 122.88MHz
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE (fCLK = 500MHz)MAX5889 toc09
TEMPERATURE (°C)
SFDR (dBc)3510-15
fOUT = 10MHz
fOUT = 50MHz
fOUT = 100MHz
0dBFS
INTEGRAL NONLINEARITYMAX5889 toc10
DIGITAL INPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX5889 toc11
DIGITAL INPUT CODE
DNL (LSB)
TOTAL POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 16MHz, AOUT = 0dBFS)
MAX5889 toc12
CLOCK FREQUENCY (MHz)
POWER DISSIPATION (mW)
Typical Operating Characteristics (continued)
(AVDD3.3= DVDD3.3= AVCLK= 3.3V, AVDD1.8= DVDD1.8= 1.8V, external reference VREFIO= 1.2V, output load 50Ωdouble-termi-
nated, transformer-coupled output, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
PINNAMEFUNCTION1, 46, 48, 50,
52, 54, 56, 58,
60, 63, 65, 67
D0N, D11N, D10N,
D9N, D8N, D7N,
D6N, D5N, D4N,
D3N, D2N, D1N
Differential Negative LVDS Inputs. Data bits D0–D11 (offset binary format).
2–9N.C.No Connection. Leave floating or connect to DGND.DGNDDigital Ground. Ground return for DVDD3.3 and DVDD1.8.DVDD3.3Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to DGND.PDPower-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for
normal operation. PD has an internal 2µA pulldown.
13, 42, 43, 44N.C.No Connection. Leave floating or connect to AGND.
14, 21, 22, 25,
26, 31, 32AVDD3.3Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to AGND.
15, 20, 23, 24,
27, 30, 33AGNDAnalog Ground. Ground return for AVDD3.3 and AVDD1.8.REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a
0.1µF capacitor to AGND. REFIO can be driven with an external reference source.FSADJ
Full-Scale Current Adjustment. Connect an external resistor RSET between FSADJ and
DACREF to set the output full-scale current. The output full-scale current is equal to 32 x
VREF / RSET.DACREFCurrent-Set Resistor Return Path. Internally connected to ground, but do not use as
ground connection.
19, 34, 35AVDD1.8Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to AGND.OUTNComplementary DAC Output. Negative terminal for current output.OUTPDAC Output. Positive terminal for current output.
36, 41AVCLKClock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a
0.1µF capacitor to CGND.
37, 40CGNDClock Supply GroundCLKNComplementary Converter Clock Input. Negative input terminal for differential converter
clock.CLKPConverter Clock Input. Positive input terminal for differential converter clock.
45, 47, 49, 51,
53, 55, 57, 59,
62, 64, 66, 68
D11P, D10P, D9P,
D8P, D7P, D6P, D5P,
D4P, D3P, D2P, D1P,
D0P
Differential Positive LVDS Inputs. Data bits D0–D11 (offset binary format).DVDD1.8Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a
0.1µF capacitor to DGND.
—EPExposed Pad. Must be connected to common point for AGND, DGND, and CGND through
a low-impedance path. EP is internally connected to AGND, DGND, and CGND.
Pin Description
