MAX5884EGM+D ,3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B10Base Stations: Single-/Multicarrier UMTS, N.C. 2 35 B11CDMA, GSM XOR 3 34 B ..
MAX5885EGM+D ,3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36B1 B12Base Stations: Single/Multicarrier UMTS, 2 35B0 B13CDMA, GSM XOR 3 34 B14Comm ..
MAX5886EGK ,3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPN.C. 1 51 B7NBase Stations: Single/Multicarrier UMTS, N.C. 2 50 B7PN.C. 3 49 B8NCDMA, ..
MAX5886EGK+D ,3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPN.C. 1 51 B7NBase Stations: Single/Multicarrier UMTS, N.C. 2 50 B7PN.C. 3 49 B8NCDMA, ..
MAX5887EGK ,3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPBase Stations: Single/Multicarrier UMTS, B1P 1 51 B9NB1N 2 50 B9PCDMA, GSM B0P 3 49 B ..
MAX5887EGK+D ,3.3V, 14-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS InputsApplicationsEPBase Stations: Single/Multicarrier UMTS, B1P 1 51 B9NB1N 2 50 B9PCDMA, GSM B0P 3 49 B ..
MAZ8051-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8051-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8051M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAZ8056-L ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAX5884EGM+D
3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs
General DescriptionThe MAX5884 is an advanced, 14-bit, 200Msps digital-
to-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthe-
sis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dyna-
mic performance such as 77dBc spurious-free dynamic
range (SFDR) at fOUT= 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
The MAX5884 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1VP-Pand 1VP-P.
The MAX5884 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an exter-
nal reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5884 are
designed for CMOS-compatible voltage levels. The
MAX5884 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5885 data sheets for
pin-compatible 12- and 16-bit versions of the MAX5884.
For LVDS high-speed versions, refer to the MAX5886,
MAX5887, and MAX5888 data sheets.
ApplicationsBase Stations: Single-/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features200Msps Output Update RateSingle 3.3V Supply OperationExcellent SFDR and IMD Performance
SFDR = 77dBc at fOUT= 10MHz (to Nyquist)
IMD = -86dBc at fOUT= 10MHz
ACLR = 72dB at fOUT= 30.72MHz2mA to 20mA Full-Scale Output CurrentCMOS-Compatible Digital and Clock InputsOn-Chip 1.2V Bandgap ReferenceLow Power Dissipation48-Pin QFN-EP Package
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Ordering Information19-2825; Rev 1; 12/03
PARTTEMP RANGEPIN-PACKAGEMAX5884EGM-40°C to +85°C48 QFN-EP*
B10
B11
B13
DGND
N.C.
N.C.
N.C.
N.C.
N.C.
DVDD
SEL0
B12XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
AVDD
AGND
N.C.
N.C.1
AGND
IOUTNIOUTP
AGND
AGND
N.C.
DACREF
FSADJ
REFIOB2B3B4DV
DGNDB5B6B7B9B8B0
QFNMAX5884
AGND
TOP VIEW47464544434241403938371415161718192021222324
Pin Configuration*EP = Exposed paddle.
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AVDD, DVDD, VCLK to DGND...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B13, SEL0, PD, XOR to DGND.............-0.3V to DVDD+ 0.3V
Continuous Power Dissipation (TA= +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (θJA)..............................................+37°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution14Bits
Integral NonlinearityINLMeasured differentially±0.8LSB
Differential NonlinearityDNLMeasured differentially±0.5LSB
Offset ErrorOS-0.025±0.003+0.025%FS
Offset Drift±50ppm/°C
Full-Scale Gain ErrorGEFSExternal reference, TA ≥ +25°C-3.5+1.3%FS
Internal reference±100Gain DriftExternal reference±50ppm/°C
Full-Scale Output CurrentIOUT(Note 1)220mA
Min Output VoltageSingle ended-0.5V
Max Output VoltageSingle ended1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCEOutput Update RatefCLK1200Msps
fCLK = 100MHzfOUT = 16MHz, -12dB FS-153Noise Spectral DensityfCLK = 200MHzfOUT = 80MHz, -12dB FS-148
dB FS/
fOUT = 1MHz, 0dB FS87
fOUT = 1MHz, -6dB FS82Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 100MHz
fOUT = 1MHz, -12dB FS80
dBc
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 10MHz, -12dB FS77fCLK = 100MHzfOUT = 30MHz, -12dB FS73
fOUT = 10MHz, -12dB FS72
fOUT = 16MHz, -12dB FS,
TA ≥ +25°C6874
fOUT = 30MHz, -12dB FS66
Spurious-Free Dynamic Range to
NyquistSFDR
fCLK = 200MHz
fOUT = 50MHz, -12dB FS70
dBc
fOUT1 = 9MHz, -6dB FSfCLK = 100MHzfOUT2 = 10MHz, -6dB FS-86
fOU T 1 = 29M H z, - 6d B FS Two-Tone IMDTTIMD
fCLK = 200MHzfOU T 2 = 30M H z, - 6d B FS -74
dBc
Four-Tone IMD, 1MHz Frequency
Spacing, GSM ModelFTIMDfCLK = 150MHzfOUT = 31.99MHz, -12dB FS-82dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
W-CDMA Model
ACLRfCLK =
184.32MHzfOUT = 30.72MHz72dB
Output BandwidthBW-1dB(Note 2)450MHz
REFERENCEInternal Reference Voltage RangeVREFIO1.11.221.34V
Reference Input Compliance
RangeVREFIOCR0.1251.25V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage DriftTCOREF±50ppm/°C
ANALOG OUTPUT TIMINGOutput Fall TimetFALL90% to 10% (Note 3)375ps
Output Rise TimetRISE10% to 90% (Note 3)375ps
Output Voltage Settling TimetSETTLEOutput settles to 0.025% FS (Note 3)11ns
Output Propagation DelaytPD(Note 3)1.8ns
Glitch Energy1pV-s
IOUT = 2mA30Output NoiseNOUTIOUT = 20mA30pA/√Hz
TIMING CHARACTERISTICSData to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 4)0.4ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 4)1.25ns
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Note 1:Nominal full-scale current IOUT= 32 ✕IREF.
Note 2:This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5884.
Note 3:Parameter measured single ended into a 50Ωtermination resistor.
Note 4:Parameter guaranteed by design.
Note 5:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA,
fCLK= 200Msps, TA= TMINto TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSData Latency3.5Clock
cycles
Minimum Clock Pulse Width HightCHCLKP, CLKN1.5ns
Minimum Clock Pulse Width LowtCLCLKP, CLKN1.5ns
CMOS LOGIC INPUTS (B0–B13, PD, SEL0, XOR)Input Logic HighVIH0.7 x
DVDDV
Input Logic LowVIL0.3 x
DVDDV
Input Leakage CurrentIIN-15+15µA
Input CapacitanceCIN5pF
CLOCK INPUTS (CLKP, CLKN)Sine wave≥1.5Differential Input Voltage SwingVCLKSquare wave≥0.5VP-P
Differential Input Slew RateSRCLK>100V/µs
Common-Mode Voltage RangeVCOM1.5
±20%V
Input ResistanceRCLK5kΩ
Input CapacitanceCCLK5pF
POWER SUPPLIESAnalog Supply Voltage RangeAVDD3.1353.33.465V
Digital Supply Voltage RangeDVDD3.1353.33.465V
Clock Supply Voltage RangeVCLK3.1353.33.465V
fCLK = 100Msps, fOUT = 1MHz27Analog Supply CurrentIAVDDPower-down0.3mA
fCLK = 100Msps, fOUT = 1MHz8mADigital Supply CurrentIDVDDPower-down10µA
fCLK = 100Msps, fOUT = 1MHz5.5mAClock Supply CurrentIVCLKPower-down10µA
fCLK = 100Msps, fOUT = 1MHz134Power DissipationPDISSPower-down1mW
Power-Supply Rejection RatioPSRRAVDD = VCLK = DVDD = 3.3V ±5% (Note 5)-0.1+0.1%FS/V
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Typical Operating Characteristics(AVDD= DVDD= VCLK = 3.3V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 50MHz)
MAX5884 toc01
fOUT (MHz)
SFDR (dBc)
-12dB FS
0dB FS-6dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 100MHz)
MAX5884 toc02
fOUT (MHz)
SFDR (dBc)
-6dB FS
-12dB FS
0dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 150MHz)
MAX5884 toc03
fOUT (MHz)
SFDR (dBc)
-12dB FS0dB FS
-6dB FS
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (fCLK = 200MHz)
MAX5884 toc04
fOUT (MHz)
SFDR (dBc)30706050
-12dB FS
0dB FS
-6dB FS
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 100MHz)
MAX5884 toc05
fOUT (MHz)
2-TONE IMD (dBc)2050
-12dB FS
-6dB FS40
2-TONE INTERMODULATION DISTORTION
(fCLK = 100MHz)
MAX5884 toc06
fOUT (MHz)
OUTPUT POWER (dBm)293231
2 x fT1 - fT2
fT1 fT2
fT1 = 28.9429MHz
fT2 = 29.8706MHz
2 x fT2 - fT1
AOUT = -6dB FS
BW = 12MHz
SFDR vs. OUTPUT FREQUENCY
(fCLK = 200MHz, AOUT = -6dB FS)
MAX5884 toc08
fOUT (MHz)
SFDR (dBc)
IOUT = 5mAIOUT = 10mA
IOUT = 20mA
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fCLK = 200MHz)
MAX5884 toc07
fOUT (MHz)
2-TONE IMD (dBc)103080
-12dB FS
-6dB FS607050
SFDR vs. fOUT AND TEMPERATURE
(fCLK = 200MHz, AOUT = -6dB FS, IFS = 20mA)
MAX5884 toc09
fOUT (MHz)
SFDR (dBc)306050
TA = -40°C
TA = +25°CTA = +85°C
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Typical Operating Characteristics (continued)(AVDD= DVDD= VCLK = 3.3V, external reference, VREFIO= 1.25V, RL= 50Ω, IOUT= 20mA, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5884 toc10
DIGITAL INPUT CODE
INL (LSB)20004000600080001000012000140001600018000
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
MAX5884 toc11
DIGITAL INPUT CODE
DNL (LSB)20004000600080001000012000140001600018000
POWER DISSIPATION vs. CLOCK FREQUENCY
(fOUT = 10MHz, AOUT = 0dB FS, IOUT = 20mA)
MAX5884 toc12
fCLK (MHz)
POWER DISSIPATION (mW)7550100150125175200
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fCLK = 100MHz, fOUT = 10MHz, IFS = 20mA)
MAX5884 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
EXTERNAL REFERENCE
INTERNAL REFERENCE
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Pin Description
PINNAMEFUNCTION1, 2, 16,
25–29N.C.No connection. Do not connect to these pins. Do not tie these pins together.
3XOR
XOR Input Pin.
XOR = 1 inverts the digital input data.
XOR = 0 leaves the digital input data unchanged.
XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9VCLKClock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest CLKGND.
5, 8CLKGNDClock GroundCLKPConverter Clock Input. Positive input terminal for the converter clock.CLKNComplementary Converter Clock Input. Negative input terminal for the converter clock.PDPower-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC.
11, 21, 23AVDDAnalog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest AGND.
12, 17, 20,
22, 24, EPAGNDAnalog Ground. Exposed paddle (EP) must be connected to AGND.REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1µF
capacitor to AGND. Can be driven with an external reference source.FSADJFull-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2kΩ resistor between FSADJ and DACREF.DACREFReturn Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF.IOUTNComplementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.IOUTPDAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.SEL0Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable the
segment-shuffling function (see the Segment Shuffling section).
31, 43DVDDDigital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest DGND.
32, 42DGNDDigital GroundB13Data Bit 13 (MSB)B12Data Bit 12B11Data Bit 11B10Data Bit 10B9Data Bit 9
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
PINNAMEFUNCTIONB8Data Bit 8B7Data Bit 7B6Data Bit 6B5Data Bit 5B4Data Bit 4B3Data Bit 3B2Data Bit 2B1Data Bit 1B0Data Bit 0 (LSB)
Pin Description (continued)1.2V
REFERENCE
CURRENT-STEERING
DAC
FUNCTION
SELECTION
BLOCK
AGND
SEL0DGNDDVDD
REFIO
FSADJ
CLKN
CLKP
AVDD
IOUTP
IOUTN
SEGMENT SHUFFLING/LATCH
DECODER
CMOS RECEIVER/INPUT LATCH
DIGITAL INPUTS B0 THROUGH B13
MAX5884
Figure 1. Simplified MAX5884 Block Diagram
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Detailed Description
ArchitectureThe MAX5884 is a high-performance, 14-bit, current-
steering DAC (Figure 1) capable of operating with
clock speeds up to 200MHz. The converter consists of
separate input and DAC registers, followed by a cur-
rent-steering circuit. This circuit is capable of generat-
ing differential full-scale currents in the range of 2mA to
20mA. An internal current-switching network in combi-
nation with external 50Ωtermination resistors convert
the differential output currents into a differential output
voltage with a peak-to-peak output voltage range of
0.1V to 1V. An integrated 1.2V bandgap reference,
control amplifier, and user-selectable external resistor
determine the data converter’s full-scale output range.
Reference Architecture and OperationThe MAX5884 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source, and as the output if the
DAC is operating with the internal reference. For stable
operation with the internal reference, REFIO should be
decoupled to AGND with a 0.1µF capacitor. Due to its
limited output drive capability, REFIO must be buffered
with an external amplifier, if heavier loading is required.
The MAX5884’s reference circuit (Figure 2) employs a
control amplifier, designed to regulate the full-scale
current IOUTfor the differential current outputs of the
DAC. Configured as a voltage-to-current amplifier, the
output current can be calculated as follows:
IOUT= 32 ✕IREFIO- 1 LSB
IOUT= 32 ✕IREFIO- (IOUT/ 214)
where IREFIOis the reference output current (IREFIO=
VREFIO/RSET) and IOUTis the full-scale output current
of the DAC. Located between FSADJ and DACREF,
RSETis the reference resistor, which determines the
amplifier’s output current for the DAC. See Table 1 for a
matrix of different IOUTand RSETselections.
Analog Outputs (IOUTP, IOUTN)The MAX5884 outputs two complementary currents
(IOUTP, IOUTN) that can be operated in a single-
ended or differential configuration. A load resistor can
convert these two output currents into complementary
single-ended output voltages. The differential voltage
existing between IOUTP and IOUTN can also be con-
verted to a single-ended voltage using a transformer or
a differential amplifier configuration. If no transformer is
used, the output should have a 50Ωtermination to the
analog ground and a 50Ωresistor between the outputs.
0.1μF
1.2V
REFERENCE
10kΩ
IREF
RSET
DACREF
FSADJ
REFIO
IREF = VREFIO/RSET
CURRENT-STEERING
DAC
AVDD
IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference
Configuration
RSET (kΩ)FULL-SCALE CURRENT
IOUT (mA)
REFERENCE CURRENT
IREF (µA)CALCULATED1% EIA STD
OUTPUT VOLTAGE
VIOUTP/N* (mVP-P)62.519.219.1100156.267.687.5250312.53.843.83500468.752.562.557506251.921.911000
Table 1. IOUTand RSETSelection Matrix Based on a Typical 1.200V Reference Voltage*Terminated into a 50Ωload.
