MAX5877EGK+D ,14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS InputsApplicationsBase Stations: Single/Multicarrier UMTS, CDMA, GSM68 67 66 65 64 63 62 61 60 59 58 57 5 ..
MAX5878EGK+ ,16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS InputsApplicationsBase Stations: Single/Multicarrier UMTS, CDMA, GSM68 67 66 65 64 63 62 61 60 59 58 57 5 ..
MAX5883EGM ,3.3V, 12-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B8Base Stations: Single/Multicarrier UMTS, 2 35 B9N.C.CDMAXOR 3 34 B104 33Comm ..
MAX5883EGM+D ,3.3V, 12-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B8Base Stations: Single/Multicarrier UMTS, 2 35 B9N.C.CDMAXOR 3 34 B104 33Comm ..
MAX5884EGM ,3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B10Base Stations: Single-/Multicarrier UMTS, N.C. 2 35 B11CDMA, GSM XOR 3 34 B ..
MAX5884EGM+D ,3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS InputsApplications1 36N.C. B10Base Stations: Single-/Multicarrier UMTS, N.C. 2 35 B11CDMA, GSM XOR 3 34 B ..
MAZ8047-M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8051-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8051M ,Silicon planar typeZener DiodesMAZ8000 SeriesSilicon planar typeUnit : mmFor stabilization of power supplyKA
MAZ8051-M ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8056-H ,Silicon planar typeAbsolute Maximum Ratings T = 25°CaMarking SymbolParameter Symbol Rating UnitRefer to the list of t ..
MAX5877EGK+D
14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
General DescriptionThe MAX5877 is an advanced 14-bit, 250Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 75dBc spurious-free dynamic range
(SFDR) at fOUT = 16MHz and supports update rates of
250Msps, with a power dissipation of only 287mW.
The MAX5877 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1VP-Pto 1VP-P differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an exter-
nal reference source for optimum flexibility and
improved gain accuracy.
The clock inputs of the MAX5877 accept both LVDS
and LVPECL-compatible voltage levels. The device fea-
tures an interleaved data input that allows a single
LVDS bus to support both DACs. The MAX5877 is avail-
able in a 68-pin QFN package with an exposed pad
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5876 and MAX5878 data sheets for
pin-compatible 12-bit and 16-bit versions of the
MAX5877, respectively. Refer to the MAX5874 data
sheet for a CMOS-compatible version of the MAX5877.
ApplicationsBase Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features250Msps Output Update RateNoise Spectral Density = -160dBFS/Hz
at fOUT = 16MHzExcellent SFDR and IMD Performance
SFDR = 75dBc at fOUT = 16MHz (to Nyquist)
SFDR = 71dBc at fOUT = 80MHz (to Nyquist)
IMD = -87dBc at fOUT = 10MHz
IMD = -73dBc at fOUT = 80MHzACLR = 75dB at fOUT= 61MHz2mA to 20mA Full-Scale Output CurrentLVDS-Compatible Digital and Clock InputsOn-Chip +1.20V Bandgap ReferenceLow 287mW Power DissipationCompact 68-Pin QFN-EP Package (10mm x 10mm)Evaluation Kit Available (MAX5878EVKIT)
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Pin Configuration
Ordering Information19-3632; Rev 2; 3/07
*EP = Exposed pad.= Lead-free package. D = Dry pack.
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX5877EGK-D-40°C to +85°C68 QFN-EP*G6800-4
MAX5877EGK+D-40°C to +85°C68 QFN-EP*G6800-4
Selector Guide
PARTRESOLUTION
(BITS)
UPDATE
RATE (Msps)
LOGIC
INPUTSMAX587312200CMOS
MAX587414200CMOS
MAX587516200CMOS
MAX587612250LVDS
MAX587714250LVDS
MAX587816250LVDS596061625455565763
DVDD3.3
DD1.8
B5N
QFNTOP VIEW
B5PDV
DD1.8
B6NB6PB7NB7PB8NB8PB9N53
B9PB10N
DACREFAV
DD3.3
GNDGND
DD3.3
OUTQPOUTQN
GNDGND
OUTIP
OUTIN
DD3.3
GND
DD3.3
B12P
B13N
B13P
SELIQN
SELIQP
XORP
XORN
TORB
CLKPCLKN
GND
AVCLK
GND
N.C.
N.C.
N.C.
N.C.
REFIO
GND
AVDD3.3
GND
GND
B0N
B0P
B1N
B1PB12N
B2N
B4P6667
B3NB3PB4N
B2P2221201927262524182928323130
GND
DD1.833B11N
B11PB10P
FSADJ17
MAX5877
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD1.8, DVDD1.8to GND, DACREF...................-0.3V to +2.16V
AVDD3.3, DVDD3.3, AVCLKto GND, DACREF........-0.3V to +3.9V
REFIO, FSADJ to
GND, DACREF..................................-0.3V to (AVDD3.3+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF...................-1V to (AVDD3.3+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK+ 0.3V)
B13P/B13N–B0P/B0N, XORN, XORP, SELIQN,
SELIQP to GND, DACREF...................-0.3V to (DVDD1.8+ 0.3V)
TORB, PD to GND, DACREF...............-0.3V to (DVDD3.3+ 0.3V)
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW
Thermal Resistance θJA(Note 1)...................................+24°C/W
Operating Temperature Range .........................-40°C to +85°C
Junction Temperature ....................................................+150°C
Storage Temperature Range ...........................-60°C to +150°C
Lead Temperature (soldering, 10s) ...............................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCEResolution14Bits
Integral NonlinearityINLMeasured differentially±0.5LSB
Differential NonlinearityDNLMeasured differentially±0.2LSB
Offset ErrorOS-0.025±0.001+0.025%FS
Offset-Drift Tempco±10ppm/°C
Full-Scale Gain ErrorGEFSExternal reference-4.6-0.6+4.6%FS
Internal reference±100Gain-Drift TempcoExternal reference±50ppm/°C
Full-Scale Output CurrentIOUTFS(Note 3)220mA
Output ComplianceSingle-ended-0.5+1.1V
Output ResistanceROUT1MΩ
Output CapacitanceCOUT5pF
DYNAMIC PERFORMANCEClock FrequencyfCLK2500MHz
Output Update RatefDACfDAC = fCLK / 21250Msps
fDAC = 150MHzfOUT = 16MHz, -12dBFS-160Noise Spectral DensityfDAC = 250MHzfOUT = 80MHz, -12dBFS-157
dBFS/
ELECTRICAL CHARACTERISTICS(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMINto TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
Note 1:Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMINto TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfOUT = 1MHz, 0dBFS98
fOUT = 1MHz, -6dBFS86
fOUT = 1MHz, -12dBFS78
fOUT = 10MHz, -12dBFS77
fDAC = 100MHz
fOUT = 30MHz, -12dBFS78
fOUT = 10MHz, -12dBFS75
fOUT = 16MHz, -12dBFS6675
fOUT = 50MHz, -12dBFS74
fDAC = 200MHz
fOUT = 80MHz, -12dBFS71
fOUT = 10MHz, -12dBFS74
fOUT = 50MHz, -12dBFS72
fOUT = 80MHz, -12dBFS71
Spurious-Free Dynamic Range
to NyquistSFDR
fDAC = 250MHz
fOUT = 100MHz, -12dBFS68
dBc
Spurious-Free Dynamic Range,
25MHz BandwidthSFDRfDAC = 150MHzfOUT = 16MHz, -12dBFS80dBc
fDAC = 100MHzfOUT1 = 9MHz, -7dBFS;
fOUT2 = 10MHz, -7dBFS-87
Two-Tone IMDTTIMD
fDAC = 200MHzfOUT1 = 79MHz, -7dBFS;
fOUT2 = 80MHz, -7dBFS-73
dBc
Four-Tone IMD, 1MHz
Frequency Spacing, GSM ModelFTIMDfDAC = 150MHzfOUT = 16MHz, -12dBFS-94dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLRfDAC =
184.32MHzfOUT = 61.44MHz75dB
Output BandwidthBW-1dB(Note 4)240MHz
INTER-DAC CHARACTERISTICSfOUT = DC - 80MHz±0.2Gain Matching∆GainfOUT = DC-0.25+0.01+0.25dB
Gain-Matching Tempco∆Gain/°C±20ppm/°C
Phase Matching∆PhasefOUT = 60MHz±0.25D egr ees
Phase-Matching Tempco∆Phase/°CfOUT = 60MHz±0.002D eg r ees/
°C
Channel-to-Channel CrosstalkfDAC = 200Msps, fOUT = 50MHz, 0dBFS90dB
REFERENCEInternal Reference Voltage RangeVREFIO1.141.21.26V
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMINto TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSReference Input Compliance
RangeVREFIOCR0.1251.260V
Reference Input ResistanceRREFIO10kΩ
Reference Voltage DriftTCOREF±25ppm/°C
ANALOG OUTPUT TIMING (See Figure 4)Output Fall TimetFALL90% to 10% (Note 5)0.7ns
Output Rise TimetRISE10% to 90% (Note 5)0.7ns
Output-Voltage Settling TimetSETTLEOutput settles to 0.025% FS (Note 5)14ns
Output Propagation DelaytPDExcluding data latency (Note 5)1.1ns
Glitch ImpulseMeasured differentially1pV•s
IOUTFS = 2mA30Output NoisenOUTIOUTFS = 20mA30pA/√Hz
TIMING CHARACTERISTICSData to Clock Setup TimetSETUPReferenced to rising edge of clock (Note 6)-1.2ns
Data to Clock Hold TimetHOLDReferenced to rising edge of clock (Note 6)2.0ns
Latency to I output9Data LatencyLatency to Q output8
Clock
Cycles
Minimum Clock Pulse-Width HightCHCLKP, CLKN0.9ns
Minimum Clock Pulse-Width LowtCLCLKP, CLKN0.9ns
LVDS LOGIC INPUTS (B13P/B13N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)Differential Input-Logic HighVIH100mV
Differential Input-Logic LowVIL-100mV
Common-Mode Voltage RangeVCMR1.1251.375V
Differential Input ResistanceRIN(Note 7)110Ω
Input CapacitanceCIN2.5pF
CMOS LOGIC INPUTS (PD, TORB)Input-Logic HighVIH0.7 x
DVDD3.3V
Input-Logic LowVIL0.3 x
DVDD3.3V
Input Leakage CurrentIIN-201+20µA
PD, TORB Internal Pulldown
ResistanceVPD = VTORB = 3.3V1.5MΩ
Input CapacitanceCIN2.5pF
CLOCK INPUTS (CLKP, CLKN)Sine wave> 1.5Differential Input
Voltage SwingSquare wave> 0.5VP-P
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, GND = 0, fCLK = 2 x fDAC, external reference VREFIO = +1.25V, out-
put load 50Ωdouble-terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMINto TMAX, unless otherwise noted. Typical values
are at TA = +25°C.) (Note 2)
Note 2:Specifications at TA≥+25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design.
Note 3:Nominal full-scale current IOUTFS = 32 x IREF.
Note 4:This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5877.
Note 5:Parameter measured single-ended into a 50Ωtermination resistor.
Note 6:Not production tested. Guaranteed by design.
Note 7:No termination resistance between XORP and XORN.
Note 8:A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 9:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDifferential Input Slew RateSRCLK(Note 8)>100V/µs
External Common-Mode Voltage
RangeVCOM AVCLK / 2
±0.3V
Input ResistanceRCLK5kΩ
Input CapacitanceCCLK2.5pF
POWER SUPPLIESAVDD3.33.1353.33.465Analog Supply Voltage RangeAVDD1.81.7101.81.890V
DVDD3.33.1353.33.465Digital Supply Voltage RangeDVDD1.81.7101.81.890V
Clock Supply Voltage RangeAVCLK3.1353.33.465V
fDAC = 250Msps, fOUT = 16MHz5258mAIAVDD3.3
+ IAVCLKPower-down1µA
fDAC = 250Msps, fOUT = 16MHz3036mAAnalog Supply Current
IAVDD1.8Power-down1µA
fDAC = 250Msps, fOUT = 16MHz0.21mAIDVDD3.3Power-down1µA
fDAC = 250Msps, fOUT = 16MHz3440mADigital Supply Current
IDVDD1.8Power-down4µA
fDAC = 250Msps, fOUT = 16MHz287331mWPower DissipationPDISSPower-down16µW
Power-Supply Rejection RatioPSRRAVDD3.3 = AVCLK = DVDD3.3 = +3.3V ±5%
(Notes 8, 9)-0.1+0.1%FS/V
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 50Msps)MAX5877 toc01
fOUT (MHz)
SFDR (dBc)15105
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 100Msps)MAX5877 toc02
fOUT (MHz)
SFDR (dBc)302010
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 150Msps)MAX5877 toc03
fOUT (MHz)
SFDR (dBc)453015
-12dBFS
-6dBFS
0dBFS
Typical Operating Characteristics(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 200Msps)MAX5877 toc04
fOUT (MHz)
SFDR (dBc)604020
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (fDAC = 250Msps)MAX5877 toc05
fOUT (MHz)
SFDR (dBc)
-12dBFS
-6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fDAC = 100Msps)MAX5877 toc06
fOUT (MHz)
TWO-TONE IMD (dBc)3025201510
-12dBFS
-6dBFS
TWO-TONE INTERMODULATION
DISTORTION (fDAC = 100Msps)MAX5877 toc07
fOUT (MHz)
OUTPUT POWER (dBFS)32302826
BW = 12MHz
2 x fT1 - fT22 x fT2 - fT1
fT1fT2
fT1 = 28.9795MHz
fT2 = 30.0049MHz
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, fDAC = 200Msps)MAX5877 toc08
fOUT (MHz)
TWO-TONE IMD (dBc)605040302010
-12dBFS
-6dBFS
SFDR vs. FULL-SCALE OUTPUT CURRENT
(fDAC = 250Msps)MAX5877 toc09
fOUT (MHz)
SFDR (dBc)
AOUT = -6dBFS
10mA5mA
20mA
SFDR vs. TEMPERATURE
(fDAC = 250Msps)MAX5877 toc10
fOUT (MHz)
SFDR (dBc)
AOUT = -6dBFS
TA = +85°C
TA = +25°C
TA = -40°C
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODEMAX5877 toc11
DIGITAL INPUT CODE
INL (LSB)
12,28881924096
1.016,384
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5877 toc12
DIGITAL INPUT CODE
DNL (LSB)
12,28881924096
016,384
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Typical Operating Characteristics (continued)(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Typical Operating Characteristics (continued)(AVDD3.3 = DVDD3.3 = AVCLK= +3.3V, AVDD1.8 = DVDD1.8 = +1.8V, external reference, VREFIO = +1.25V, RL = 50Ωdouble-terminated,
IOUTFS = 20mA, TA= +25°C, unless otherwise noted.)
POWER DISSIPATION vs. DAC
UPDATE RATE (fOUT = 10MHz)MAX5877 toc13
fDAC (Msps)
POWER DISSIPATION (mW)
AOUT = 0dBFS
POWER DISSIPATION vs. SUPPLY VOLTAGE
(fDAC = 100Msps, fOUT = 10MHz)MAX5877 toc14
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
AOUT = 0dBFS
EXTERNAL REFERENCE
INTERNAL REFERENCE
FOUR-TONE POWER RATIO PLOT
(fDAC = 150MHz)
MAX5877 toc15
fOUT (MHz)
OUTPUT POWER (dBFS)34323028
BW = 12MHz
fT1
fT2fT3
fT4
fT1 = 29.6997MHz
fT2 = 30.7251MHz
fT3 = 31.6040MHz
fT4 = 32.4829MHz
ACLR FOR WCDMA MODULATION,
SINGLE-CARRIER ACLRMAX5877 toc16
9.216MHz/div
ANALOG OUTPUT POWER (dBm)
1MHz92.16MHz
fDAC = 184.32Mbps
fCARRIER = 30.72MHz
ACLR = +80dB
ACLR FOR WCDMA MODULATION
TWO-CARRIER ACLR
MAX5877 toc17
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
fDAC = 245.76Msps
fCENTER = 30.72MHz
ACLR = +77dB
ACLR FOR WCDMA MODULATION
TWO-CARRIER ACLRMAX5877 toc18
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
fDAC = 184.32Msps
fCENTER = 30.72MHz
ACLR = +77dB-40
WCDMA BASEBAND ACLR
(fDAC = 245.76Msps)MAX5877 toc19
NUMBER OF CHANNELS
ACLR (dB)321
ALTERNATE
ADJACENT
79.0
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Pin Description
PINNAMEFUNCTIONB2NComplementary Data Bit 2B1PData Bit 1B1NComplementary Data Bit 1B0PData Bit 0 (LSB)B0NComplementary Data Bit 0 (LSB)
6–9N.C.No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GNDGroundDVDD3.3Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,AVDD3.3Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.FSADJFull-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.DACREFCurrent-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.19, 34AVDD1.8Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.OUTQNComplementary Q-DAC Output. Negative terminal for current output.OUTQPQ-DAC Output. Positive terminal for current output.OUTINComplementary I-DAC Output. Negative terminal for current output.OUTIPI-DAC Output. Positive terminal for current output.AVCLKClock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.CLKNComplementary Converter Clock Input. Negative input terminal for LVDS/LVPECL-compatible
differential converter clock. Internally biased to AVCLK / 2.CLKPConverter Clock Input. Positive input terminal for LVDS/LVPECL-compatible differential converter
clock. Internally biased to AVCLK / 2.TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate an offset binary input
format. TORB has an internal pulldown resistor.
MAX5877
14-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Pin Description (continued)
PINNAMEFUNCTIONPDPower-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.XORN
Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow
the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the
DAC input data. If unused, connect XORN to DVDD1.8.XORP
LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to
pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If
unused, connect XORP to GND.SELIQPLVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs.
Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.SELIQNComplementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the
I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.B13PData Bit 13 (MSB)B13NComplementary Data Bit 13 (MSB)B12PData Bit 12B12NComplementary Data Bit 12B11PData Bit 11B11NComplementary Data Bit 11B10PData Bit 10B10NComplementary Data Bit 10B9PData Bit 9B9NComplementary Data Bit 9B8PData Bit 8B8NComplementary Data Bit 8B7PData Bit 7B7NComplementary Data Bit 7B6PData Bit 6B6NComplementary Data Bit 6DVDD1.8Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF
capacitor to GND.B5PData Bit 5B5NComplementary Data Bit 5B4PData Bit 4B4NComplementary Data Bit 4B3PData Bit 3B3NComplementary Data Bit 3B2PData Bit 2
—EPExposed Pad. Must be connected to GND through a low-impedance path.
