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MAX5631UCB+D |MAX5631UCBDMAXIMN/a4avai16-Bit DACs with 32-Channel Sample-and-Hold Outputs


MAX5631UCB+D ,16-Bit DACs with 32-Channel Sample-and-Hold OutputsApplicationsN.C. 2 50 VDDGS 3 49CHMEMS Mirror Servo ControlV 4 48LDAC VSSIndustrial Process Control ..
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MAZ8027-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8027-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
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MAX5631UCB+D
16-Bit DACs with 32-Channel Sample-and-Hold Outputs
General Description
The MAX5631/MAX5632/MAX5633 are 16-bit digital-to-
analog converters (DACs) with 32 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
The MAX5631/MAX5632/MAX5633 feature a -4.5V to
+9.2V output voltage range. Other features include a
200µV/step resolution, with output linearity error, typi-
cally 0.005% of full-scale range (FSR). The 100kHz
refresh-rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
These devices are controlled through a 20MHz
SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial
interface. Immediate Update Mode allows any chan-
nel’s output to be updated within 20µs. Burst Mode
allows multiple values to be loaded into memory in a
single, high-speed data burst. All channels are updated
within 330µs after data has been loaded.
Each device features an output clamp and output resis-
tors for filtering. The MAX5631 features a 50Ωoutput
impedance and is capable of driving up to 250pF of out-
put capacitance. The MAX5632 features a 500Ωoutput
impedance and is capable of driving up to 10nF of output
capacitance. The MAX5633 features a 1kΩoutput imped-
ance and is capable of driving up to 10nF of output
capacitance.
The MAX5631/MAX5632/MAX5633 are available in 12mm
x 12mm, 64-pin TQFP, and 10mm x 10mm, 68-pin thin
QFN packages.
________________________Applications

MEMS Mirror Servo Control
Industrial Process Control
Automatic Test Equipment
Instrumentation
Features
Integrated 16-Bit DAC and 32-Channel SHA with
SRAM and Sequencer
32 Voltage Outputs0.005% Output Linearity200µV Output ResolutionFlexible Output Voltage RangeRemote Ground SensingFast Sequential Loading: 1.3µs per RegisterBurst and Immediate Mode AddressingNo External Components Required for Setting
Gain and Offset
Integrated Output Clamp DiodesThree Output Impedance Options:
MAX5631 (50Ω), MAX5632 (500Ω), and
MAX5633 (1kΩ)

19-2171; Rev 2; 9/02
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Configurations
Ordering Information

SPI and QSPI are trademarks of Motorola, Inc.
Pin Configurations continued at end of data sheet.
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= +10V, VSS= -4V, VLOGIC= VLDAC= VLSHA= +5V, VREF= +2.5V, AGND = DGND = VGS= 0, RL ≥10MΩ, CL= 50pF,
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND.......................................................-0.3V to +12.2V
VSSto AGND.........................................................-6.0V to +0.3V
VDDto VSS...........................................................................+15V
VLDAC, VLOGIC, VLSHAto AGND or DGND..............-0.3V to +6V
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................VSSto VDD
CL and CH to AGND...................................................VSSto VDD
Logic Inputs to DGND..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current Into OUT_............................................±10mA
Maximum Current Into Logic Inputs.................................±20mA
Continuous Power Dissipation (TA= +70°C)
64-Pin TQFP (derate 13.3mW/°C above +70°C)............1066mW
68-Pin QFN (derate 28.6mW/°C above +70°C)..............2285mW
Operating Temperature Range...........................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +10V, VSS= -4V, VLOGIC= VLDAC= VLSHA= +5V, VREF= +2.5V, AGND = DGND = VGS= 0, RL ≥10MΩ, CL= 50pF,
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Note 1:
The nominal zero-scale (code = 0) voltage is -4.0535V. The nominal full-scale (code = FFFF hex) voltage is +9.0535V. The
output voltage is limited by the Output Range specification, restricting the useable range of DAC codes. The nominal zero-
scale voltage may be achieved when VSS< -4.9V, and the nominal full-scale voltage may be achieved when VDD> +11.5V.
Note 2:
Gain is calculated from measurements
for voltages VDD= 10V and VSS= -4V at codes C000 hex and 4F2C hex,
for voltages VDD= 11.6V and VSS= -2.9V at codes FFFF hex and 252E hex,
for voltages VDD= 9.25V and VSS= -5.25V at codes D4F6 hex and 0 hex, and
for voltages VDD= 8.55V and VSS= -2.75V at codes C74A hex and 281C hex.
Note 3:
Steady-state change in any output with an 8V change in an adjacent output.
Note 4:
Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5:
External clock mode with the external clock not toggling.
Note 6:
The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F2C hex.
Note 7:
The sequencer runs at fSEQ= fECLK/4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
limited by acceptable droop and update time after a Burst Mode Update.
Note 8:
VDDrise to CSlow = 500µs maximum.
Note 9:
Guaranteed by gain-error test.
Note 10:
The serial interface is inactive. VIH= VLOGIC, VIL= 0.
Note 11:
The serial interface is active. VIH= VLOGIC, VIL= 0.
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +10V, VSS= -4V, VLOGIC= VLDAC= VLSHA= +5V, VREF= +2.5V, AGND = DGND = VGS= 0, RL ≥10MΩ, CL= 50pF,
Typical Operating Characteristics
(VDD= +10V, VSS= -4V, VREF= +2.5V, VGS= 0, TA = +25°C, unless otherwise noted.)
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputsypical Operating Characteristics (continued)

(VDD= +10V, VSS= -4V, VREF= +2.5V, VGS= 0, TA = +25°C, unless otherwise noted.)
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs

Figure 1. Functional Diagram
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