MAX555CQK ,300Msps, 12-Bit DAC with Complementary Voltage OutputsELECTRICAL CHARACTERISTICS(AV = DV = -5.2V, V = 1.000V, T to T = 0°C to +70°C, unless otherwise not ..
MAX5580AEUP ,Buffered / Fast-Settling / Quad / 12-/10-/8-Bit / Voltage-Output DACsApplicationsINLOUTPUT BUFFER RESOLUTIONPortable InstrumentationPART (LSBCONFIGURATION (BITS)Automat ..
MAX5580BEUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 12-bit, voltage-output DACFeaturesThe MAX5580–MAX5585 quad, 12-/10-/8-bit, voltage- ♦ 3µs (max) 12-Bit Settling Time to 0.5 L ..
MAX5580BEUP+ ,Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACsELECTRICAL CHARACTERISTICS(AV = 2.7V to 5.25V, DV = 1.8V to AV , V = 0, V = 0, V = 2.5V (for AV = 2 ..
MAX5580BEUP+ ,Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACsApplicationsThe MAX5580/MAX5581 are 12-bit DACs, the Portable InstrumentationMAX5582/MAX5583 are 10 ..
MAX5581AEUP ,+2.7 to +5.25 V, buffered, fast-settling, quad, 12-bit, voltage-output DACMAX5580–MAX558519-3164; Rev 1; 5/04Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
MAZ3200 ,Small-signal deviceElectrical characteristics within part numbers T = 25°Ca• V = 2.0 V to 8.2 V (I = 5 mA)Z ZTemperat ..
MAZ3200-M ,Silicon planar typeZener DiodesMAZ3000 SeriesSilicon planar typeUnit : mm+ 0.22.8 − 0.3For stabilization of power supp ..
MAZ8024 ,Small-signal deviceelectrical characteristicswithin part numbersReverse current I V Specified value µ AR R*3Temperatur ..
MAZ8027-H ,Silicon planar typeElectrical characteristics within part numbers T = 25°CaTemperaturecoefficient ofZener voltage Rev ..
MAZ8027-L ,Silicon planar typeElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitForward voltage V ..
MAZ8030-H ,Silicon planar typeelectrical characteristicsZ Zwithin part numbersReverse current I V ··············· Specified value ..
MAX555CQK
300Msps, 12-Bit DAC with Complementary Voltage Outputs
_______________General DescriptionThe MAX555 is an advanced, monolithic, 12-bit digital-
to-analog converter (DAC) with complementary 50Ω
outputs. Fabricated using an oxide-isolated bipolar
process, the MAX555 is designed for signal-reconstruc-
tion applications at an output update rate of 300Msps.
It incorporates an analog multiplying function with
10MHz useable input bandwidth. The voltage-output
DAC uses precision laser trimming to achieve 12-bit
accuracy with ±1/2LSB integral and differential linearity
(±0.012% FS). Absolute gain error is a low 1% of full
scale. Full-scale transitions occur in less than 0.5ns.
Internal registers and a unique decoder reduce glitch-
ing and allow the MAX555 to achieve precise RF perfor-
mance with over 73dBc of spurious-free dynamic range
at 50Msps with fOUT= 3.1MHz, or 62dBc at 300Msps
with fOUT= 18.6MHz.
The MAX555 operates from a single -5.2V supply and
dissipates 980mW (nominal). It comes in a 68-pin ther-
mally enhanced PLCC package capable of accepting a
heatsink.
________________________ApplicationsDirect Digital Synthesis
Arbitrary Waveform Generation
HDTV/High-Resolution Graphics
Instrumentation
Communications Local Oscillators
Automated Tester Applications
____________________________Features12-Bit Resolution±1/2LSB Integral and Differential NonlinearityCapable of 300Msps Min Update RateComplementary 50ΩOutputsMultiplying Reference InputLow Glitch Energy (5.6pVs)Single -5.2V Power SupplyOn-Chip Data RegistersECL-Compatible Inputs with Differential Clock
______________Ordering Information
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
________________________________________________________________Maxim Integrated Products1
___________________________________________________Simplified Block Diagram
Call toll free 1-800-998-8800 for literature.
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVEE= DVEE= -5.2V, VREF= 1.000V, TMINto TMAX= 0°C to +70°C, unless otherwise noted.) (Note 2.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:Typical thermal resistance, junction-to-case RqJC= 28°C/W. See Package Information.
Analog Supply Voltage (AVEE).................................-7V to +0.3V
Digital Supply Voltage (DVEE)..................................-7V to +0.3V
Digital Input Voltage (D0–D11)...................................-5.5V to 0V
Reference Input Voltage (VIN).................................0V to +1.25V
Reference Input Current....................................0mA to +1.56mA
Output Compliance Voltage (VOC)......................-1.25V to +1.0V
Output Common-Mode Voltage (VCM)................-0.25V to +1.0V
Continuous Power Dissipation (TA= +70°C)
(without additional heatsink)..............................................1.3W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature Range (Note 1).................0°C to +150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)(AVEE= DVEE= -5.2V, VREF= 1.000V, TMINto TMAX= 0°C to +70°C, unless otherwise noted.) (Note 2.)
Note 2:All devices are 100% production tested at +25°C and are guaranteed by design for TA= TMINto TMAXas specified.
Note 3:The gain-error method of calculation is shown below:
Definition:
[VMEASURE(FS)- VIDEAL(FS)] x 100
EG(%) = ––––––––––––––––––––––––––––––––––
VIDEAL(FS)
where FS indicates full-scale measurements.
EG Method:
EG = [(4096 / 4095) VMEASURE- 16(VREF / RIN) (ROUT)] x 100
–––––––––––––––––––––––––––––––––––––––––––––––––– %
16(VREF / RIN) (ROUT)
= [(4096 / 4095) VMEASURE- 1] x 100
––––––––––––––––––––––––––––––––- %
where: VREF= 1.000V, RIN= 800Ω, ROUT= 50Ω, VMEASURE= VOUT(FS).
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs_______________________________________________________________________________________
__________________________________________Typical Operating Characteristics(VREF = 0.75V, TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. fCLK (fOUT ~ 1/16 fCLK)MAX555-07
CLOCK FREQUENCY (MHz)
SFDR (dB)
3RD HARMONIC DISTORTION vs.
VREF VOLTAGE (fOUT ~ 1/5 fCLK)
MAX555-08
VREF VOLTAGE (V)
3RD HARMONIC (dBc)
2ND HARMONIC DISTORTION vs.
VREF VOLTAGE (fOUT ~ 1/5 fCLK)
MAX555-09
VREF VOLTAGE (V)
3RD HARMONIC (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 50MHz)
MAX555-01
fOUT (MHz)
SFDR (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 200MHz)
MAX555-04
fOUT (MHz)
SFDR (dBc)405153525
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 150MHz)
MAX555-03
fOUT (MHz)
SFDR (dBc)40515352551525
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 100MHz)MAX555-02
fOUT (MHz)
SFDR (dBc)20
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 250MHz)
MAX555-05
fOUT (MHz)
SFDR (dBc)40515352545
SPURIOUS-FREE DYNAMIC RANGE
vs. fOUT (fCLK = 300MHz)MAX555-06
fOUT (MHz)
SFDR (dBc)50403020100
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs
_______________________________________________________________________________________5
_______________Detailed DescriptionFigure 1’s functional diagram shows the MAX555’s three
major divisions: a digital section, a control-amplifier sec-
tion, and a resistor-divider network. The digital section
consists of a master/slave register, decoding logic, and
current switches. The control-amplifier section includes a
control amplifier and an array of 23 current sources divid-
ed into three groups. The resistor divider scales the cur-
rents from these groups to achieve the correct binary
weighting at the output. The output of the resistor-divider
network is laser trimmed to 50Ω, a key feature for driving
into controlled impedance transmission lines.
The first group of current sources comprises the six
MSBs, D11–D6 (resulting in 15 identical, plus two binary
weighted currents), which are applied directly to the out-
put of the resistor-divider network. The second group,
bits D5–D3 (three binary weighted currents), is applied
to the middle of the divider network. The middle of the
network divides the current seen at the output by 8. The
third group, bits D2–D0 (three additional binary weighted
current sources), is applied to the input of the resistive
network, dividing the current seen at the output by 64.
Glitching is reduced by decoding the four MSBs into 15
identical current sources and synchronizing data with a
master/slave register at every current switch. Data bits
are transferred to the output on the positive-going edge
of the clock, with the BYPASS input asserted low. In
the asynchronous mode with the BYPASS input assert-
ed high, the latches are transparent and data is trans-
ferred to the output regardless of the clock state. All
digital inputs are ECL compatible. The clock input is
differential.
The control amplifier forces a reference current, which is
replicated in the current sources. This reference current
is nominally 1.25mA. It can be supplied by an external
current source, or by an external voltage source of
1.000V applied to the VREF input.
A reference input of VREF= 1.000V will produce a full-
scale output voltage of VFS= -1.000V, where:
VFS= 4096 / 4095 x VOUT(code 0)
for the VOUToutput. The output coding is summarized
in Table 1.
The DAC’s control amplifier has a typical open-loop volt-
age gain of 85dB, and its gain-magnitude bandwidth is
flat up to 10MHz. When the control amplifier is not being
used for high-speed multiplying applications, it is recom-
mended that a 0.4µF capacitor be connected from LBIAS
to AVEEto increase control-amplifier stability and reduce
current-source noise.
MAX555
300Msps, 12-Bit DAC with
Complementary Voltage Outputs_______________________________________________________________________________________Figure 1. Functional Diagram
