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MAX509ACAP+MAXIMN/a1500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX509BCAP+MAXIMN/a8avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX509BCWP+ |MAX509BCWPMAXIMN/a20avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX510AEWE+N/AN/a2500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX510AEWE+TMAXIMN/a500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX510BCWE+N/AN/a2500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX510BCWE+TMAIXMN/a2500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
MAX510BEWE+TMAXIMN/a500avaiQuad, Serial, 8-Bit DACs with Rail-to-Rail Outputs


MAX510AEWE+ ,Quad, Serial, 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 3; 12/10Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX510AEWE+T ,Quad, Serial, 8-Bit DACs with Rail-to-Rail OutputsGeneral Description ________
MAX510BCPE ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsGeneral Description ________
MAX510BCPE ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 2; 1/96Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX510BCWE ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsGeneral Description ________
MAX510BCWE+ ,Quad, Serial, 8-Bit DACs with Rail-to-Rail OutputsGeneral Description ________
MAX9491ETP045+ ,Factory-Programmable, Single PLL Clock GeneratorELECTRICAL CHARACTERISTICS(V = V = +3.0V to +3.6V and T = -40°C to +85°C. Typical values at V = V = ..
MAX9491ETP045+T ,Factory-Programmable, Single PLL Clock GeneratorApplications Ordering InformationTelecommunicationsPIN- PKGPART TEMP RANGEPACKAGE CODEData Networki ..
MAX9491ETP095+ ,Factory-Programmable, Single PLL Clock Generatorfeatures an integrated volt-age-controlled crystal oscillator (VCXO) that is tuned by a♦ Low RMS Ji ..
MAX9502GEXK+T ,2.5V Video Amplifier with Reconstruction FilterFEATURES● Security/CCTVMAX9503 DirectDrive™, LPF, TQFNMAX9505 DirectDrive, LPF, analog switch, TQFN ..
MAX9502MEXK+T ,2.5V Video Amplifier with Reconstruction FilterElectrical Characteristics(V = SHDN = 3.0V, GND = 0V, no load, T = T to T , unless otherwise noted. ..
MAX9502MEXK+T ,2.5V Video Amplifier with Reconstruction Filterapplications.● 5.5MHz PassbandThe MAX9502 DC-couples the input and the output, ● 55dB Attenuation ..


MAX509ACAP+-MAX509BCAP+-MAX509BCWP+-MAX510AEWE+-MAX510AEWE+T-MAX510BCWE+-MAX510BCWE+T-MAX510BEWE+T
Quad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
_______________General Description
The MAX509/MAX510 are quad, serial-input, 8-bit volt-
age-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual ±5V supplies.
Internal, precision buffers swing rail-to-rail. The refer-
ence input range includes both supply rails.
The MAX509 has four separate reference inputs, allow-
ing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two ref-
erence inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.
The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to
load data into each register. Both input and DAC regis-
ters can be updated independently or simultaneously
with single software commands. Two additional asyn-
chronous control pins provide simultaneous updating
(LDAC)or clearing (CLR)of input and DAC registers.
The interface is compatible with MICROWIRETMand
SPI/QSPITM. All digital inputs and outputs are
TTL/CMOS compatible. A buffered data output provides
for readback or daisy-chaining of serial devices.
____________________________Features
Single +5V or Dual ±5V Supply OperationOutput Buffer Amplifiers Swing Rail-to-RailReference Input Range Includes Both Supply RailsCalibrated Offset, Gain, and Linearity (1LSB TUE)10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0) and MICROWIRE
Double-Buffered Registers for Synchronous
Updating
Serial Data Output for Daisy-Chaining Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
______________Ordering Information
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

OUTC
OUTD
VDD
REFCREFB
VSS
OUTA
OUTB
TOP VIEW
MAX509
REFD
N.C.
SCLKDGND
N.C.
AGND
REFA
DIN
CLRDOUT
LDAC
DIP/SO/SSOP
_________________Pin Configurations

MAX509
OUTA
DAC A
DAC B
DAC C
DAC D
REFAREFB
DAC
REG A
DECODE
CONTROL
INPUT
REG A
DAC
REG B
INPUT
REG B
DAC
REG C
INPUT
REG C
DAC
REG D
INPUT
REG D
12-BIT
SHIFT
REGISTER
CONTROLDINSCLKREFCREFD
OUTB
OUTC
OUTD
DOUTLDAC
CLR
VDDDGNDVSSAGND
_______________Functional Diagrams

19-0155; Rev 3; 12/10
Pin Configurations continued at end of data sheet.Functional Diagrams continued at end of data sheet.
PARTTEMP RANGEPIN-PACKAGETUE
(LSB)

MAX509ACPP+0°C to +70°C20 PDIP±1
MAX509BCPP+0°C to +70°C20 PDIP±1.5
MAX509ACWP+0°C to +70°C20 Wide SO±1
MAX509BCWP+0°C to +70°C20 Wide SO±1.5
MAX509ACAP+0°C to +70°C20 SSOP±1
Ordering Information continued on last page.

**Contact factory for availability and processing to MIL-STD-883.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

VDDto DGND..............................................................-0.3V, +6V
VDDto AGND...............................................................-0.3V, +6V
VSSto DGND...............................................................-6V, +0.3V
VSSto AGND...............................................................-6V, +0.3V
VDDto VSS.................................................................-0.3V, +12V
Digital Input Voltage to DGND......................-0.3V, (VDD+ 0.3V)
REF_....................................................(VSS- 0.3V), (VDD+ 0.3V)
OUT_..............................................................................VDD, VSS
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C).........762mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C)........800mW
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
20-Pin Wide SO (derate 10.00mW/°C above +70°C).......800mW
20-Pin SSOP (derate 10.00mW/°C above +70°C)............800mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C)........889mW
Operating Temperature Ranges:
MAX5_ _ _C_ _.....................................................0°C to +70°C
MAX5_ _ _E_ _..................................................-40°C to +85°C
MAX5_ _ _MJ_................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages..............................................+260°C
Packages containing lead (Pb).....................................+260°C
ELECTRICAL CHARACTERISTICS
DD= +5V ±10%, VSS= 0V to -5.5V, VREF= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX, unless other-
wise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETERCONDITIONSMINTYPMAXUNITS
Note:
The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuitcurrent
to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.
ABSOLUTE MAXIMUM RATINGS

Resolution8BitsMAX5_ _AVREF = +4V,
VSS= 0V or -5V ±10%MAX5_ _BMAX5_ _ATotal Unadjusted ErrorVREF = -4V,SS= -5V ±10%±1.5
LSB
Differential Nonlinearity±1LSBGuaranteed monotonicMAX5_ _CMAX5_ _E
MAX5_ _B
±10µV/°CCode = FF hexMAX5_ _C
Full-Scale Error±14mVCode = FF hex
±10µV/°CCode = 00 hex
Zero-Code-Error Supply Rejection12mV
Code = 00 hex,SS= 0VMAX5_ _M
SYMBOL

TUE
DNL
±14MAX5_ _C
±16MAX5_ _E
Zero-Code Error
Code = 00 hex,SS= -5V ±10%
±20
MAX5_ _M
ZCE
±1.5
Code = 00 hex, VDD= 5V ±10%,
VSS= 0V or -5V ±10%
Zero-Code
Temperature CoefficientMAX5_ _EFull-Scale-Error Supply Rejection
Code = FF hex,
VDD= +5V ±10%,
VSS= 0V or -5V ±10%112
MAX5_ _M
Full-Scale-Error
Temperature Coefficient
STATIC ACCURACY
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
DD= +5V ±10%, VSS= 0V to -5.5V, VREF= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS

Input Voltage Range
SYMBOL

VSSVDDV
MAX5091624
MAX510Input Resistance (Note 1)812kΩCode = 55 hex
MAX50915
(Note 4)ACFeedthrough-70dB
(Note 3)Channel-to-Channel Isolation-60dB
MAX510Input Capacitance (Note 2)30pFCode = 00 hex
VREF = 4V, load regulation ≤1/4LSB2
Full-Scale Output VoltageVSSVDDV
Resistive Load
Input High Voltage2.4VVIH
VREF = -4V, VSS = -5V ±10%,
load regulation ≤1/4LSB
VREF = VDDMAX5_ _C/E,
load regulation ≤1LSB
VREF = VDDMAX5_ _M,
load regulation ≤2LSB
Input Low Voltage0.8VVIL
VIN= 0V or VDDInput Current1.0µAIIN
(Note 5)Input Capacitance10pFCIN
ISOURCE= 0.2mAOutput High VoltageVDD- 0.5VVOH
ISINK= 1.6mAOutput Low Voltage0.4VVOL
MAX5_ _E0.7
MAX5_ _C1.0
MAX5_ _M
Voltage-Output Slew Rate
V/µsPositive and negative
To 1/2LSB, 10kΩII 100pF loadOutput Settling Time (Note 6)6µs
Digital Feedthrough5nV-s
Wideband Amplifier Noise60
MHzVREF = 0.5Vp-p, 3dB bandwidthMultiplying Bandwidth1
VREF = 4Vp-pat 1kHz, VDD= 5V,
code = FF hex
Digital-to-Analog Glitch Impulse
Code 128➝12712nV-s
Code = 00 hex, all digital inputs
from 0V to VDD
Signal-to-Noise + Distortion Ratio
VREF = 4Vp-pat 20kHz, VSS= -5V ±10%74SINAD
µVRMS
REFERENCE INPUTS
DAC OUTPUTS
DIGITAL INPUTS
DIGITAL OUTPUTS
DYNAMIC PERFORMANCE
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
DD= +5V ±10%, VSS= 0V to -5.5V, VREF= 4V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS

Positive Supply Voltage
SYMBOL

4.55.5VFor specified performanceVDD
Negative Supply Voltage-5.50VFor specified performanceVSS
510Positive Supply Current512mAIDD
Negative Supply CurrentmAISS
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
512MAX5_ _M
VSS= -5V ±10%, outputs
unloaded, all digital
inputs = 0V or VDD
Note 1:
Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2:
Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3:
VREF = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 4:
VREF = 4Vp-p, 10kHz. DAC code = 00 hex.
Note 5:
Guaranteed by design.
Note 6:
Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
DD= +5V ±10%, VSS= 0V to -5V, VREF= 4V, AGND = DGND = 0V, CL= 50pF, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERCONDITIONSMINTYPMAXUNITS

CLRPulse Width Low
SYMBOL
25nsMAX5_ _M
MAX5_ _C/E4020
tCLW
MAX5_ _M5025ns
MAX5_ _C/E4020
SCLK Fall to CSRise Hold Time0nstCSH2
SCLK Fall to CSFall Hold Time0ns(Note 7)tCSH0MAX5_ _C/E100MAX5_ _C/E
MAX5_ _C/E40MAX5_ _C/E12.5MAX5_ _C/E
DIN to SCLK Rise Hold Time0nstDH
SCLK Rise to CSRise Hold Time(Note 9)40nstCSH1
LDACPulse Width Low
(Notes 7, 8)0ns
tLDW
tCLLCSRise to LDACFall Setup TimeMAX5_ _C/ECSFall to SCLK Setup Time50nsMAX5_ _MtCSS
DIN to SCLK Rise Setup Time50nsMAX5_ _MtDS
SCLK Clock Frequency2010MHzMAX5_ _MfCLK
SCLK Pulse Width High50nsMAX5_ _MtCH
SCLK Pulse Width LowMAX5_ _M50nstCL
SCLK to DOUT Valid10100nsMAX5_ _MtDO
Note 7:
Guaranteed by design.
Note 8:
If LDACis activated prior to CS's rising edge, it must stay low for tLDWor longer after CSgoes high.
Note 9:
Minimum delay from 12th clock cycle to CSrise.
Outputs unloaded, all
digital inputs = 0V or VDD
POWER SUPPLIES
SERIAL INTERFACE TIMING
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

OUTPUT SINK CURRENT
vs. (VOUT - VSS)
MAX509-FG01
VOUT - VSS (V)
IOUT
(mA)
VDD = VREF = +5V
VSS = GND = 0V
ALL DIGITAL INPUTS = 00 HEX
MAX509-FG10
VOUT (V)
IOUT
(mA)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
VDD = VREF = +5V
VSS = GND
DIGITAL INPUT = FF HEX
SUPPLY CURRENT
vs. TEMPERATURE
MAX509-FG02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)80
IDD
ISS
VDD = +5.5V
VSS = -5.5V
VREF = -4.75
ALL DIGITAL INPUTS = +5V5
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX509-FG03
VREF VOLTAGE (V)
IDD
(mA)-2231-1-3
VDD = +5V
ALL LOGIC
INPUTS = +5V
VSS = -5V
VSS = 0V10k100k
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX509-FG06
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)-30
-1010M
VDD = +5V
VSS = AGND
VREF = 2.5VDC + 0.5Vp-p SINE WAVE
THD + NOISE AT DAC OUTPUT
vs. REFERENCE AMPLITUDE
MAX509-FG04
REFERENCE AMPLITUDE (Vp-p)
THD + NOISE (dB)
0.01%
0.1%
FREQ = 20kHz
FREQ = 1kHz
VDD = +5V
VSS = -5V
INPUT CODE = FF HEX
THD + NOISE (%)
-801k100k
THD + NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY

MAX509-FG05
REFERENCE FREQUENCY (Hz)
THD + NOISE (dB)
10010k
VREF = 8Vp-p
VREF = 1Vp-p
VREF = 4Vp-p
VDD = +5V
VSS = -5V
INPUT CODE = FF HEX
FREQ = SWEPT
10%
0.1%
0.01%
THD + NOISE (%)10k100k
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX509-FG07
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)-30
-1010M
VDD = +5V
VSS = AGND
VREF = 2.5VDC + 0.05Vp-p SINE WAVE10k100k
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE

MAX509-FG08
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)-30
-1010M
VDD = +5V
VSS = -5V
VREF = 2.5VDC + 4Vp-p SINE WAVE
__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)
MAX509/MAX510
Quad, Serial 8-DACs
with Rail-to-Rail Outputs
____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)
A = REFA, 10Vp-p
B = OUTA, 100μV/div, UNLOADED
TIMEBASE = 10μs/div
VDD = +5V, VSS = -5V
CODE = ALL 0s
REFERENCE FEEDTHROUGH AT 40kHz
A = REFA, 10Vp-p
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 1ms/div
REFERENCE FEEDTHROUGH AT 400Hz
A = REFA, 10Vp-p
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 50μs/div
REFERENCE FEEDTHROUGH AT 10kHz50μV
100μS
A = REFA, 10Vp-p
B = OUTA, 50μV/div, UNLOADED
TIMEBASE = 100μs/div
REFERENCE FEEDTHROUGH AT 4kHz10
ZERO-CODE ERROR
vs. NEGATIVE SUPPLY VOLTAGE
MAX509-FG09
VSS (V)
ZERO-CODE ERROR (mV)
VDD = +5V
VREF = +4V
A = CS, 2V/div
B = OUTA, 20mV ˜
TIMEBASE = 200ns/div
WORST-CASE 1LSB DIGITAL STEP CHANGE
200nS20mV
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
100mV
1μS
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1μs/div
VDD = +5V
REF_ = +4V
ALL BITS OFF TO ALL BITS ON
RL = 10kΩ, CL = 100pF
POSITIVE SETTLING TIME
(VSS = AGND OR -5V)100mV
1μS
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1μs/div
VDD = +5V
REF_ = +4V
ALL BITS ON TO ALL BITS OFF
RL = 10kΩ, CL = 100pF
NEGATIVE SETTLING TIME
(VSS = AGND)
____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)
A = SCLK, 333kHz
B = OUT_, 10mV/div
TIMEBASE = 2μs/div
CLOCK FEEDTHROUGH100mV
1μS
A = DIGITAL INPUT, 5V/div
B = OUT_ , 2V/div
TIMEBASE = 1μs/div
VDD = +5V
REF_ = +4V
ALL BITS ON TO ALL BITS OFF
RL = 10kΩ, CL = 100pF
NEGATIVE SETTLING TIME
(VSS = -5V)
NAMEFUNCTIONOUTBDAC B Voltage OutputOUTADAC A Voltage OutputVSSNegative Power Supply, 0V to -5V ±10%. Connect to AGND for single-supply operation.
PIN
MAX509MAX510
REFBReference Voltage Input for DAC BREFABReference Voltage Input for DACs A and BREFAReference Voltage Input for DAC AAGNDAnalog Ground
7, 14N.C.Not Internally ConnectedDGNDDigital Ground
______________________________________________________________Pin Description
DOUT8LDAC7CLR9DIN10SCLK11CS12REFDReference Voltage Input for DAC D–REFCDReference Voltage Input for DACs C and D13
Load DAC Input (active low). Driving this asynchronous input low (level sensitive)
transfers the contents of each input latch to its respective DAC latch.
Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be
clocked out on rising or falling edge of SCLK.REFCReference Voltage Input for DAC C–VDDPositive Power Supply, +5V ±10%14OUTDDAC D Output Voltage15OUTCDAC C Output Voltage16
Clear DAC input (active low). Driving CLRlow causes an asynchronous clear of input
and DAC registers and sets all DAC outputs to zero.
Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the
rising edge of SCLK. CSmust be low for data to be clocked in.
Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the
rising (default) or the falling edge.
Chip-Select Input (active low). Data is shifted in and out when CSis low. Programming
commands are executed when CSrises.
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

• • •
• • •
• • •
• • •A0C1C0D7D6D5D4D3D2D1D0
MSBLSB
DACA
DATA FROM PREVIOUS DATA INPUTDATA FROM PREVIOUS DATA INPUTA0C1C0D7D6D5D4D3D2D1D0
MSBLSB
DACDA0C1C0D7D6D5D4D3D2D1D0A1A0C1C0D7C1C0D7D5D4D3D2D1D0A1A0C1C0D7D6D5D4D3D2D1D0A1D6D5D4D3D2D1D0A1
DOUT
MODE 0
DOUT
MODE 1
(DEFAULT)
DIN
SCLK
• • •
INSTRUCTION
EXECUTED
Figure 1. MAX509/MAX510 3-Wire Interface Timing
_______________Detailed Description
Serial Interface

At power-on, the serial interface and all DACs are
cleared and set to code zero. The serial data output
(DOUT) is set to transition on SCLK's rising edge.
The MAX509/MAX510 communicate with microproces-
sors through a synchronous, full-duplex, 3-wire inter-
face (Figure 1). Data is sent MSB first and can be
transmitted in one 4-bit and one 8-bit (byte) packet or
in one 12-bit word. If a 16-bit control word is used, the
first four bits are ignored. A 4-wire interface adds a line
for LDACand allows asynchronous updating. The serial
clock (SCLK) synchronizes the data transfer. Data is
transmitted and received simultaneously.
Figure 2 shows a detailed serial interface timing.
Please note that the clock should be low if it is stopped
between updates. DOUT does not go into a high-
impedance state if the clock or CSis high.
Serial data is clocked into the data registers in MSB-
first format, with the address and configuration infor-
mation preceding the actual DAC data. Data is
clocked in on SCLK's rising edge while CSis low. Data
at DOUT is clocked out 12 clock cycles later, either at
SCLK's rising edge (default or mode 1) or falling edge
(mode 0).
Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CSmust go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the first bit. With CSlow, data is clocked into the
MAX509/MAX510's internal shift register on the rising
edge of the external serial clock. SCLK can be driven
at rates up to 12.5MHz.
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

• • •
• • •
• • •
• • •
• • •
tLDW
SCLK
DIN
DOUT
LDAC
tDO
tDH
tDS
tCSH0
tCSStCH
tCLtCSH1
tCSH2
tCLL
NOTE: TIMING SPECIFICATION tCLL IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands

Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
“LDAC” Command, all DACs updated from respective
input registers.
12-Bit Serial Word

FunctionLDACD7 . . . . . . . . D0A1
X X X X X X X X1X X X X X X X X1X X X X X X X X0
No Operation (NOP), shifts data in shift register.XX X X X X X X X X
Update all DACs from shift register.X8-Bit DAC DataX
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Serial Input Data Format and Control Codes
The 12-bit serial input format shown in Figure 3 com-
prises two DAC address bits (A1, A0), two control bits
(C1, C0) and eight bits of data (D0...D7).
The 4-bit address/control code configures the DAC as
shown in Table 1.
Load Input Register, DAC Registers Unchanged
(Single Update Operation)

When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.
Load Input and DAC Registers

This command directly loads the selected DAC register
at CS's rising edge. A1 and A0 set the DAC address.
Current shift-register data is placed in the selected
input and DAC registers.
For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 1V, DAC B = 2V,DAC
C = 3V and DAC D = 4V), five commands are required.
First, perform four single input register update opera-
tions. Next, perform an “LDAC” command as a fifth
command. All DACs will be updated from their respec-
tive input registers at the rising edge of CS.
Update All DACs from Shift Registers

All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLRif code 00 hex is pro-
grammed, which clears all DACs.
No Operation (NOP)

The NOP command (no operation) allows data to be shift-
ed through the MAX509/MAX510 shift register without
affecting the input or DAC registers. This is useful in daisy
chaining (also see the Daisy-Chaining Devicessection).
For this command, the data bits are "Don't Cares." As an
example, three MAX509/MAX510s are daisy-chained (A, B
and C), and DAC A and DAC C need to be updated. The
36-bit-wide command would consist of one 12-bit word for
device C, followed by an NOP instruction for device B and
a third 12-bit word with data for device A.At CS's rising
edge, only device B is not updated.
“LDAC” Command (Software)

All DAC registers are updated with the contents of their
respective input registers at CS's rising edge. With the
exception of using CSto execute, this performs the
same function as the asynchronous LDAC.
Set DOUT Phase – SCLK Rising (Mode 1, Default)

Mode 1 resets the serial output DOUT to transition at
SCLK's rising edge. This is the MAX509/MAX510’s
default setting after the supply voltage has been
applied.
The command also loads all DAC registers with the con-
tents of their respective input registers, and is identical to
the “LDAC” command.
MAX509/MAX510
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs

This is the first bit shifted in A0C1 C0 D7D6 ● ● ● D1 D0DINDOUT
Control and
Address bits 8-bit DAC data
MSBLSB
Figure 3. Serial Input Format
(LDAC= H)
(LDAC= x)
(LDAC= x)
(LDAC= x)
(LDAC= x)
(LDAC= H)
1 01 1xxxxxxxxD1D2D3D4D5D6D7C0C1A0A1
8-Bit DAC Data0 0x 0D1D2D3D4D5D6D7C0C1A0A1xxxxxx0 0x 1D1D2D3D4D5D6D7C0C1A0A1
1 00 xxxxxxxxxD1D2D3D4D5D6D7C0C1A0A1
8-Bit Data0 1AddressD1D2D3D4D5D6D7C0C1A0A1
8-Bit Data1 1AddressD1D2D3D4D5D6D7C0C1A0A1
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