MAX5105EEP+-MAX5105EEP+T-MAX5106EEE+-MAX5106EEE+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX5105EEP+T ,Nonvolatile, Quad, 8-Bit DACsApplications(MAX5105)Digital Gain and Offset Adjustments♦ Wide Operating Temperature Range Programm ..
MAX5106EEE ,Nonvolatile, Quad, 8-Bit DACsApplications(MAX5105)Digital Gain and Offset Adjustments Wide Operating Temperature Range Programm ..
MAX5106EEE+ ,Nonvolatile, Quad, 8-Bit DACsMAX5105/MAX510619-1925; Rev 1; 6/01Nonvolatile, Quad, 8-Bit DACs
MAX5106EEE+T ,Nonvolatile, Quad, 8-Bit DACsApplications(MAX5105)Digital Gain and Offset Adjustments♦ Wide Operating Temperature Range Programm ..
MAX510ACPE ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 2; 1/96Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX510ACWE ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 2; 1/96Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX942EUA+T ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply ComparatorsApplicationsMAX941CSA 0°C to +70°C 8 SO● 3V/5V SystemsMAX941EPA -40°C to +85°C 8 PDIP● Battery-Powe ..
MAX944CSD+ ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply ComparatorsApplications 3V or 5V supply. These devices combine high speed, low (Operation Down to 2.7V)power, ..
MAX944EPD ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply ComparatorsApplicationsered from a 3V or 5V supply. These devices combine(operation down to 2.7V)high speed, l ..
MAX944EPD+ ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply ComparatorsElectrical Characteristics(V+ = 2.7V to 5.5V, T = T to T , unless otherwise noted. Typical values a ..
MAX9482EUI , Low-Power, Low-Distortion, Central-Office
MAX9485ETP+ ,Programmable Audio Clock GeneratorApplicationsDigital TVs DVD PlayersSet-Top Boxes HDTVsHome EntertainmentCentersPin ConfigurationsTO ..

MAX5105EEP+-MAX5105EEP+T-MAX5106EEE+-MAX5106EEE+T
Nonvolatile, Quad, 8-Bit DACs
General Description
The MAX5105/MAX5106 nonvolatile, quad, 8-bit digital-
to-analog converters (DACs) operate from a single
+2.7V to +5.5V supply. An internal EEPROM stores the
DAC states even after power is removed. Data from
these nonvolatile registers automatically initialize the
DAC outputs and operating states during power-up.
Precision internal buffers swing Rail-to-Rail®, and the
reference input range includes both ground and the
positive rail.
The MAX5105/MAX5106 feature a software-controlled
10µA shutdown mode and a mute state that drives the
DAC outputs to their respective REFL_ voltages. The
MAX5105 includes an asynchronous MUTE input, as
well as a RDY/BSYoutput that indicates the status of
the nonvolatile memory.
The MAX5105 is available in a 20-pin QSOP and 20-pin
wide SO packages, and the MAX5106 is available in a
16-pin QSOP package.
________________________Applications
Digital Gain and Offset Adjustments
Programmable Attenuators
Portable Instruments
Power-Amp Bias Control
FeaturesOn-Chip EEPROM Stores DAC StatesPower-On Reset Initialization of All Registers to
Prestored States+2.7V to +5.5V Single-Supply OperationFour 8-Bit DACs with Independent High and Low
Reference Inputs (MAX5105)Ground to VDDReference Input RangeRail-to-Rail Output BuffersLow 1mA Supply CurrentLow Power 10µA (max) Shutdown ModeSmall 20- or 16-Pin QSOP PackageSPI™/QSPI™/MICROWIRE™-Compatible Serial
InterfaceAsynchronous MUTE Input (MAX5105)RDY/BSYPin to Indicate Memory Status
(MAX5105)Wide Operating Temperature Range
(-40°C to +85°C)
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
REFH2
REFH3
OUT0
OUT1RDY/BSY
VDD
REFH0
REFH1
TOP VIEW
OUT2
OUT3
REFL3
REFL2DOUT
DIN
CLK
REFL1
REFL0GND
MUTE
MAX5105
20 QSOP/SOIC
REFH1REFH2
REFH3
OUT0
OUT1
OUT2
OUT3
REFL1
REFL0
MAX5106
16 QSOP
REFH0
VDD
DIN
CLK
DOUT
GND
Ordering Information
Pin Configurations
19-1925; Rev 1; 6/01
Functional Diagram appears at end of data sheet.
Rail-to-Rail is a trademark of Nippon Motorola, Ltd.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PARTTEMP RANGE PIN-PACKAGE
MAX5105EEP-40°C to +85°C 20 QSOP
MAX5105EWP-40°C to +85°C 20 SO
MAX5106EEE-40°C to +85°C 16 QSOP
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= VREFH_= +2.7V to +5.5V, GND = VREFL_= 0, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at
VDD = +3V and TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, DIN, CS, CLK, MUTE to GND.............................-0.3V, +6V
DOUT, REFH_, REFL_, RDY/BSY,
OUT_ to GND.........................................-0.3V to (VDD+ 0.3V)
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)........727.3mW
20-Pin SO (derate 10mW/°C above +70°C).................800mW
Operating Temperature Range
MAX510_.........................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
STATIC ACCURACY
Resolution8Bits
Code range 10hex to F0hex,
ILOAD = 50µA±1Integral NonlinearityINL
Full code range, ILOAD = 50µA±2
LSB
Code range 10hex to F0hex,
ILOAD = 50µA±0.5Differential Nonlinearity
(Note 1)DNL
Full code range, ILOAD = 50µA±1
LSB
Zero-Code ErrorZCECode = 0Ahex±20mV
Zero-Code Temperature
CoefficientCode = 0Ahex±20µV/°C
Gain Error (Note 2)Code = F0hex±1LSB
Gain-Error Temperature
CoefficientCode = F0hex±0.002LSB/°C
Power-Supply Rejection RatioPSRR
Code = 0Ahex and FFhex, VDD = 2.7V
to 5.5V, VREFH_ = 2.5V, VREFL_ = 0,
ILOAD = 50µALSB/V
REFERENCE INPUT
Reference Input Voltage RangeVREFH_,
VREFL_0VDDV
Input Resistance92256413kΩ
Input Resistance Matching±0.2±1%
Input Capacitance10pF
DAC OUTPUTS
Output Voltage RangeN = input code, ILOAD = 0VREFL_
(VREFH -
VREFL)
(N/256)
+ VREFL_
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VREFH_= +2.7V to +5.5V, GND = VREFL_= 0, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at
VDD = +3V and TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Output Current (Note 3)ΔVOUT_< 1LSB±1.0mA
Amplifier Output Resistance
(Note 3)3Ω
DIGITAL INPUTS
Input High VoltageVIH0.7 x
VDDV
Input Low VoltageVIL0.8V
Input CurrentIINVIN = 0 or VDD±10μA
Input CapacitanceCIN10pF
DIGITAL OUTPUTS
Output High VoltageVOHISOURCE = 0.4mAVDD
- 0.3V
Output Low VoltageVOLISINK = 1mA0.4V
Three-State Leakage CurrentILEAK±10μA
Three-State Output CapacitanceCOUT15pF
DYNAMIC PERFORMANCE
CLK to OUT_ Settling Time
(Note 4)tCOS6μs
Channel-to-Channel Crosstalk
(Note 5)
VDD = +5V, code = Ffhex,
VREFH_ = 2.5Vp-p at 10kHz85dB
VREFH_ = 2.5Vp-p at
1kHz58
Signal to Noise Plus DistortionSINADVDD = +5V,
code = FFhexVREFH_ = 2.5Vp-p at
10kHz56
Multiplying BandwidthVREFH_ = 0.5Vp-p, 3dB bandwidth250kHz
Reference FeedthroughVDD = +5V, code = 00hex,
VREFH_ = 2.5Vp-p at 1kHz86dB
Clock Feedthrough4nV - s
DAC Output White Noise75nV/√Hz
Shutdown Recovery TimetSDR7μs
Time to ShutdowntSHDN2μs
POWER SUPPLIES
Supply VoltageVDD2.75.5V
ILOAD = 0, digital inputs at GND or VDD0.81.0Supply CurrentIDDDuring nonvolatile write operation20mA
Shutdown Current0.510μA
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD= VREFH_= +2.7V to +5.5V, GND = VREFL_= 0, CL= 100pF, TA= TMINto TMAX, unless otherwise noted. Typical values are at
VDD = +3V and TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL TIMING
CLK PeriodtCP1μs
CLK High TimetCH300ns
CLK Low TimetCL300ns
CS High TimetCSHT150ns
CS Setup TimetCSS100ns
CS Hold TimetCSH0ns
DIN Setup TimetDS100ns
DIN Hold TimetDH0ns
CLK to DOUT Valid TimetCDVCLOAD = 100pF1μs
CLK to DOUT Propagation DelaytCDCLOAD = 100pF1μs
DOUT Disable TimetCSDCLOAD = 100pF250ns
Nonvolatile Store TimetBUSY13ms
NONVOLATILE MEMORY RELIABILITY
Data RetentionMIL STD-883 Test Method 1008100Years
EnduranceMIL STD-883 Test Method 1033100,000Stores
Note 1:Guaranteed monotonic.
Note 2:Gain error is: [100 x (VF0(MEAS)- ZCE - VF0(IDEAL))/VREFH]; where VF0(MEAS)is the DAC output voltage with input code
F0hex. VF0(IDEAL)is the ideal DAC output voltage with input code F0hex (i.e., (VREFH- VREFL) ×240/256 + VREFL).
Note 3:In the voltage range, 0.5V < VOUT_ < VDD - 0.5V.
Note 4:Output settling time is measured from the 50% point of the rising edge of last CLK to 1/2LSB of VOUT’s final value for a code
transition from 10hex to F0hex. See Figure 4.
Note 5:Channel-to-channel crosstalk is defined as the coupling from one driven reference with input code = FFhex to any other
DAC output with the reference of that DAC at a constant value and input code = 00hex.
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
DAC ZERO-CODE OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX5105/06 toc01
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
VDD = +3V
VREFL_ = +0.2VVDD = +5V
VREFL_ = +0.2V
CODE = 00hex26810
DAC FULL-SCALE OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX5105/06 toc02
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
VDD = VREFH_ = +5V
VDD = VREFH_ = +3V
SUPPLY CURRENT vs. TEMPERATURE
MAX5105/06 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (
VDD = +5V
VREFH_ = +4.096V
VDD = +3V
VREFH_ = +2.5V
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX5105/06 toc04
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (
CODE = FFhex
CODE = 00hex
VDD = +3V0
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
MAX5105/06 toc05
REFERENCE VOLTAGE (V)
SUPPLY CURRENT (
CODE = FFhex
CODE = 00hex
VDD = +5V-70
THD + NOISE AT DAC OUTPUT
vs. REFERENCE AMPLITUDE
MAX5105/06 toc06
REFERENCE AMPLITUDE (Vp-p)
THD + NOISE (dB)
VREF = SINE-WAVE
VDD = +3.0V
CENTERED AT 1.5V
DAC CODE = FFhex
80kHz LOWPASS FILTER
fVREF = 1kHz
fVREF = 10kHz
THD + NOISE AT DAC OUTPUT
vs. REFERENCE AMPLITUDE
MAX5105/06 toc07
REFERENCE AMPLITUDE (Vp-p)
THD + NOISE (dB)
VREF = SINE-WAVE
VDD = +5.0V
CENTERED AT 2.5V
DAC CODE = FFhex
80kHz LOWPASS FILTER
fVREF = 1kHzfVREF = 10kHz
-701k10k100100k
THD + NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX5105/06 toc08
FREQUENCY (Hz)
THD + NOISE (dB)
VREF = SINE-WAVE
VDD = +3.0V
CENTERED AT 1.5V
DAC CODE = FFhex
500kHz LOWPASS FILTER
VREF = 1Vp-pVREF = 0.5Vp-p
VREF = 2Vp-p
-701k10k100100k
THD + NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
MAX5105/06 toc09
FREQUENCY (Hz)
THD + NOISE (dB)
VREF = SINE-WAVE
VDD = +5.0V
CENTERED AT 2.5V
DAC CODE = FFhex
500kHz LOWPASS FILTER
VREF = 2.5Vp-pVREF = 1Vp-p
VREF = 2Vp-p
Typical Operating Characteristics
(RL= ∞, code = FFhex, VREFL_= GND, TA= +25°C, unless otherwise noted.)
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
Typical Operating Characteristics (continued)
(RL= ∞, code = FFhex, VREFL_= GND, TA= +25°C, unless otherwise noted.)10k1M100101k100k10M100M
REFERENCE INPUT FREQUENCY
RESPONSE
MAX5105/06 toc10
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
VREF = 0.5Vp-p SINE-WAVE
CENTERED AT +2.5V
DAC CODE = FFhex
VDD = +5.0V10k1M100101k100k10M100M
REFERENCE FEEDTHROUGH
vs. FREQUENCY
MAX5105/06 toc11
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
VREF = 2.5Vp-p SINE-WAVE
CENTERED AT +2.5V
DAC CODE = FFhex
VDD = +5V10k1M100101k100k10M100M
CROSSTALK
vs. FREQUENCY
MAX5105/06 toc12
FREQUENCY (Hz)
RELATIVE OUTPUT (dB)
VREH0 = 3Vp-p SINE-WAVE
CENTERED AT +2.5V
DAC0 CODE = FFhex
VREFH1 = GND
DAC1 CODE = 00hex
VDD = +5V
1.0 μs/div
1LSB DIGITAL STEP-CHANGE
(NEGATIVE)
50mV/div
MAX5105/06 toc13
OUT1
VDD = +3.0V
VREFH1 = +2.5V
CLOAD = 100pF
fCLK = 500kHz
CODE = 80 HEX TO 7F HEX
RL = 10kΩ
1.0 μs/div
1LSB DIGITAL STEP-CHANGE
(NEGATIVE)
50mV/div
MAX5105/06 toc14
OUT1
VDD = +5.0V
VREFH1 = +4.096V
CLOAD = 100pF
fCLK = 500kHz
CODE = 80 HEX TO 7F HEX
RL = 10kΩ
1.0 μs/div
1LSB DIGITAL STEP-CHANGE
(POSITIVE)
50mV/div
MAX5105/06 toc16
OUT1
VDD = +5.0V
VREFH1 = +4.096V
CLOAD = 100pF
fCLK = 500kHz
CODE = 7F HEX TO 80 HEX
RL = 10kΩ
1.0 μs/div
CLOCK FEEDTHROUGH
CLK
10mV/div
MAX5105/06 toc17
OUT1
VDD = +3.0V
VREFH1 = +2.5V
CLOAD = 100pF
fCLK = 500kHz
CODE = 00 HEX
RL = 10kΩ
1.0 μs/div
CLOCK FEEDTHROUGH
CLK
10mV/div
MAX5105/06 toc18
OUT1
VDD = +5.0V
VREFH1 = +4.096V
CLOAD = 100pF
fCLK = 500kHz
CODE = 00 HEX
RL = 10kΩ
1.0 μs/div
1LSB DIGITAL STEP-CHANGE
(POSITIVE)
50mV/div
MAX5105/06 toc15
OUT1
VDD = +3.0V
VREFH1 = +2.5V
CLOAD = 100pF
fCLK = 500kHz
CODE = 7F HEX TO 80 HEX
RL = 10kΩ
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
1.0 μs/div
POSITIVE SETTLING TIME
MAX5105/06 toc19
OUT1
VDD = +3.0V
VREFH1 = +2.5V
CLOAD = 100pF
fCLK = 500kHz
CODE = 00 HEX TO FF HEX
RL = 10kΩ
2.5V
2.0 μs/div
POSITIVE SETTLING TIME
MAX5105/06 toc20
OUT1
VDD = +5.0V
VREFH1 = +4.096V
CLOAD = 100pF
fCLK = 500kHz
CODE = 00 HEX TO FF HEX
RL = 10kΩ
4.096V
1.0 μs/div
NEGATIVE SETTLING TIME
MAX5105/06 toc21
OUT1
VDD = +3.0V
VREFH1 = +2.5V
CLOAD = 100pF
fCLK = 500kHz
CODE = FF HEX TO 00 HEX
RL = 10kΩ
2.5V
2.0 μs/div
NEGATIVE SETTLING TIME
MAX5105/06 toc22
OUT1
VDD = +5.0V
VREFH1 = +4.096V
CLOAD = 100pF
fCLK = 500kHz
CODE = FF HEX TO 00 HEX
RL = 10kΩ
4.096V
Typical Operating Characteristics (continued)
(RL= ∞, code = FFhex, VREFL_= GND, TA= +25°C, unless otherwise noted.)
Detailed Description
The MAX5105/MAX5106 quad, 8-bit DACs feature an
internal, nonvolatile EEPROM, which stores the DAC
states for initialization during power-up. These devices
consist of four resistor string DACs, four rail-to-rail
buffers, a 14-bit shift register, oscillator, power-on reset
(POR) circuitry, and five volatile and five nonvolatile
memory registers (Functional Diagram). The shift regis-
ter decodes the control and address bits, routing the
data to the proper memory registers. Data can be writ-
ten to a selected volatile register, immediately updating
the DAC output, or can be written to a selected non-
volatile register for storage.
The five volatile registers retain data as long as the
device is enabled and powered. Once power is
removed or the device is shut down, the volatile regis-
ters are cleared. The nonvolatile registers retain data
even after power is removed. On power-up, the POR
circuitry and internal oscillator control the transfer of
data from the nonvolatile registers to the volatile regis-
ters, which automatically initializes the device upon
startup. Data can be read from the nonvolatile registers
through DOUT.
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
Pin Description
PIN
MAX5105MAX5106
NAMEFUNCTION1REFH1DAC1 High Reference Input2REFH0DAC0 High Reference InputVDDPositive Supply Voltage—RDY/BSYReady/Busy Open-Drain Output. Indicates the state of the nonvolatile memory.
Connect a 100kΩ pullup resistor from RDY/BSY to VDD.4CLKSerial Clock InputCSChip Select Input6DINSerial Data Input7DOUTSerial Data Output—MUTEMute Input. Drives all DAC outputs to their respective REFL_ voltages.8GNDGround. Serves as REFL2 and REFL3 for the MAX5106.9REFL0DAC0 Low Reference Input10REFL1DAC1 Low Reference Input—REFL2DAC2 Low Reference Input—REFL3DAC3 Low Reference Input11OUT3DAC3 Output12OUT2DAC2 Output13OUT1DAC1 Output14OUT0DAC0 Output15REFH3DAC3 High Reference Input16REFH2DAC2 High Reference Input
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
DAC Operation
The MAX5105/MAX5106 use a matrix decoding archi-
tecture for the DACs, which saves power in the overall
system. A resistor string placed in a matrix fashion
divides down the difference between the external refer-
ence voltages, VREFHand VREFL. Row and column
decoders select the appropriate tab from the resistor
string, providing the needed analog voltages. The
resistor string presents a code-independent input
impedance to the reference and guarantees a monoto-
nic output. Figure 1 shows a simplified diagram of one
of the four DACs.
Output Buffer Amplifiers
All MAX5105/MAX5106 analog outputs are internally
buffered by precision unity-gain followers that slew at
about 0.5V/µs. The outputs can swing from GND to
VDD. With a VREFL_ to VREFH_ (or VREFH_to VREFL_)
output transition, the amplifier outputs typically settle to
±1/2LSB in 6µs when loaded with 10kΩin parallel with
100pF.
The software mute/shutdown command independently
drives each output to its respective REFL_ voltage
(mute) or to a high-impedance state (shutdown).
Placing all four DACs in shutdown reduces supply cur-
rent to 10µA (max). The MAX5105 also provides an
asynchronous MUTE input, simultaneously driving all
DAC outputs to their respective REFL_ voltages.
Internal EEPROM
The MAX5105/MAX5106 internal EEPROM consists of
five nonvolatile registers that retain the DAC output and
operating states after the device is powered down.
Four registers store data for each DAC, and one stores
the mute and shutdown states for the device.
DAC Registers
The MAX5105/MAX5106 have eight 8-bit DAC regis-
ters, four volatile and four nonvolatile, that store DAC
data. The four volatile DAC registers hold the current
value of each DAC. Data is written to these registers in
two ways: directly from DIN or loaded from the respec-
tive nonvolatile registers (see Serial Input Data Format
and Control Codes). These registers are cleared when
the device is shut down or power is removed.
The four nonvolatile registers retain the DAC values
even after power is removed. Stored data is accessed
in two ways: transferring data to a volatile register to
update the respective DAC output or reading data
through DOUT (see Serial Input Data Format and
Control Codes). On power-up, the device is automati-
cally initialized with data stored in the nonvolatile regis-
ters.
Mute/Shutdown Registers
The MAX5105/MAX5106 have two 8-bit mute/shutdown
registers that store the operating state of each DAC.
The four MSBs hold the mute states, and the four LSBs
hold the shutdown states (Table 1). The volatile regis-
ters hold the current mute/shutdown state of each DAC.
Like the DAC registers, the nonvolatile mute/shutdown
register maintains its data after the device is powered
down, and the contents can be read on DOUT. The
volatile register is initialized with the nonvolatile data on
power-up and can be loaded through DIN or from the
nonvolatile register (see Serial Input Data Format and
Control Codes).
REFH
REFL
R1 R15
R16
R255
R0
D7
D6
D4
DAC
MSB DECODER
D3 D0 D2D1
LSB DECODER
Figure 1. DAC Simplified Circuit Diagram
Table 1. Mute/Shutdown Register Mapping
Bit in
Register
(MSB)D6D5D4D3D2D1D0
(LSB)o n t r o l lin g u n c t io n
Mute
DAC3
Mute
DAC2
Mute
DAC1
Mute
DAC0
Shutdown
DAC3
Shutdown
DAC2
Shutdown
DAC1
Shutdown
DAC0
MAX5105/MAX5106
Nonvolatile, Quad, 8-Bit DACs
14-BIT SERIAL WORD
STARTC1C0A2A1A0D7–D0FUNCTION000008-bit DAC
data
Write DAC data to DAC0 nonvolatile register. Output remains
unchanged.000018-bit DAC
data
Write DAC data to DAC1 nonvolatile register. Output remains
unchanged.000108-bit DAC
data
Write DAC data to DAC2 nonvolatile register. Output remains
unchanged.000118-bit DAC
data
Write DAC data to DAC3 nonvolatile register. Output remains
unchanged.001008-bit DAC
data
Write shutdown and mute states to nonvolatile register. A 1 in bits
D7–D4 mutes the respective DAC; a 1 in bits D3–D0 shuts down
the respective DAC (Table 1). Outputs remain unchanged.010008-bit DAC
data
Write DAC data to DAC0 volatile register and update OUT0.
All other DAC outputs remain unchanged.010018-bit DAC
data
Write DAC data to DAC1 volatile register and update OUT1.
All other DAC outputs remain unchanged.010108-bit DAC
data
Write DAC data to DAC2 volatile register and update OUT2.
All other DAC outputs remain unchanged.010118-bit DAC
data
Write DAC data to DAC3 volatile register and update OUT3.
All other DAC outputs remain unchanged.011008-bit DAC
data
Write shutdown and mute states to volatile register. A 1 in bits
D7–D4 mutes the respective DAC; a 1 in bits D3–D0 shuts down
the respective DAC (Table 1). DAC outputs updated to their
respective mute/shutdown states.10000XXXXXXXX
Read DAC0 nonvolatile register. Contents of DAC0 nonvolatile
register available on DOUT. D7–D0 are ignored, and all DAC
outputs remain unchanged.10001XXXXXXXX
Read DAC1 nonvolatile register. Contents of DAC1 nonvolatile
register available on DOUT. D7–D0 are ignored, and all DAC
outputs remain unchanged.10010XXXXXXXX
Read DAC2 nonvolatile register. Contents of DAC2 nonvolatile
register available on DOUT. D7–D0 are ignored, and all DAC
outputs remain unchanged.10011XXXXXXXX
Read DAC3 nonvolatile register. Contents of DAC3 nonvolatile
register available on DOUT. D7–D0 are ignored, and all DAC
outputs remain unchanged.10100XXXXXXXX
Read mute/shutdown nonvolatile register. Contents of
mute/shutdown nonvolatile register available on DOUT. D7–D0 are
ignored, and all DAC outputs remain unchanged.
Table 2. Serial Interface Programming Commands

Partno	Mfg	Dc	Qty	Available	Descript
MAX5106EEE+	MAIXM	N/a	2500	avai	Nonvolatile, Quad, 8-Bit DACs
MAX5106EEE+T	MAXIM	N/a	2500	avai	Nonvolatile, Quad, 8-Bit DACs
MAX5105EEP+ \|MAX5105EEP	MAXIN	N/a	348	avai	Nonvolatile, Quad, 8-Bit DACs
MAX5105EEP+T \|MAX5105EEPT	MAXIM	N/a	6311	avai	Nonvolatile, Quad, 8-Bit DACs