MAX5098AATJ+ ,Dual, 2.2MHz, Buck or Boost Converter with 80V Load-Dump ProtectionApplications● IndustrialPin Configuration appears at end of data sheet.19-4111; Rev 1; 10/14Downloa ..
MAX509ACAP ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsELECTRICAL CHARACTERISTICS(V = +5V ±10%, V = 0V to -5.5V, V = 4V, AGND = DGND = 0V, R = 10kΩ, C = 1 ..
MAX509ACAP+ ,Quad, Serial, 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 3; 12/10Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX509ACPP ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsFeaturesThe MAX509/MAX510 are quad, serial-input, 8-bit volt- ' Single +5V or Dual ±5V Supply Opera ..
MAX509ACWP ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 2; 1/96Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX509AEAP ,Quad, Serial 8-Bit DACs with Rail-to-Rail OutputsMAX509/MAX51019-0155; Rev 2; 1/96Quad, Serial 8-Bit DACswith Rail-to-Rail Outputs_______________
MAX941CPA+ ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply ComparatorsApplications 3V or 5V supply. These devices combine high speed, low (Operation Down to 2.7V)power, ..
MAX941CSA ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply ComparatorsMAX941/MAX942/MAX94419-0229; Rev 3; 6/97High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply Co ..
MAX941CSA ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply ComparatorsApplicationsMAX941CSA 0°C to +70°C 8 SO3V/5V SystemsMAX941C/D 0°C to +70°C Dice*Battery-Powered Sys ..
MAX941CSA ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply ComparatorsELECTRICAL CHARACTERISTICS(V+ = 2.7V to 6.0V, T = T to T , unless otherwise noted. Typical values a ..
MAX941CSA-T ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail, Single-Supply ComparatorsFeaturesThe MAX941/MAX942/MAX944 are single/dual/quad high- ● Available in μMAX Packagespeed compar ..
MAX941ESA ,High-Speed, Low-Power, 3V/5V, Rail-to-Rail Single-Supply ComparatorsApplicationsMAX941CSA 0°C to +70°C 8 SO3V/5V SystemsMAX941C/D 0°C to +70°C Dice*Battery-Powered Sys ..
MAX5098AATJ+
Dual, 2.2MHz, Buck or Boost Converter with 80V Load-Dump Protection
Pin Configuration appears at end of data sheet.
General DescriptionThe MAX5098A is a dual-output, high-switching-
frequency DC-DC converter with integrated n-channel
switches that can be used either in high-side or low-
side configuration. Each output can be configured either
as a buck converter or a boost converter. In the buck
configuration, this device delivers up to 2A from
converter 1 and 1A from converter 2. The MAX5098A also
integrates a load-dump protection circuitry that is capable
of handling load-dump transients up to 80V for industrial
applications. The load-dump protection circuit utilizes
an internal charge pump to drive the gate of an external
n-channel MOSFET. When an overvoltage or load-dump
condition occurs, the series protection MOSFET absorbs
the high-voltage transient to prevent damage to lower-
voltage components.
The DC-DC converters operate over a wide operating
voltage range from 4.5V to 19V. The MAX5098A operates
180° out-of-phase with an adjustable switching frequency
to minimize external components while allowing the ability
to make trade-offs between the size, efficiency, and cost.
This device utilizes voltage-mode control for stable
operation and external compensation; thus, the loop gain
is tailored to optimize component selection and transient
response. This device can be synchronized to an external
clock fed at the SYNC input. Also, a clock output (CKO)
allows a master-slave connection of two devices with a
four-phase synchronized switching sequence. Additional
features include internal digital soft-start, individual enable
for each DC-DC regulator (EN1 and EN2), open-drain
power-good outputs (PGOOD1 and PGOOD2), and a
shutdown input (ON/OFF).
Other features of the MAX5098A include overvolt-
age protection, short-circuit (hiccup current limit), and
thermal protection. The MAX5098A is available in
a thermally enhanced, exposed pad, 5mm x 5mm,
32-pin TQFN package and is fully specified over the
-40°C to +125°C temperature range.
Applications●Industrial
Features●Wide 4.5V to 5.5V or 5.2V to 19V Input Voltage
Range (with Up to 80V Load-Dump Protection)●Dual-Output DC-DC Converter with Integrated Power
MOSFETs●Each Output Configurable in Buck or Boost Mode●Adjustable Outputs from 0.8V to 0.85VIN Buck
Configuration) and from VIN to 28V (Boost
Configuration)●IOUT1 and IOUT2 of 2A and 1A (Respectively) in
Buck Configuration●Switching Frequency Programmable from 200kHz to
2.2MHz●Synchronization Input (SYNC)●Clock Output (CKO) for Four-Phase Master-Slave
Operation●Individual Converter Enable Input and Power-Good
Output●Low-IQ (7µA) Standby Current (ON/OFF)●Internal Digital Soft-Start and Soft-Stop●Short-Circuit Protection on Outputs and Maximum
Duty-Cycle Limit●Overvoltage Protection on Outputs with Auto Restart●Thermal Shutdown●Thermally Enhanced 32-Pin TQFN Package
Dissipates Up to 2.7W at +70°C +Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PARTTEMP RANGEPIN-PACKAGEMAX5098AATJ+-40°C to +125°C32 TQFN-EP*
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Ordering Information
EVALUATION KIT AVAILABLE
V+ to SGND ..........................................................-0.3V to +25V
V+ to IN_HIGH .........................................................-19V to +6V
IN_HIGH to SGND ................................................-0.3V to +19V
IN_HIGH Maximum Input Current ......................................60mA
BYPASS to SGND ................................................-0.3V to +2.5V
GATE to V+ ...........................................................-0.3V to +12V
GATE to SGND .....................................................-0.3V to +36V
SGND to PGND_..................................................-0.3V to +0.3V
VL to SGND ................-0.3V to the Lower of +6V or (V+ + 0.3V)
VDRV to SGND .......................................................-0.3V to +6V
BST1/VDD1, BST2/VDD2, DRAIN_,
PGOOD_ to SGND ............................................-0.3V to +30V
ON/OFF to SGND .............................-0.3V to (IN_HIGH + 0.3V)
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2...................................-0.3V to +6V
SOURCE_ to SGND..............................................-0.6V to +25V
SOURCE_ to PGND_..............................................-1V for 50ns
EN_ to SGND ..........................................................-0.3V to +6V
OSC, FSEL_1, COMP_, SYNC,
FB_ to SGND...........................................-0.3V to (VL + 0.3V)
CKO to SGND .......................................-0.3V to (VDRV + 0.3V)
SOURCE1, DRAIN1 Peak Current ............................5A for 1ms
SOURCE2, DRAIN2 Peak Current ............................3A for 1ms
VL, BYPASS to
SGND Short Circuit ................ Continuous, Internally Limited
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFN-EP (derate 34.5mW/°C above +70°C) ...2759mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range ...........................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND_ = SGND,
CBYPASS = 0.22µF (low ESR), CVL = 4.7µF (ceramic), CV+ = 1µF (low ESR), CIN_HIGH = 1µF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ,
TJ = -40°C to +125°C, unless otherwise noted.) (Note 2)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information
on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SYSTEM SPECIFICATIONSInput Voltage RangeV+V+ = IN_HIGH5.219VVL = V+ = IN_HIGH (Note 3)4.55.5
V+ Operating Supply CurrentIQVL unloaded, no switching4.2mA
V+ Standby Supply CurrentIV+STBYVEN_ = 0V, PGOOD_ unconnected, V+ =
VIN_HIGH = 14V0.751.1mA
Efficiencyh
(VOUT1 = 5V at 1.5A,
VOUT2 = 3.3V at 0.75A,
fSW = 1.85MHz
V+ = VL = 5.2V78V+ = 12V76
V+ = 16V70
OVERVOLTAGE PROTECTORIN_HIGH Clamp VoltageIN_HIGHISINK = 10mA192021V
IN_HIGH Clamp Load
Regulation1mA < ISINK < 50mA160mV
IN_HIGH Supply CurrentIIN_HIGHVEN_ = VPGOOD_ = VGATE = 0V,
VIN_HIGH = VON/OFF = 14V270600µA
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Electrical CharacteristicsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
Package Thermal Characteristics (Note 1)Junction-to-Ambient Thermal Resistance (θJA) ...........29.0°C/W
Junction-to-Case Thermal Resistance (θJC) ..................1.7°C/W
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND_ = SGND,
CBYPASS = 0.22µF (low ESR), CVL = 4.7µF (ceramic), CV+ = 1µF (low ESR), CIN_HIGH = 1µF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ,
TJ = -40°C to +125°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSIN_HIGH Standby Supply
CurrentIIN_HIGHSTBY
VON/OFF = 0V, PGOOD_ = V+ =
unconnected, VIN_HIGH = 14V, TA = -40°C
to +85°C9µA
V+ to IN_HIGH Overvoltage
ClampVOVVOV = V+ - VIN_HIGH, IGATE = 0mA
(sinking)1.21.852.5V
IN_HIGH Startup VoltageIN_HIGH
UVLO
Rising, ON/OFF = IN_HIGH, GATE rising3.64.1VFalling, ON/OFF = IN_HIGH, GATE falling3.45
GATE Charge CurrentIGATE_CHVIN_HIGH = VON/OFF = 14V,
VGATE = V+ = 0V204580µA
GATE Output VoltageVGATE –
VIN_HIGH
V+ = VIN_HIGH = VON/OFF = 4.5V,
IGATE = 1µA, sourcing4.05.37.5V+ = VIN_HIGH = VON/OFF = 14V,
IGATE = 1µA, sourcing9
GATE Turn-Off Pulldown
CurrentIGATE_PDVIN_HIGH = 14V, VON/OFF = 0V, V+ = 0V,
VGATE = 5V, sinking3.6mA
STARTUP/VL REGULATORVL Undervoltage Lockout Trip
LevelUVLOVL falling3.94.14.3V
VL Undervoltage Lockout
Hysteresis180mV
VL Output VoltageVLISOURCE_ = 0 to 40mA, 5.5V ≤ V+ ≤ 19V5.05.25.5V
VL LDO Short-Circuit CurrentIVL_SHORTV+ = VIN_HIGH = 5.2V130mA
VL LDO Dropout VoltageVLDOISOURCE_ = 40mA, V+ = VIN_HIGH = 4.5V300550mV
BYPASS OUTPUTBYPASS VoltageVBYPASSIBYPASS = 0µA1.982.002.02V
BYPASS Load Regulation∆VBYPASS0 < IBYPASS < 100µA (sourcing)25mV
SOFT-START/SOFT-STOPDigital Ramp Period Soft-
Start/Soft-StopInternal 6-bit DAC2048
fSW
Clock
Cycles
Soft-Start/Soft-Stop64Steps
VOLTAGE-ERROR AMPLIFIERFB_ Input Bias CurrentIFB_250nA
FB_ Input Voltage Set PointVFB_-40°C ≤ TA ≤ +85°C0.7830.80.809V-40°C ≤ TA ≤ +125°C0.7850.814
FB_ to COMP_
TransconductancegM1.42.43.4mS
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Electrical Characteristics (continued)
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND_ = SGND,
CBYPASS = 0.22µF (low ESR), CVL = 4.7µF (ceramic), CV+ = 1µF (low ESR), CIN_HIGH = 1µF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ,
TJ = -40°C to +125°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL MOSFETsOn-Resistance High-Side
MOSFET Converter 1RON1
ISWITCH = 100mA, BST1/VDD1 to
VSOURCE1 = 5.2V195
ISWITCH = 100mA, BST1/VDD1 to
VSOURCE1 = 4.5V208355
On-Resistance High-Side
MOSFET Converter 2RON2
ISWITCH = 100mA, BST2/VDD2 to
VSOURCE2 = 5.2V280
ISWITCH = 100mA, BST2/VDD2 to
VSOURCE2 = 4.5V300520
Minimum Converter 1 Output
CurrentIOUT1VOUT1 = 5V, V+ = 12V (Note 4)2A
Minimum Converter 2 Output
CurrentIOUT2VOUT2 = 3.3V, V+ = 12V (Note 4)1A
Converter 1/Converter 2
MOSFET DRAIN_ Leakage
Current
ILK12VEN1 = VEN2 = 0V, VDRAIN_ = 19V,
VSOURCE_ = 0V20µA
Internal Weak Low-Side Switch
On-ResistanceRONLSSW_ILSSW = 30mA22Ω
INTERNAL SWITCH CURRENT LIMITInternal Switch Current-Limit
Converter 1ICL1V+ = VIN_HIGH = 5.2V, VL = VDRV =
VBST_/VDD_ = 5.2V2.83.454.3A
Internal Switch Current-Limit
Converter 2ICL2V+ = VIN_HIGH = 5.2V, VL = VDRV =
VBST_/VDD_ = 5.2V1.752.12.6A
SWITCHING FREQUENCYPWM Maximum Duty CycleDMAXSYNC = SGND, fSW = 1.25MHz829095%
Switching Frequency RangefSW2002200kHz
Switching FrequencyfSWROSC = 6.81kΩ, each converter
(FSEL_1 = VL)1.71.92.1MHz
Switching Frequency Accuracy5.6kΩ < ROSC < 10kΩ, 1%5%
10kΩ < ROSC < 62.5kΩ, 1%7
SYNC Frequency RangefSYNC
SYNC input frequency is twice the
individual converter frequency,
FSEL_1 = VL (see the Setting the
Switching Frequency section)
4004400kHz
SYNC High ThresholdVSYNCH2V
SYNC Low ThresholdVSYNCL0.8V
SYNC Input LeakageISYNC_LEAK2µA
SYNC Input Minimum Pulse
WidthtSYNCIN100ns
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Electrical Characteristics (continued)
Note 2: 100% tested at TA = +25°C and TA = +125°C. Specifications at TA = -40°C are guaranteed by design and not production
tested.
Note 3: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to IN_HIGH and VL for 5V operation.
Note 4: Output current is limited by the power dissipation of the package; see the Power Dissipation section in the Applications
Information section.
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND_ = SGND,
CBYPASS = 0.22µF (low ESR), CVL = 4.7µF (ceramic), CV+ = 1µF (low ESR), CIN_HIGH = 1µF (ceramic), RIN_HIGH = 3.9kΩ, ROSC = 10kΩ,
TJ = -40°C to +125°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSClock Output Phase DelayCKOPHASEROSC = 62.5kΩ, with respect to converter
2/SOURCE2 waveform 40Degrees
SYNC to Source 1 Phase DelaySYNCPHASEROSC = 62.5kΩ90Degrees
Clock Output High LevelVCKOHVL = 5.2V, sourcing 5mA3.6V
Clock Output Low LevelVCKOLVL = 5.2V, sinking 5mA0.6V
FSEL_1FSEL_1 Input High ThresholdVIH2V
FSEL_1 Input Low ThresholdVIL0.8V
FSEL_1 Input LeakageIFSEL_1_LEAK2µA
ON/OFFON/OFF Input High ThresholdVIH2V
ON/OFF Input Low ThresholdVIL0.8V
ON/OFF Input Leakage CurrentION/OFF_LEAKVON/OFF = 5V0.262.00µA
EN_ INPUTSEN_ Input High ThresholdVIHEN_ rising1.92.02.1V
EN_ Input HysteresisVEN_HYS0.5V
EN_ Input Leakage CurrentIEN_LEAK-1+1µA
POWER-GOOD OUTPUT (PGOOD1, PGOOD2)PGOOD_ ThresholdVTPGOOD_Falling9092.595% VFB_
PGOOD_ Output VoltageVPGOOD_ISINK = 3mA0.4V
PGOOD_ Output Leakage
CurrentILKPGOOD_V+ = VL = VIN_HIGH = VEN_ = 5.2V,
VPGOOD_ = 23V, VFB_ = 1V2µA
OUTPUT OVERVOLTAGE PROTECTIONFB_ OVP Threshold RisingVOVP_R107114121% VFB_
FB_ OVP Threshold FallingVOVP_F12.5V
THERMAL PROTECTIONThermal ShutdownTSHDNRising+165°C
Thermal HysteresisTHYST20°C
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Electrical Characteristics (continued)
(See the Typical Application Circuit, unless otherwise noted. V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means
that N1 is shorted externally.)
EACH CONVERTER SWITCHING
FREQUENCY vs. TEMPERATUREMAX5098A toc09
SWITCHING FREQUENCY (MHz)3065100
0.3MHz
0.6MHz
1.25MHz
1.85MHz2.2MHz
FSEL_1 = VL
EACH CONVERTER SWITCHING
FREQUENCY vs. ROSCMAX5098A toc08
SWITCHING FREQUENCY (MHz)402080
CONVERTER 1, CONVERTER 2
CONVERTER 1
FSEL_1 = VL,
FSEL_1 = GND,
VL OUTPUT VOLTAGE
vs. CONVERTER SWITCHING FREQUENCYMAX5098A toc07
OUTPUT VOLTAGE (V)
VIN = 4.5V
VIN = 5.5VVIN = 8VVIN = 19V
VIN = 5V
BOTH CONVERTERS SWITCHING
FSEL_1 = VL
OUTPUT2 VOLTAGE
vs. LOAD CURRENTMAX5098A toc06
LOAD (A)
OUTPUT2 VOLTAGE (V)
VIN = 5.5VVIN = 16VVIN = 14V
VOUT = 3.3V
fSW = 1.85MHz
OUTPUT1 VOLTAGE
vs. LOAD CURRENTMAX5098A toc05
LOAD (A)
OUTPUT1 VOLTAGE (V)
VIN = 8VVIN = 14VVIN = 16V
VOUT = 5V
fSW = 1.85MHz
OUTPUT2 EFFICIENCY
vs. LOAD CURRENTMAX5098A toc04
LOAD (A)
OUTPUT2 EFFICIENCY (%)
VIN = 16V
VIN = 8V
VIN = 14V
VIN = 5.5V
VIN = 4.5V
VOUT = 3.3V
fSW = 300kHz
L2 = 27µH
OUTPUT1 EFFICIENCY
vs. LOAD CURRENTMAX5098A toc03
LOAD (A)
OUTPUT1 EFFICIENCY (%)
VIN = 8V
VIN = 14VVIN = 16V
VOUT = 5V
fSW = 300kHz
L1 = 18µH
OUTPUT2 EFFICIENCY
vs. LOAD CURRENTMAX5098A toc02
LOAD (A)
OUTPUT2 EFFICIENCY (%)
VIN = 16VVIN = 8VVIN = 14V
VIN = 5.5V
VIN = 4.5V
VOUT = 3.3V
fSW = 1.85MHz
OUTPUT1 EFFICIENCY
vs. LOAD CURRENTMAX5098A toc01
LOAD (A)
OUTPUT1 EFFICIENCY (%)
VIN = 8V
VIN = 14VVIN = 16V
VOUT = 5V
fSW = 1.85MHz
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Typical Operating Characteristics
(See the Typical Application Circuit, unless otherwise noted. V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means
that N1 is shorted externally.)
OUT-OF-PHASE OPERATION
(FSEL_1 = VL)MAX5098A toc15
200ns/div
SOURCE2
10V/div
SOURCE1
10V/div
CKO
5V/div
SOFT-START FROM ON/OFFMAX5098A toc14
2ms/div
VOUT1 = 5V/2A
5V/div
ON/OFF
5V/div
GATE
10V/div
10V/div
VL = EN1 = EN2
5V/div
SOFT-START/SOFT-STOP FROM EN1MAX5098A toc13
1ms/div
VOUT1 = 5V/2A
5V/div
EN1
5V/div
PGOOD1
5V/div
fSW = 1.85MHz
CONVERTER 2
LOAD-TRANSIENT RESPONSEMAX5098A toc12
100s/div
VOUT2 = 3.3V
AC-COUPLED
200mV/div
IOUT2
500mA/div
CONVERTER 1
LOAD-TRANSIENT RESPONSEMAX5098A toc11
100s/div
VOUT1 = 5.0V
AC-COUPLED
200mV/div
IOUT1
1A/div
LINE-TRANSIENT RESPONSE
(BUCK CONVERTER)MAX5098A toc10
1ms/div
VIN
5V/div
VOUT1 = 5.0V/1.5A
AC-COUPLED
200mV/div
VOUT2 = 3.3V/0.75A
AC-COUPLED
200mV/div
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
(See the Typical Application Circuit, unless otherwise noted. V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means
that N1 is shorted externally.)
FB_ VOLTAGE
vs. TEMPERATUREMAX5098A toc21
FB_ VOLTAGE (V)
VL = V+ = VIN_HIGH = 5.5V
OVP BEHAVIORMAX5098A toc20
1ms/div
10V/div
GATE
10V/div
VOUT1
10V/div
PGOOD2
10V/div
VOUT2
10V/div
EXTERNAL OVERVOLTAGE REMOVED
FOUR-PHASE OPERATION
(FSEL_1 = VL )MAX5098A toc19
200ns/div
MASTER SOURCE120V/div
MASTER SOURCE220V/div
SLAVE SOURCE1
20V/div
SLAVE SOURCE220V/div
MASTERCKO
5V/div0V
EXTERNAL SYNCHRONIZATION
(FSEL_1 = SGND )MAX5098A toc18
200ns/div
SOURCE2
10V/div
SOURCE1
10V/div
CKO
5V/div
SYNC
5V/div
EXTERNAL SYNCHRONIZATION
(FSEL_1 = VL)MAX5098A toc17
200ns/div
SOURCE2
10V/div
SOURCE1
10V/div
CKO
5V/div
SYNC
5V/div
OUT-OF-PHASE OPERATION
(FSEL_1 = SGND)MAX5098A toc16
200ns/div
SOURCE2
10V/div
SOURCE1
10V/div
CKO
5V/div
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
(See the Typical Application Circuit, unless otherwise noted. V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means
that N1 is shorted externally.)
IN_HIGH STANDBY CURRENT
vs. TEMPERATUREMAX5098A toc28
IN_HIGH STANDBY CURRENT (A)
IN_HIGH = 8V
IN_HIGH = 14V
IN_HIGH = 16V
ON/OFF = IN_HIGH
EN1 = EN2 = SGND
IN_HIGH SHUTDOWN CURRENT
vs. TEMPERATUREMAX5098A toc27
IN_HIGH SHUTDOWN CURRENT (A)
IN_HIGH = 8V
IN_HIGH = 14V
IN_HIGH = 16V
ON/OFF = SGND
V+ STANDBY SUPPLY CURRENT
vs. TEMPERATUREMAX5098A toc26
TEMPERATURE (°C)
V+ STANDBY SUPPLY CURRENT (mA)
fSW = 1.85MHz
fSW = 300kHz
V+ = IN_HIGH = ON/OFF
EN1 = EN2 = SGND
V+ SWITCHING SUPPLY CURRENT
vs. SWITCHING FREQUENCYMAX5098A toc25
SWITCHING FREQUENCY (kHz)
V+ SWITCHING SUPPLY CURRENT (mA)
TA = +25°C
TA = +135°C
TA = +125°C
TA = +85°C
TA = -40°C
V+ = IN_HIGH = ON/OFF
SOURCE1, SOURCE1 INDICATOR CURRENT,
SOURCE2, SOURCE2 INDICATOR CURRENTMAX5098A toc24
1s/div
ISOURCE1
500mA/div
NO LOAD
SOURCE1
20V/div
NO LOAD
SOURCE2
20V/div
ISOURCE2
1A/div
BYPASS VOLTAGE
vs. BYPASS CURRENTMAX5098A toc23
BYPASS CURRENT (µA)
BYPASS VOLTAGE (V)602040
TA = +25°C
TA = +135°CTA = +125°CTA = +85°C
TA = -40°C
BYPASS VOLTAGE
vs. TEMPERATUREMAX5098A toc22
TEMPERATURE (C)
BYPASS VOLTAGE (V)
VL = V+ = VIN_HIGH = 5.5V
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
(See the Typical Application Circuit, unless otherwise noted. V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means
that N1 is shorted externally.)
SYSTEM LOAD-DUMPMAX5098A toc34
100ms/div
VOUT1
AC-COUPLED
100mV/div
10V/div
GATE
10V/div
IN_HIGH
10V/div0V
VIN
50V/div
SYSTEM TURN-OFF FROM BATTERYMAX5098A toc33
10ms/div
10V/div
10V/div
GATE
10V/div
IN_HIGH
10V/div
VIN
10V/div0V
SYSTEM TURN-ON FROM BATTERYMAX5098A toc32
10ms/div
10V/div
10V/div
GATE
10V/div
IN_HIGH
10V/div
VIN
10V/div
(VGATE - V) vs. VIN_HIGHMAX5098A toc31
VIN_HIGH (V)
(V
GATE
- V) (V)
TA = +25°C
TA = +135°C
TA = +125°C
TA = +85°C
TA = -40°C
ON/OFF = IN_HIGH
V+ TO IN_HIGH CLAMP VOLTAGE
vs. GATE SINK CURRENTMAX5098A toc30
GATE SINK CURRENT (mA)
V+ TO IN_HIGH CLAMP VOLTAGE (V)64210
TA = +25°C
TA = +135°C
TA = +125°C
TA = +85°C
TA = -40°C
IN_HIGH CLAMP VOLTAGE
vs. CLAMP CURRENTMAX5098A toc29
CLAMP CURRENT (mA)
IN_HIGH CLAMP VOLTAGE (V)302010
TA = +25°C
TA = +135°C
TA = +125°C
TA = +85°C
TA = -40°C
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
PINNAMEFUNCTION1, 32SOURCE2Converter 2 Internal MOSFET Source Connection. For buck converter operation, connect SOURCE2 to
the switched side of the inductor. For boost operation, connect SOURCE2 to PGND_ (Figure 6).
2, 3DRAIN2
Converter 2 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a high-
side switch and connect DRAIN2 to the DC-DC converters supply input rail. For boost converter operation,
use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 6).PGOOD2Converter 2 Open-Drain Power-Good Output. PGOOD2 goes low when converter 2’s output falls below 92.5% of its set regulation voltage. Use PGOOD2 and EN1 to sequence the converters. Converter 2 starts irst.EN2Converter 2 Active-High Enable Input. Connect to VL for always-on operation.FB2
Converter 2 Feedback Input. Connect FB2 to a resistive divider between converter 2’s output and SGND
to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-
divider from BYPASS to regulator 2’s output (Figure 3). See the Setting the Output Voltage section.COMP2Converter 2 Internal Transconductance Ampliier Output. See the Compensation section.OSC
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching
frequency (see the Setting the Switching Frequency section). Set ROSC for an oscillator frequency equal to
the SYNC input frequency when using external synchronization. ROSC is still required when an external
clock is connected to the SYNC input. See the Synchronization (SYNC)/Clock Output (CKO) section.SYNC
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is 1/2 of the frequency applied to
SYNC (FSEL_1 = VL). For FSEL_1 = SGND, the switching frequency of converter 1 becomes 1/4 of the
SYNC frequency. Connect SYNC to SGND when not used.GATE
Gate Drive Output. Connect to the gate of the external n-channel load-dump protection MOSFET. GATE =
IN_HIGH + 9V (typ) with IN_HIGH = 12V. GATE pulls to IN_HIGH by an internal n-channel MOSFET when
V+ raises 2V above IN_HIGH. Leave gate unconnected if the load-dump protection is not used (MOSFET not
installed).ON/OFF
n-Channel Switch Enable Input. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the
external n-channel load-dump protection MOSFET and reduce the supply current to 7µA (typ). When ON/
OFF is driven low, both DC-DC converters are disabled and the PGOOD_ outputs are driven low. Connect
to V+ if the external load-dump protection is not used (MOSFET not installed).IN_HIGH
Startup Input. IN_HIGH is protected by internally clamping to 21V (max). Connect a resistor (4kΩ max) from
IN_HIGH to the drain of the protection switch. Bypass IN_HIGH with a 4.7µF electrolytic or 1µF minimum
ceramic capacitor. Connect to V+ if the external load-dump protection is not used (MOSFET not installed).V+Input Supply Voltage. V+ can range from 5.2V to 19V. Connect V+, IN_HIGH, and VL together for 4.5V to
5.5V input operation. Bypass V+ to SGND with a 1µF minimum ceramic capacitor. VL
Internal Regulator Output. The VL regulator is used to supply the drive current at input VDRV. When driving VDRV, use an RC lowpass ilter to decouple switching noise from VDRV to the VL regulator (see the Typical
Application Circuit). Bypass VL to SGND with a 4.7µF minimum ceramic capacitor.SGNDSignal Ground. Connect SGND to exposed pad and to the board signal ground plane. Connect the board
signal ground and power ground planes together at a single point.
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Pin Description
PINNAMEFUNCTIONBYPASSReference Output Bypass Connection. Bypass to SGND with a 0.22µF or greater ceramic capacitor.FSEL_1
Converter 1 Frequency Select Input. Connect FSEL_1 to VL for normal operation. Connect FSEL_1 to
SGND to reduce converter 1’s switching frequency to 1/2 of converter 2’s switching frequency (Converter 1
switching frequency is 1/4 the CKO frequency). Do not leave FSEL_1 unconnected. COMP1Converter 1 Internal Transconductance Ampliier Output. See the Compensation section.FB1
Converter 1 Feedback Input. Connect FB1 to a resistive divider between converter 1’s output and SGND
to adjust the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltage-
divider from BYPASS to regulator 1’s output (Figure 3). See the Setting the Output Voltage section. EN1Converter 1 Active-High Enable Input. Connect to VL for an always-on operation.PGOOD1
Converter 1 Open-Drain Power-Good Output. PGOOD1 output goes low when converter 1’s output falls
below 92.5% of its set regulation voltage. Use PGOOD1 and EN2 to sequence the converters. Converter 1 starts irst.
22, 23DRAIN1
Converter 1 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a high-
side switch and connect DRAIN1 to the DC-DC converters supply input rail. For boost converter operation,
use the MOSFET as a low-side switch and connect DRAIN1 to the inductor and diode junction (Figure 6).
24, 25SOURCE1Converter 1 Internal MOSFET Source Connection. For buck operation, connect SOURCE1 to the switched
side of the inductor. For boost operation, connect SOURCE1 to PGND_ (Figure 6).BST1/VDD1
Converter 1 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST1/VDD1 to
a 0.1µF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter
Operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1µF ceramic capacitor
to PGND_ (Figure 6).VDRV
Low-Side Driver Supply Input. Connect VDRV to VL through an RC ilter to bypass switching noise to the
internal VL regulator. For buck converter operation, connect anode terminals of external bootstrap diodes
to VDRV. For boost converter operation, connect VDRV to BST1/VDD1 and BST2/VDD2. Bypass with a
minimum 2.2µF ceramic capacitor to PGND_ (see the Typical Application Circuit). Do not connect to an
external supply.CKO
Clock Output. CKO is an output with twice the frequency of each converter (FSEL_1 = VL) and 90° out-of-
phase with respect to converter 1. Connect CKO to the SYNC input of another MAX5098A for a four-
phase converter.
29, 30PGND1,
PGND2Power Ground. Connect both PGND1 and PGND2 together and to the board power ground plane.BST2/VDD2
Converter 2 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST2/VDD2 to
a 0.1µF ceramic capacitor and diode according to the Typical Application Circuit. For boost converter
operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1µF ceramic
capacitor from BST2/VDD2 to PGND_ (Figure 6).EPExposed Pad. Connect EP to SGND. For enhanced thermal dissipation, connect EP to a copper area
as large as possible. Do not use EP as the sole ground connection.
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Pin Description (continued)
CONVERTER 1
COMP1
PGOOD1
SOURCE1
DRAIN1
BYPASS
FSEL_1
EN1
SYNC
OSC
VDRV
CKO
EN2
DRAIN2
PGOOD2
CONVERTER 2
CKO2
LDOS
0.2V0.74V
0.8V
TRANSCONDUCTANCE
ERROR AMPLIFIER
fSW/4
FREQUENCY
CONTROL
PWM
COMPARATOR
CKO1
MAXIMUM DUTY-CYCLE
CONTROL
FB1
BST1/VDD1
IN_HIGH
ON/OFF
0.9V
PGND_
CURRENT
LIMIT
OSCILLATOR
MAIN
OSCILLATOR
GATE
OVERVOLTAGE
OVERVOLTAGE
STARTUP CIRCUIT/
PROTECTION CIRCUIT/
CHARGE PUMP
20V SHUNT
REGULATOR
1.8V
SGND
BST2/VDD2
SOURCE2
FB2
PGND_
COMP2
CHARGE
PUMP
DIGITAL
SOFT-START
FREQUENCY
DIVIDER
MAX5098A
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Functional Diagram
Detailed Description
PWM ControllerThe MAX5098A dual DC-DC converter uses a
pulse-width-modulation (PWM) voltage-mode control
scheme. On each converter the device includes one inte-
grated n-channel MOSFET switch and requires an external
low-forward-drop Schottky diode for output rectification.
The controller generates the clock signal by dividing down
the internal oscillator (fCKO) or the SYNC input when
driven by an external clock, therefore each controller’s
switching frequency equals half the oscillator frequency
(fSW = fCKO/2) or half of the SYNC input frequency (fSW
= fSYNC/2). An internal transconductance error amplifier
produces an integrated error voltage at COMP_, providing
high DC accuracy. The voltage at COMP_ sets the duty
cycle using a PWM comparator and a ramp generator.
At each rising edge of the clock, converter 1’s MOSFET
switch turns on and remains on until either the appropriate
or maximum duty cycle is reached, or the maximum current
limit for the switch is reached. Converter 2 operates 180°
out-of-phase, so its MOSFET switch turns on at each fall-
ing edge of the clock.
In the case of buck operation (see the Typical Application
Circuit), the internal MOSFET is used in high-side config-
uration. During each MOSFET’s on-time, the associated
inductor current ramps up. During the second half of the
switching cycle, the high-side MOSFET turns off and forward
biases the Schottky rectifier. During this time, the SOURCE_
voltage is clamped to a diode drop (VD) below ground. A
low forward voltage drop (0.4V) Schottky diode must be
used to ensure the SOURCE_ voltage does not go below
-0.6V abs max. The inductor releases the stored energy
as its current ramps down, and provides current to the
output. The bootstrap capacitor is also recharged when the
SOURCE_ voltage goes low during the high-side MOSFET
off-time. The maximum duty-cycle limit ensures proper
bootstrap charging at startup or low input voltages. The
circuit goes in discontinuous conduction mode operation at
light load, when the inductor current completely discharges
before the next cycle commences. Under overload condi-
tions, when the inductor current exceeds the peak current
limit of the respective switch, the high-side MOSFET turns
off quickly and waits until the next clock cycle.
In the case of boost operation, the MOSFET is a low-
side switch (Figure 6). During each on-time, the induc-
tor current ramps up. During the second half of the
switching cycle, the low-side switch turns off and for-
ward biases the Schottky diode. During this time, the
DRAIN_ voltage is clamped to a diode drop (VD) above
VOUT_ and the inductor provides energy to the output
as well as replenishes the output capacitor charge.
ON/OFFThe MAX5098A provides an input (ON/OFF) to turn on and
off the external load-dump protection MOSFET. Drive ON/
OFF high for normal operation. Drive ON/OFF low to turn
off the external n-channel load-dump protection MOSFET
and reduce the supply current to 7µA (typ). When ON/OFF
is driven low, the converter also turns off, and the PGOOD_
outputs are driven low. V+ will be self discharged through
the converters output currents and the IC supply current.
Internal Oscillator/Out-of-Phase OperationThe internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The switching
frequency of each converter (fSW) is programmable from
200kHz to 2.2MHz using a single 1% resistor at ROSC. See
the Setting the Switching Frequency section.
With dual synchronized out-of-phase operation, the
MAX5098A’s internal MOSFETs turn on 180° out-of-phase.
The instantaneous input current peaks of both regulators
do not overlap, resulting in reduced RMS ripple current and
input-voltage ripple. This reduces the required input capac-
itor ripple current rating, allows for fewer or less expensive
capacitors, and reduces shielding requirements for EMI.
Synchronization (SYNC)/
Clock Output (CKO)The main oscillator can be synchronized to the system
clock by applying an external clock (fSYNC) at SYNC. The
fSYNC frequency must be twice the required operating
frequency of an individual converter. Use a TTL logic sig-
nal for the external clock with at least 100ns pulse width.
ROSC is still required when using external synchronization.
Program the internal oscillator frequency to have fSW = 1/2
fSYNC. The device is properly synchronized if the SYNC
frequency, fSYNC, varies within ±20%.
Two MAX5098As can be connected in the master-slave
configuration for four ripple-phase operation (Figure 1).
The MAX5098A provides a clock output (CKO) that is 45°
phase-shifted with respect to the internal switch turn-on
edge. Feed the CKO of the master to the SYNC input of the
slave. The effective input ripple switching frequency is four
times the individual converter’s switching frequency. When
driving the master converter using an external clock at
SYNC, set the fSYNC clock duty cycle to 50% for effective
90° phase-shifted interleaved operation. When a SYNC is
applied (and FSEL_1 = 0), converter 1 duty cycle is limited
to 75% (max).
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
Input Voltage (V+)/
Internal Linear Regulator (VL)All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (VL). At higher input
voltages (V+) of 5.2V to 19V, VL is regulated to 5.2V. At
5.2V or below, the internal linear regulator operates in
dropout mode, where VL follows V+. Depending on the
load on VL, the dropout voltage can be high enough to
reduce VL below the undervoltage lockout (UVLO) thresh-
old. Do not use VL to power external circuitry.
For input voltages less than 5.5V, connect V+ and VL
together. The load on VL is proportional to the switching
frequency of converter 1 and converter 2. See the VL
Output Voltage vs. Converter Switching Frequency graph
in the Typical Operating Characteristics. For input voltage
ranges higher than 5.5V, disconnect VL from V+.
Bypass V+ to SGND with a 1µF or greater ceramic capac-
itor placed close to the MAX5098A. Bypass VL with a
4.7µF ceramic capacitor to SGND.
Undervoltage Lockout/
Soft-Start/Soft-StopThe MAX5098A includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for converter turn-
on and monotonic rise of the output voltage. The falling
UVLO threshold is internally set to 4.1V (typ) with 180mV
hysteresis. Hysteresis at UVLO eliminates “chattering”
during startup. When VL drops below UVLO, the internal
MOSFET switches are turned off.
The MAX5098A digital soft-start reduces input inrush
currents and glitches at the input during turn-on. When
UVLO is cleared and EN_ is high, digital soft-start slowly
ramps up the internal reference voltage in 64 steps. The
total soft-start period is 4096 internal oscillator switching
cycles.
Driving EN_ low initiates digital soft-stop that slowly
ramps down the internal reference voltage in 64 steps.
The total soft-stop period is equal to the soft-start period.
To calculate the soft-start/soft-stop period, use the follow-
ing equation:CKO
4096t(ms)f(kHz)=
where fCKO is the internal oscillator and fCKO is twice
each converters’ switching frequency (FSEL_1 = VL).
Enable (EN1, EN2)The MAX5098A dual converter provides separate
enable inputs, EN1 and EN2, to individually control
or sequence the output voltages. These active-high
enable inputs are TTL compatible. Driving EN_ high
initiates soft-start of the converter, and PGOOD_ goes
logic-high when the converter output voltage reaches the
VTPGOOD_ threshold. Driving EN_ low initiates a soft-
stop of the converter, and immediately forces PGOOD_
low. Use EN1, EN2, and PGOOD1 for sequencing (see
Figure 2). Connect PGOOD1 to EN2 to make sure con-
verter 1’s output is within regulation before converter 2
starts. Add an RC network from VL to EN1 and EN2 to
delay the individual converter. Sequencing reduces input
inrush current and possible chattering. Connect EN_ to
VL for always-on operation.
PGOOD_Converter 1 and converter 2 include a power-good flag,
PGOOD1 and PGOOD2, respectively. Since PGOOD_ is
an open-drain output and can sink 3mA while providing
the TTL logic-low signal, pull PGOOD_ to a logic voltage
to provide a logic-level output. PGOOD1 goes low when
converter 1’s feedback FB1 drops to 92.5% (VTPGOOD_)
of its nominal set point. The same is true for converter 2.
Connect PGOOD_ to SGND or leave unconnected if not
used.
Current LimitThe internal MOSFET switch current of each converter is
monitored during its on-time. When the peak switch cur-
rent crosses the current-limit threshold of 3.45A (typ) and
2.1A (typ) for converter 1 and converter 2, respectively,
the on-cycle is terminated immediately and the inductor
is allowed to discharge. The MOSFET is turned on at the
next clock pulse, initiating a new switching cycle.
In deep overload or short-circuit conditions when the
VFB_ voltage drops below 0.2V, the switching frequency
is reduced to 1/4 x fSW to provide sufficient time for the
inductor to discharge. During overload conditions, if the
voltage across the inductor is not high enough to allow
for the inductor current to properly discharge, current run-
away may occur. Current runaway can destroy the device
in spite of internal thermal-overload protection. Reducing
the switching frequency during overload conditions allows
more time for inductor discharge and prevents current
runaway.
MAX5098ADual 2.2MHz Buck or Boost Converter
with 80V Load-Dump Protection
