IC Phoenix
 
Home ›  MM61 > MAX5062AASA+T-MAX5063AASA+T,125V/2A, High-Speed, Half-Bridge MOSFET Drivers
MAX5062AASA+T-MAX5063AASA+T Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
MAX5062AASA+T |MAX5062AASATMAXIMN/a12489avai125V/2A, High-Speed, Half-Bridge MOSFET Drivers
MAX5063AASA+T |MAX5063AASATMAXIMN/a4054avai125V/2A, High-Speed, Half-Bridge MOSFET Drivers


MAX5062AASA+T ,125V/2A, High-Speed, Half-Bridge MOSFET DriversELECTRICAL CHARACTERISTICS(V = V = +8V to +12.6V, V = GND = 0V, BBM = open, T = -40°C to +125°C, un ..
MAX5062BASA ,125V/2A, high-speed, half-bridge MOSFET driverapplications.♦ Up to 125V Input OperationThese drivers are independently controlled and their♦ 8V t ..
MAX5063AASA ,125V/2A, high-speed, half-bridge MOSFET driverMAX5062/MAX5063/MAX506419-3502; Rev 0; 11/04125V/2A, High-Speed, Half-Bridge MOSFET Drivers
MAX5063AASA+T ,125V/2A, High-Speed, Half-Bridge MOSFET DriversFeatures♦ HIP2100/HIP2101 Pin Compatible (MAX5062A/The MAX5062/MAX5063/MAX5064 high-frequency,125V ..
MAX5063BASA ,125V/2A, high-speed, half-bridge MOSFET driverELECTRICAL CHARACTERISTICS(V = V = +8V to +13.2V, V = GND = 0V, BBM = open, T = -40°C to +125°C, un ..
MAX5066EUI ,Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current ApplicationsFeaturesThe MAX5066 is a two-phase, configurable single- or ♦ 4.75V to 5.5V or 5V to 28V Inputdual- ..
MAX9323EUP+ ,One-to-Four LVCMOS-to-LVPECL Output Clock and Data DriverELECTRICAL CHARACTERISTICS(V = 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (V - 2V), CLK_SEL = ..
MAX9324EUP , One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
MAX9324EUP+ ,One-to-Five LVPECL/LVCMOS Output Clock and Data DriverApplications*Future product—Contact factory for availability.**EP = Exposed paddle.Precision Clock ..
MAX9325EQI ,+2.375 V to +3.8 V, 2:8 differential LVPECL/LVECL/HSTL clock and data driverApplicationsFunctional Diagram appears at end of data sheet.Precision Clock DistributionLow-Jitter ..
MAX932CPA ,Ultra Low-Power, Low-Cost Comparators with 2eferenceGeneral Description ________
MAX932CSA ,Ultra Low-Power, Low-Cost Comparators with 2eferenceELECTRICAL CHARACTERISTICS—5V Operation (continued)(V+ = 5V, V- = GND = 0V, T = T to T , unless oth ..


MAX5062AASA+T-MAX5063AASA+T
125V/2A, High-Speed, Half-Bridge MOSFET Drivers
General Description
The MAX5062/MAX5063/MAX5064 high-frequency,
125V half-bridge, n-channel MOSFET drivers drive high-
and low-side MOSFETs in high-voltage applications.
These drivers are independently controlled and their
35ns typical propagation delay, from input to output, are
matched to within 3ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities in a
thermally enhanced package make these devices suit-
able for the high-power, high-frequency telecom power
converters. The 125V maximum input voltage range pro-
vides plenty of margin over the 100V input transient
requirement of telecom standards. A reliable on-chip
bootstrap diode connected between VDDand BST elimi-
nates the need for an external discrete diode.
The MAX5062A/C and the MAX5063A/C offer both nonin-
verting drivers (see the Selector Guide). The
MAX5062B/D and the MAX5063B/D offer a noninverting
high-side driver and an inverting low-side driver. The
MAX5064A/B offer two inputs per driver that can be
either inverting or noninverting. The MAX5062A/B/C/D
and the MAX5064A feature CMOS (VDD / 2) logic inputs.
The MAX5063A/B/C/D and the MAX5064B feature TTL
logic inputs. The MAX5064A/B include a break-before-
make adjustment input that sets the dead time between
drivers from 16ns to 95ns. The drivers are available in the
industry-standard 8-pin SO footprint and pin configura-
tion, and a thermally enhanced 8-pin SO and 12-pin
(4mm x 4mm) thin QFN packages. All devices operate
over the -40°C to +125°C automotive temperature range.
Applications

Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
Active-Clamp Forward Converters
Power-Supply Modules
Motor Control
Features
HIP2100/HIP2101 Pin Compatible (MAX5062A/
MAX5063A)
Up to 125V Input Operation8V to 12.6V VDDInput Voltage Range2A Peak Source and Sink Current Drive Capability35ns Typical Propagation DelayGuaranteed 8ns Propagation Delay Matching
Between Drivers
Programmable Break-Before-Make Timing
(MAX5064)
Up to 1MHz Combined Switching Frequency while
Driving 100nC Gate Charge (MAX5064)
Available in CMOS (VDD / 2) or TTL Logic-Level
Inputs with Hysteresis
Up to 15V Logic Inputs Independent of Input
Voltage
Low 2.5pF Input CapacitanceInstant Turn-Off of Drivers During Fault or PWM
Start-Stop Synchronization (MAX5064)
Low 200μA Supply CurrentVersions Available With Combination of
Noninverting and Inverting Drivers (MAX5062B/D
and MAX5063B/D)
Available in 8-Pin SO, Thermally Enhanced SO,
and 12-Pin Thin QFN Packages
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARK
PKG
CODE
MAX5062AASA
-40°C to +125°C8 SO—S8-5
MAX5062BASA-40°C to +125°C8 SO—S8-5
MAX5062CASA-40°C to +125°C8 SO-EP*—S8E-14
MAX5062DASA-40°C to +125°C8 SO-EP*—S8E-14
Ordering Information
PARTHIGH-SIDE DRIVERLOW-SIDE DRIVERLOGIC LEVELSPIN COMPATIBLE

MAX5062AASANoninvertingNoninvertingCMOS (VDD / 2)HIP 2100IB
MAX5062BASANoninvertingInvertingCMOS (VDD / 2)—
MAX5062CASANoninvertingNoninvertingCMOS (VDD / 2)—
MAX5062DASANoninvertingInvertingCMOS (VDD / 2)—
Selector Guide

19-3502; Rev 5; 5/07
Selector Guide continued at end of data sheet.

*EP = Exposed paddle.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Ordering Information continued at end of data sheet.
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= VBST= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
VDD= VBST= +12V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
VDD, IN_H, IN_L, IN_L+, IN_L-, IN_H+, IN_H-........-0.3V to +15V
DL, BBM.....................................................-0.3V to (VDD+ 0.3V)
HS............................................................................-5V to +130V
DH to HS.....................................................-0.3V to (VDD+ 0.3V)
BST to HS...............................................................-0.3V to +15V
AGND to PGND (MAX5064)..................................-0.3V to +0.3V
dV/dt at HS........................................................................50V/ns
Continuous Power Dissipation (TA= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW
8-Pin SO with Exposed Pad (derate 19.2mW/°C
above +70°C)*....................................................1538.5mW
12-Pin Thin QFN (derate 24.4mW/°C
above +70°C)*....................................................1951.2mW
Maximum Junction Temperature.....................................+150°C
Operating Temperature Range.........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
*Per JEDEC 51 standard multilayer board.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIES

Operating Supply VoltageVDD(Note 2)8.012.6V
MAX5062_/
MAX5063_70140
VDD Quiescent Supply CurrentIDDIN_H = IN_L = GND
(no switching)MAX5064_120260
VDD Operating Supply CurrentIDDOfSW = 500kHz, VDD = +12V3mA
BST Quiescent Supply CurrentIBSTIN_H = IN_L = GND (no switching)1540µA
BST Operating Supply CurrentIBSTOfSW = 500kHz, VDD = VBST = +12V3mA
UVLO (VDD to GND)UVLOVDDVDD rising6.57.38.0V
UVLO (BST to HS)UVLOBSTBST rising6.06.97.8V
UVLO Hysteresis0.5V
LOGIC INPUT

MAX5062_/MAX5064A,
CMOS (VDD / 2) version
0.67 x
VDD
0.55 x
VDDInput-Logic HighVIH_
MAX5063_/MAX5064B, TTL version21.65
MAX5062_/MAX5064A,
CMOS (VDD / 2) version
0.4 x
VDD
0.33 x
VDDInput-Logic LowVIL_
MAX5063_/MAX5064B, TTL version1.40.8
MAX5062_/MAX5064A,
CMOS (VDD / 2) version1.6Logic-Input HysteresisVHYS
MAX5063_/MAX5064B, TTL version0.25
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)

(VDD= VBST= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
VDD= VBST= +12V and TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

VIN_H+, VIN_L+ = 0V
VIN_L = VDD for MAX5062B/D, MAX5063B/D
VIN_H-, VIN_L-, VIN_H = VDDLogic-Input CurrentI_IN
VIN_L = 0V for MAX5062A/C, MAX5063A/C0.001+1µA
IN_H+, IN_L+ IN_H, to GND
IN_L to VDD for MAX5062B/D,
MAX5063B/D
IN_H-, IN_L-, IN_H, to VDD
Input ResistanceRIN
IN_L for MAX5062A/C, MAX5063A/C to GND
1MΩ
Input CapacitanceCIN2.5pF
HIGH-SIDE GATE DRIVER

HS Maximum VoltageVHS_MAX125V
BST Maximum VoltageVBST_MAX140V
TA = +25°C2.53.3Driver Output Resistance
(Sourcing)RON_HPVDD = 12V, IDH = 100mA
(sourcing)TA = +125°C3.54.6Ω
TA = +25°C2.12.8Driver Output Resistance
(Sinking)RON_HNVDD = 12V, IDH = 100mA
(sinking)TA = +125°C3.24.2Ω
DH Reverse Current (Latchup
Protection)(Note 3)400mA
Power-Off Pulldown Clamp
VoltageVBST = 0V or floating, IDH = 1mA (sinking)0.941.16V
Peak Output Current (Sourcing)CL = 10nF, VDH = 0V2A
Peak Output Current (Sinking)IDH_PEAKCL = 10nF, VDH = 12V2A
LOW-SIDE GATE DRIVER

TA = +25°C2.53.3Driver Output Resistance
(Sourcing)RON_LPVDD = 12V, IDL = 100mA
(sourcing)TA = +125°C3.54.6Ω
TA = +25°C2.12.8Driver Output Resistance
(Sinking)RON_LNVDD = 12V, IDL = 100mA
(sinking)TA = +125°C3.24.2Ω
Reverse Current at DL (Latchup
Protection)(Note 3)400mA
Power-Off Pulldown Clamp
VoltageVDD = 0V or floating, IDL = 1mA (sinking)0.951.16V
Peak Output Current (Sourcing)IPK_LPCL = 10nF, VDL = 0V2A
Peak Output Current (Sinking)IPK_LNCL = 10nF, VDL = 12V2A
INTERNAL BOOTSTRAP DIODE

Forward Voltage DropVfIBST = 100mA0.911.11V
Turn-On and Turn-Off TimetRIBST = 100mA40ns
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Note 1:
All devices are 100% tested at TA= +125°C. Limits over temperature are guaranteed by design.
Note 2:
Ensure that the VDD-to-GND or BST-to-HS voltage does not exceed 13.2V.
Note 3:
Guaranteed by design, not production tested.
Note 4:
Break-before-make time is calculated by tBBM= 8ns x (1 + RBBM / 10kΩ).
Note 5:
See the Minimum Pulse Widthsection.
ELECTRICAL CHARACTERISTICS (continued)

(VDD= VBST= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
VDD= VBST= +12V and TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (VDD = VBST = +12V)

CL = 1000pF7
CL = 5000pF33Rise TimetR
CL = 10,000pF65
CL = 1000pF7
CL = 5000pF33Fall TimetF
CL = 10,000pF65
CMOS3055Turn-On Propagation Delay TimetD_ONFigure 1, CL = 1000pF
(Note 3)TTL3563ns
CMOS3055Turn-Off Propagation Delay TimetD_OFFFigure 1, CL = 1000pF
(Note 3)TTL3563ns
Delay Matching Between
Inverting Input to Output and
Noninverting Input to Output
tMATCH1CL = 1000pF, BBM open for MAX5064,
Figure 1 (Note 3)28ns
Delay Matching Between Driver-
Low and Driver-HightMATCH2CL = 1000pF, BBM open for MAX5064,
Figure 1 (Note 3)28ns
RBBM = 10kΩ16
RBBM = 47kΩ (Notes 3, 4)405672Break-Before-Make Accuracy
(MAX5064 Only)
RBBM = 100kΩ95
Internal Nonoverlap1ns
VDD = VBST = 12V135Minimum Pulse-Width Input Logic
(High or Low) (Note 5)tPW-MINVDD = VBST = 8V170ns
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
UNDERVOLTAGE LOCKOUT
(VDD AND VBST RISING) vs. TEMPERATURE

MAX5062/3/4 toc01
TEMPERATURE (°C)
UVLO (V)
UVLOVDD
UVLOBST
VDD AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE

MAX5062/3/4 toc02
TEMPERATURE (°C)
UVLO HYSTERESIS (V)
UVLOBST
HYSTERESIS
UVLOVDD
HYSTERESIS
IDD vs. VDD

MAX5062/3/4 toc03
40µs/div
VDD2V/div
500µA/div
IDD
MAX5064
IN_L-, IN_H- = VDD
IN_L+, IN_H+ = GND
IDDO + IBSTO vs. VDD
(fSW = 250kHz)

MAX5062/3/4 toc04
VDD (V)
IDDO
IBSTO
(mA)1011345678912
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
MAX5062/3/4 toc05
VDD - VBST (V)
IDIODE
(mA)
TA = +125°C
TA = +25°C
TA = 0°C
TA = -40°C
VDD QUIESCENT CURRENT
vs. VDD (NO SWITCHING)
MAX5062/3/4 toc06
VDD (V)
IDD
TA = -40°C
TA = +125°C
MAX5064
TA = +25°C, TA = 0°C26810153791112131415
BST QUIESCENT CURRENT
vs. BST VOLTAGE

MAX5062/3/4 toc07
VBST (V)
IBST
VBST = VDD + 1V,
NO SWITCHING
TA = +125°C
TA = -40°C, TA = 0°C, TA = +25°C
Typical Operating Characteristics

(Typical values are at VDD= VBST= +12V and TA= +25°C, unless otherwise specified.)
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
VDD AND BST OPERATING SUPPLY
CURRENT vs. FREQUENCY

MAX5062/3/4 toc08
FREQUENCY (kHz)
DDO
+ I
BSTO
(mA)
CL = 0
DH OR DL OUTPUT LOW VOLTAGE
vs. TEMPERATURE

MAX5062/3/4 toc09
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
SINKING 100mA
DH OR DL FALL TIME
vs. TEMPERATURE (CLOAD = 10nF)

MAX5062/3/4 toc12
TEMPERATURE (°C)
tF (ns)
VDD = VBST = 8V
VDD = VBST = 12V
DH OR DL RISE PROPAGATION DELAY
vs. TEMPERATURE

MAX5062/3/4 toc13
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
PEAK DH AND DL
SOURCE/SINK CURRENT
MAX5062/3/4 toc10
1µs/div
DH OR DL5V/div
SINK AND SOURCE
CURRENT2A/div
CL = 100nF
DH OR DL RISE TIME
vs. TEMPERATURE (CL = 10nF)

MAX5062/3/4 toc11
TEMPERATURE (°C)
(ns)
VDD = VBST = 8V
VDD = VBST = 12V
Typical Operating Characteristics (continued)

(Typical values are at VDD= VBST= +12V and TA= +25°C, unless otherwise specified.)
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
DH OR DL FALL PROPAGATION DELAY
vs. TEMPERATURE

MAX5062/3/4 toc14
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
BREAK-BEFORE-MAKE
DEAD TIME vs. RBBM
MAX5062/3/4 toc15
RBBM (kΩ)
tBBM
(ns)
MAX5064
BREAK-BEFORE-MAKE DEAD TIME
vs. TEMPERATURE

MAX5062/3/4 toc16
TEMPERATURE (°C)
tBBM
(ns)
RBBM = 100kΩ
RBBM = 10kΩ
MAX5064
DELAY MATCHING (DH/DL RISING)

MAX5062/3/4 toc17
10ns/div
INPUT5V/div
5V/divDH/DL
CL = 0
DELAY MATCHING (DH/DL FALLING)

MAX5062/3/4 toc18
10ns/div
INPUT5V/div
5V/divDH/DL
CL = 0
DH/DL RESPONSE TO VDD GLITCH

MAX5062/3/4 toc19
40µs/div
VDD
10V/div
10V/div
10V/div
5V/divINPUTypical Operating Characteristics (continued)
(Typical values are at VDD= VBST= +12V and TA= +25°C, unless otherwise specified.)
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
PINNAMEFUNCTION
BSTBoost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.DHHigh-Side-Gate Driver Output. Drives high-side MOSFET gate.HSSource Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.AGNDAnalog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced toBBM
Break-Before-Make Programming Resistor Connection. Connect a 10kΩ to 100kΩ resistor from BBM
to AGND to program the break-before-make time (tBBM) from 16ns to 95ns. Resistance values
greater than 200kΩ disables the BBM function and makes tBBM = 1ns. Bypass this pin with at least a
1nF capacitor to AGND.IN_H-High-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
AGND when not used.IN_H+High-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
VDD when not used.IN_L-Low-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND
when not used.IN_L+Low-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
VDD when not used.PGNDPower Ground. Return path for high-switching current signals. Use PGND as a return path for the
low-side driver.DLLow-Side-Gate Driver Output. Drives the low-side MOSFET gate.VDDPower Input. Bypass to PGND with a 0.1µF ceramic in parallel with a 1µF ceramic capacitor.
—EPExposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in
heat dissipation.
MAX5064 Pin Description
PINNAMEFUNCTION

1VDDPower Input. Bypass to GND with a parallel combination of 0.1µF and 1µF ceramic capacitor.BSTBoost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.DHHigh-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.HSSource Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.IN_HHigh-Side Noninverting Logic InputIN_LLow-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input
(MAX5062B/D, MAX5063B/D).GNDGround. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.DLLow-Side-Gate Driver Output. Drives low-side MOSFET gate.
—EPExposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).
MAX5062/MAX5063 Pin Description
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Detailed Description

The MAX5062/MAX5063/MAX5064 are 125V/2A high-
speed, half-bridge MOSFET drivers that operate from a
supply voltage of +8V to +12.6V. The drivers are
intended to drive a high-side switch without any isola-
tion device like an optocoupler or drive transformer.
The high-side driver is controlled by a TTL/CMOS logic
signal referenced to ground. The 2A source and sink
drive capability is achieved by using low RDS_ONp-
and n-channel driver output stages. The BiCMOS
process allows extremely fast rise/fall times and low
propagation delays. The typical propagation delay from
the logic-input signal to the drive output is 35ns with a
matched propagation delay of 3ns typical. Matching
these propagation delays is as important as the
absolute value of the delay itself. The high 125V input
voltage range allows plenty of margin above the 100V
transient specification per telecom standards.
The MAX5064 is available in a thermally enhanced
TQFN package, which can dissipate up to 1.95W (at
+70°C) and allow up to 1MHz switching frequency
while driving 100nC combined gate-charge MOSFETs.
Figure1. Timing Characteristics for Noninverting and Inverting Logic Inputs
VIH
VIL
90%
10%
VIH
VIL
IN_H+
IN_H-
tD_ON3
tD_ON4tD_OFF4
tD_OFF3
VIH
VIL
90%
10%
VIH
VIL
IN_L+
IN_L-
tD_ON1
tD_ON2tD_OFF2
tD_OFF1
tMATCH1 = (tD_ON2 - tD_ON1) or (tD_OFF2 - tD_OFF1)
tMATCH2 = (tD_ON3 - tD_ON1) or (tD_ON4 - tD_ON2) or (tD_OFF3 - tD_OFF1) or (tD_OFF4 - tD_OFF2)
MAX5062/MAX5063/MAX5064
Undervoltage Lockout

Both the high- and low-side drivers feature undervolt-
age lockout (UVLO). The low-side driver’s UVLOLOW
threshold is referenced to GND and pulls both driver
outputs low when VDDfalls below 6.8V. The high-side
driver has its own undervoltage lockout threshold
(UVLOHIGH), referenced to HS, and pulls DH low when
BST falls below 6.4V with respect to HS.
During turn-on, once VDDrises above its UVLO thresh-
old, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
the BST-to-HS voltage is below UVLOBST. For synchro-
nous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and
normal operation begins in a few microseconds after the
BST-to-HS voltage exceeds UVLOBST. In the two-switch
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
voltage above UVLOBST.
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected care-
fully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capaci-
tance of the MOSFET. Use a low-ESR-type X7R dielec-
tric ceramic capacitor at BST (typically a 0.1µF ceramic
is adequate) and a parallel combination of 1µF and
0.1µF ceramic capacitors from VDDto GND
(MAX5062_, MAX5063_) or to PGND (MAX5064_). The
high-side MOSFET’s continuous on-time is limited due
to the charge loss from the high-side driver’s quiescent
current. The maximum on-time is dependent on the size
of CBST, IBST(50µA max), and UVLOBST.
Output Driver

The MAX5062/MAX5063/MAX5064 have low 2.5Ω
RDS_ONp-channel and n-channel devices (totem pole)
in the output stage. This allows for a fast turn-on and
turn-off of the high gate-charge switching MOSFETs.
The peak source and sink current is typically 2A.
Propagation delays from the logic inputs to the driver
outputs are matched to within 8ns. The internal p- and
n-channel MOSFETs have a 1ns break-before-make
logic to avoid any cross conduction between them. This
internal break-before-make logic eliminates shoot-
through currents reducing the operating supply current
as well as the spikes at VDD. The DL voltage is approxi-
mately equal to VDDand the DH-to-HS voltage, a diode
drop below VDD, when they are in a high state and to
zero when in a low state. The driver RDS_ONis lower at
higher VDD. Lower RDS_ONmeans higher source and
sink currents and faster switching speeds.
Internal Bootstrap Diode

An internal diode connects from VDDto BST and is
used in conjunction with a bootstrap capacitor external-
ly connected between BST and HS. The diode charges
the capacitor from VDDwhen the DL low-side switch is
on and isolates VDDwhen HS is pulled high as the high-
side driver turns on (see the Typical Operating Circuit).
The internal bootstrap diode has a typical forward volt-
age drop of 0.9V and has a 10ns typical turn-off/turn-on
time. For lower voltage drops from VDDto BST, connect
an external Schottky diode between VDDand BST.
Programmable Break-Before-Make
(MAX5064)

Half-bridge and synchronous buck topologies require
that the high- or low-side switch be turned off before
the other switch is turned on to avoid shoot-through
currents. Shoot-through occurs when both high- and
low-side switches are on at the same time. This condi-
tion is caused by the mismatch in the propagation
delay from IN_H/IN_L to DH/DL, driver output imped-
ance, and the MOSFET gate capacitance. Shoot-
through currents increase power dissipation, radiate
EMI, and can be catastrophic, especially with high
input voltages.
The MAX5064 offers a break-before-make (BBM) fea-
ture that allows the adjustment of the delay from the
input to the output of each driver. The propagation
delay from the rising edges of IN_H and IN_L to the ris-
ing edges of DH and DL, respectively, can be pro-
grammed from 16ns to 95ns. Note that the BBM time
(tBBM) has a higher percentage error at lower value
because of the fixed comparator delay in the BBM
block. The propagation delay mismatch (tMATCH_)
needs to be included when calculating the total tBBM
error. The low 8ns (maximum) delay mismatch reduces
the total tBBMvariation. Use the following equations to
calculate RBBMfor the required BBM time and
tBBM_ERROR:
where tBBMis in nanoseconds.
The voltage at BBM is regulated to 1.3V. The BBM circuit
adjusts tBBMdepending on the current drawn by RBBM.
Bypass BBM to AGND with a 1nF or smaller ceramic
capacitor (CBBM) to avoid any effect of ground bounce
caused during switching. The charging time of CBBM
does not affect tBBMat turn-on because the BBM voltage
is stabilized before the UVLO clears the device turn-on.tforRkt
BBMBBMBBM
BBMERRORBBMMATCH . __⎛⎜⎞⎟<+1081200
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED