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MAX3991UTGMAXIMN/a8avai10 Gbps clock and data recovery with limiting amplifier


MAX3991UTG ,10 Gbps clock and data recovery with limiting amplifierApplications Pin Configuration9.95Gbps to 11.1Gbps Optical XFP ModulesTOP VIEWSONET OC-192/SDH STM- ..
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MAX3991UTG
10 Gbps clock and data recovery with limiting amplifier
General Description
The MAX3991 is a 10Gbps clock and data recovery
(CDR) with limiting amplifier IC for XFP optical receivers.
The MAX3991 and the MAX3992 (CDR with equalizer)
form a signal conditioner chipset for use in XFP trans-
ceiver modules. The chipset is XFI compliant and offers
multirate operation for data rates from 9.95Gbps to
11.1Gbps.
The MAX3991 has 7mVP-Pinput sensitivity (BER ≤10-12),
which allows direct connection to a transimpedance
amplifier without the use of a stand-alone limiting amplifi-
er. The phase-locked loop (PLL) is optimized for jitter tol-
erance and provides 0.6UI of high-frequency tolerance
in SONET, Ethernet, and Fibre-Channel applications. The
MAX3991 output provides 27% margin to the XFP eye
mask specification.
An AC-based power detector toggles the loss-of-signal
(LOS) output when the input signal swing is below the
user-programmed assert threshold. An external refer-
ence clock, with frequency equal to 1/64 or 1/16 of the
serial data rate is used to aid in frequency acquisition. A
loss-of-lock (LOL) indicator is provided to indicate the
lock status of the receiver PLL.
The MAX3991 is available in a 4mm x 4mm, 24-pin QFN
package. It consumes 350mW from a single +3.3V supply
and operates over the 0°C to +85°C temperature range.
Applications

9.95Gbps to 11.1Gbps Optical XFP Modules
SONET OC-192/SDH STM-64 XFP Transceivers
10.3Gbps/11.1Gbps Ethernet XFP Transceivers
10.5Gbps Fibre-Channel XFP Transceivers
10Gbps DWDM Transceivers
Features
Multirate Operation from 9.95Gbps to 11.1Gbps7mVP-P Input Sensitivity (BER ≤10-12)0.6UIP-P Total High-Frequency Jitter ToleranceLow-Output Jitter Generation: 7mUIRMSLow-Output Deterministic Jitter: 4.6psP-PXFI-Compliant Output InterfaceLOS Indicator with Programmable ThresholdLOL IndicatorPower Dissipation: 350mW
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier

19-3486; Rev 0; 11/04
Ordering Information
Typical Application Circuit appears at end of data sheet.

*Future product—contact factory for availability.
+Denotes lead-free package.
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +4.0V
Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-)....................................(VCC- 1.0V) to (VCC+ 0.5V)
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-)......................................(VCC- 1.0V) to (VCC+ 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2)..............................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C).........1355mW
Junction Temperature Range............................-40°C to +150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s)..……………………..+300°C
ELECTRICAL CHARACTERISTICS

(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)

(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)

(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
Note 1:
Measured with 100mVP-Pdifferential amplitude.
Note 2:
Guaranteed by design and characterization.
Note 3:
Measured from the time that the FCTL1 input goes high with FCTL2 = 0 to the time when the supply current drops to less
than 40% of the nominal value.
Note 4:
Measured with PRBS = 231 - 1.
Note 5:
Measurement limited by test equipment.
Note 6:
Jitter tolerance is for BER ≤10-12, measured with additional 0.1UI deterministic jitter and 40mVP-Pdifferential input.
Note 7:
Measured with 50kHz to 80MHz SONET filter.
Note 8:
Applies on power-up, after standby.
Note 9:
Over process, temperature, and supply.
Note 10:
Hysteresis is defined as 20Log(VLOS-DEASSERT /VLOS-ASSERT).
Table 2. Serial Data Rate and Reference Clock Frequency
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier

Figure 1. RX LOL Assert and PLL Acquisition Time
Figure 2. LOS Assert/Deassert Time
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
Typical Operating Characteristics

(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
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