MAX3991UTG+ ,10Gbps Clock and Data Recovery with Limiting AmplifierApplications Pin Configuration9.95Gbps to 11.1Gbps Optical XFP ModulesTOP VIEWSONET OC-192/SDH STM- ..
MAX3992UTG+ ,10Gbps Clock and Data Recovery with EqualizerApplications9.95Gbps to 11.1Gbps Optical XFP ModulesTOP VIEWSONET OC-192/SDH STM-64 XFP Transceiver ..
MAX3996CGP ,3.0V to 5.5V / 2.5Gbps VCSEL and Laser DriverApplicationsFibre Channel Optical Transmitters0.01µ FVCCSHDNDRVTX_DISABLEVCSEL Transmitters0.01µ FG ..
MAX3996CTP+ ,+3.0V to +5.5V, 2.5Gbps VCSEL and Laser DriverApplicationsFibre Channel Optical Transmitters0.01μFVCC SHDNDRVTX_DISABLEVCSEL Transmitters0.01μFGi ..
MAX3996CTP+T ,+3.0V to +5.5V, 2.5Gbps VCSEL and Laser DriverELECTRICAL CHARACTERISTICS(V = 3.0V to 5.5V, T = 0°C to +70°C, unless otherwise noted. Typical valu ..
MAX399CEE+ ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersApplicationsMAX398CGE 0°C to +70°C 16 QFN-EP* G1655-3Sample-and-Hold CircuitsMAX398CEE 0°C to +70°C ..
MAX749CPA+ ,Digitally Adjustable LCD Bias SupplyGeneral Description ________
MAX749CSA ,Digitally Adjustable LCD Bias SupplyFeaturesThe MAX749 generates negative LCD-bias contrast' +2.0V to +6.0V Input Voltage Rangevoltages ..
MAX749CSA ,Digitally Adjustable LCD Bias SupplyFeaturesThe MAX749 generates negative LCD-bias contrast' +2.0V to +6.0V Input Voltage Rangevoltages ..
MAX749CSA+ ,Digitally Adjustable LCD Bias SupplyApplications______________Ordering InformationNotebook ComputersPART TEMP. RANGE PIN-PACKAGELaptop ..
MAX749CSA+T ,Digitally Adjustable LCD Bias SupplyApplications______________Ordering InformationNotebook ComputersPART TEMP. RANGE PIN-PACKAGELaptop ..
MAX749EPA ,Digitally Adjustable LCD Bias SupplyMAX74919-0143; Rev 1; 2/95Digitally Adjustable LCD Bias Supply_______________
MAX3991UTG+
10Gbps Clock and Data Recovery with Limiting Amplifier
General DescriptionThe MAX3991 is a 10Gbps clock and data recovery
(CDR) with limiting amplifier IC for XFP optical receivers.
The MAX3991 and the MAX3992 (CDR with equalizer)
form a signal conditioner chipset for use in XFP trans-
ceiver modules. The chipset is XFI compliant and offers
multirate operation for data rates from 9.95Gbps to
11.1Gbps.
The MAX3991 has 7mVP-Pinput sensitivity (BER ≤10-12),
which allows direct connection to a transimpedance
amplifier without the use of a stand-alone limiting amplifi-
er. The phase-locked loop (PLL) is optimized for jitter tol-
erance and provides 0.6UI of high-frequency tolerance
in SONET, Ethernet, and Fibre-Channel applications. The
MAX3991 output provides 27% margin to the XFP eye
mask specification.
An AC-based power detector toggles the loss-of-signal
(LOS) output when the input signal swing is below the
user-programmed assert threshold. An external refer-
ence clock, with frequency equal to 1/64 or 1/16 of the
serial data rate is used to aid in frequency acquisition. A
loss-of-lock (LOL) indicator is provided to indicate the
lock status of the receiver PLL.
The MAX3991 is available in a 4mm x 4mm, 24-pin QFN
package. It consumes 350mW from a single +3.3V supply
and operates over the 0°C to +85°C temperature range.
Applications9.95Gbps to 11.1Gbps Optical XFP Modules
SONET OC-192/SDH STM-64 XFP Transceivers
10.3Gbps/11.1Gbps Ethernet XFP Transceivers
10.5Gbps Fibre-Channel XFP Transceivers
10Gbps DWDM Transceivers
FeaturesMultirate Operation from 9.95Gbps to 11.1Gbps7mVP-P Input Sensitivity (BER ≤10-12)0.6UIP-P Total High-Frequency Jitter ToleranceLow-Output Jitter Generation: 7mUIRMSLow-Output Deterministic Jitter: 4.6psP-PXFI-Compliant Output InterfaceLOS Indicator with Programmable ThresholdLOL IndicatorPower Dissipation: 350mW
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier19-3486; Rev 1; 11/05
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX3991UTG0°C to +85°C24 QFNT2444-4
MAX3991UTG+*0°C to +85°C24 QFNT2444-4
VCC1
GND2
SDI+3
SDI-4
GND5
VCC6
VCC18
GND17
SDO+16
SDO-15
GND14
VCC13
SCLKO+
SCLKO-
FCTL2
POL
CFIL
VTH
FCTL1
REFCLK-
REFCLK+
LOS
LOL
MAX3991
4mm x 4mm QFN**THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
TOP VIEW
Pin Configuration
Typical Application Circuit appears at end of data sheet.*Future product—contact factory for availability.
+Denotes lead-free package.
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +4.0V
Input Voltage Levels
(SDI+, SDI-, REFCLK+,
REFCLK-)....................................(VCC- 1.0V) to (VCC+ 0.5V)
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-)......................................(VCC- 1.0V) to (VCC+ 0.5V)
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2)..............................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
24-Pin QFN (derate 20.8mW/°C above +85°C).........1355mW
Junction Temperature Range............................-40°C to +150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s)..……………………..+300°C
ELECTRICAL CHARACTERISTICS(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSSupply CurrentICC106140mA
DATA INPUT SPECIFICATION (SDI±)Single-Ended Input ResistanceRSE425058Ω
Differential Input ResistanceRD84100116Ω
Single-Ended Input Resistance
Matching±5%
0.1GHz to 5.5GHz (Note 1)12.5Differential Input Return LossSDD115.5GHz to 12GHz (Note 1)6dB
DC Cancellation Loop Low-
Frequency Cutoff30kHz
REFERENCE CLOCK SPECIFICATION (REFCLK±)Single-Ended Input Resisitance84100116Ω
Differential Input Resistance168200232Ω
CML OUTPUT SPECIFICATION (SDO±)SDO± Differential Output Swing(Note 2)575650725mVP-P
SDO± Output Common-Mode
VoltageRL = 50Ω to VCCVCC -
0.16V
SCLKO± Differential Output380mVP-P
Single-Ended Output Resistance425058Ω
Differential Output ResistanceRO84100116Ω
Single-Ended Output Resistance
Matching±5%
0.1GHz to 5.5GHz (Note 1)13Differential Output Return LossSDD225.5GHz to 12GHz (Note 1)8dB
Common-Mode Output ReturnSCC220.1GHz to 15GHz (Note 1)5dB
Rise/Fall Time(20% to 80%) (Note 2)182330ps
Output AC Common Mode(Note 2)10mVRMS
Power-Down Assert Time(Note 3)50µs
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
JITTER SPECIFICATION120kHz < f ≤ 8MHz (Notes 2, 4)0.050.25Jitter PeakingJPf ≤ 120kHz (Note 5)0.03dB
Jitter Transfer BandwidthJBW(Notes 2, 4)5.68.0MHz
f = 400kHz3.0>3 (Note 6)
f = 4MHz0.55>0.6 (Note 6)Sinusoidal Jitter Tolerance(Notes 2, 4, 7)
f = 80MHz0.45>0.5 (Note 6)
UIP-P
Jitter Generation(Notes 2, 4, 8)4.511.0m U IRM S
Serial Data Output Deterministic
JitterDJPRBS 27 - 1 (Note 2)4.613psP-P
PLL ACQUISITION/LOCK SPECIFICATIONAcquisition TimeFigures 1, 2 (Note 2)200µs
LOL Assert TimeFigure 1 (Note 2)90µs
Maximum Frequency Pullin Time(Note 9)2ms
Frequency Difference at which
LOL is Asserted∆f/fREFCLK∆f = |fVCO / N - fREFCLK|,
N = 16 or 64651ppm
Frequency Difference at which
LOL is DeAsserted∆f/fREFCLK∆f = |fVCO / N - fREFCLK|,
N = 16 or 64500ppm
LOSS-OF-SIGNAL (LOS) SPECIFICATIONVTH Control Voltage RangeVTH150500mV
LOS Gain FactorVTH/
VLOS_ASSERT10V/V
Minimum LOS Assert VoltageVLOS_ASSERT15mV
Maximum LOS Assert VoltageVLOS_ASSERT50mV
LOS Gain-Factor Accuracy(Notes 2, 10)-1.5+1.5dB
LOS Hysteresis(Notes 2, 11)3.53.73.9dB
LOS Gain-Factor Stability(Note 2) Overtemperature and supply-10+10%
LOS Assert TimeFigure 2 (Note 2)390µs
LOS Deassert TimeFigure 2 (Note 2)90µs
VTH Input Current-5+5µA
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2)Input High VoltageVIH2.0V
Input Low VoltageVIL0.8V
Input Current-30+30µA
Output High VoltageVOHSourcing 30µAVCC -
0.5V
Output Low VoltageVOLSinking 1mA0.4V
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)(See Table 1 for operating conditions. Typical values at VCC= +3.3V, TA= +25°C, unless otherwise noted.)
Note 1:Measured with 100mVP-Pdifferential amplitude.
Note 2:Guaranteed by design and characterization.
Note 3:Measured from the time that the FCTL1 input goes high with FCTL2 = 0 to the time when the supply current drops to less
than 40% of the nominal value.
Note 4:Measured with PRBS = 231 - 1.
Note 5:Larger CFILTcan be used to reduce jitter peaking at ≤120kHz. A larger CFILTwill increase acquisition time. CFILTshould
not exceed 200nF.
Note 6:Measurement limited by test equipment.
Note 7:Jitter tolerance is for BER ≤10-12, measured with additional 0.1UI deterministic jitter and 40mVP-Pdifferential input.
Note 8:Measured with 50kHz to 80MHz SONET filter.
Note 9:Applies on power-up, after standby.
Note 10:Over process, temperature, and supply.
Note 11:Hysteresis is defined as 20Log(VLOS-DEASSERT /VLOS-ASSERT).
Table 2. Serial Data Rate and Reference Clock Frequency
APPLICATIONDATA RATE (Rb)
(Gbps)
/16 REFERENCE CLOCK
FREQUENCY (MHz)
/64 REFERENCE CLOCK
FREQUENCY (MHz)OC-192 SONET – SDH649.95328622.08155.52
OC-192 SONET Over FEC10.664666.5166.625
ITU G.70910.709669.3125167.328125
10Gbps Ethernet, IEEE 802.3ae10.3125644.53125161.1328125
10 Gigabit Ethernet Over ITU G.70911.09573693.483125173.3707813
10Gbps Fibre Channel10.51875657.421875164.355469
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply VoltageVCC3.03.6V
Ambient TemperatureTA0+85°C
Input Data RateRb(See Tab l e 2 ) GbpsD I± D i ffer enti al Inp ut V ol tag e S w i ng VD151000mVP-P
Load ResistanceRLRL is AC-coupled50Ω
REFCLK± Differential Input Voltage
Swing3001600mVP-P
REFCLK Duty Cycle3070%
Rb / 16REFCLK FrequencyfREFCLKRb / 64GHz
REFCLK AccuracyRelative to Rb / 16 or Rb / 64-100+100ppm
fREFCLK= Rb / 641200REFCLK Rise/Fall Times (20% to
80%)fREFCLK= Rb / 16300ps
REFCLK Random JitterNoise bandwidth < 100MHz10psRMS
Note: The part should be in standby mode when data rates are being switched.
MAX3991
10Gbps Clock and Data Recovery
with Limiting AmplifierFigure 1. RX LOL Assert and PLL Acquisition Time
LOL
ACQUISITION
TIME
∆f/fREFCLK
LOL
ASSERT TIME
*ASSERT AND ACQUISITION TIME ARE DEFINED
WITH A VALID REFERENCE CLOCK APPLIED.
651ppm
500ppm
Figure 2. LOS Assert/Deassert Time
LOS
LOS DEASSERT TIME
DATA INPUT
POWER
LOS ASSERT TIME
LOL
ACQUISITION TIME
MAX3991
10Gbps Clock and Data Recovery
with Limiting Amplifier
Typical Operating Characteristics(VCC= 3.3V, TA= +25°C, unless otherwise noted.)
20ps/div
MAX3991 OUPTUT AFTER XFP CONNECTOR
(INPUT = 9.95328Gbps, 231-1 PATTERN, 10mVP-P)MAX3991 toc01
20ps/div
MAX3991 OUTPUT
(INPUT = 9.95328Gbps, 231-1 PATTERN)MAX3991 toc02
JITTER GENERATION vs. POWER-SUPPLY
WHITE NOISE AMPLITUDE (BW < 100kHz)
MAX3991 toc03
NOISE AMPLITUDE (mVRMS)
JITTER GENERATION (mUI
RMS
SUPPLY-INDUCED OUTPUT JITTERMAX3991 toc04
FREQUENCY (Hz)
ADDITIONAL OUTPUT JITTER (ps
P-P/
P-P100k10k
0.0710M
JITTER TOLERANCE vs. FREQUENCYMAX3991 toc05
FREQUENCY (Hz)
JITTER TOLERANCE (U|
P-P
10M1M100k
10k100M
TOLERANCE EXCEEDS
MODULATION
CAPABILITIES OF TEST
EQUIPMENT
INPUT = 30mVP-P,
PRBS 231-1,
10.095Gbps, 0.2UIP-P
SONET MASK
SINUSOIDAL JITTER TOLERANCE
vs. INPUT AMPLITUDE
MAX3991 toc06
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
80MHz JITTER TOLERANCE (U|
P-P
PATTERN = 231 -1
PRBS WITH 0.2UIP-P
ADDITIONAL
DETERMINISTIC
JITTER, 10.095Gbps
BIT ERROR RATIO
vs. INPUT AMPLITUDEMAX3991 toc07
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
BIT ERROR RATIO
1.0E-11
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
1.0E-00
1.0E-12
JITTER TRANSFER
MAX3991 toc08
FREQUENCY (MHz)
JITTER TRANSFER (dB)100k10k
-2110M100M
SUPPLY CURRENT vs. TEMPERATURE
MAX3991 toc09
AMBIENT TEMPERATURE (°C)
(mA)
