MAX3953UGK ,+3.3 V, 10 Gbps 1:16 deserializer with clock-recoveryApplications PART TEMP RANGE PIN-PACKAGEo oMAX3953UGK 0 C to +85 C 68 QFN (10mm × 10mm)10Gbps Ether ..
MAX395CWG ,Serially Controlled, Low-Voltage, 8-Channel SPST SwitchApplicationsMAX395EWG -40°C to +85°C 24 Wide SOSerial Data-Acquisition Industrial and Process-MAX39 ..
MAX395CWG+ ,Serially Controlled, Low-Voltage, 8-Channel SPST SwitchApplicationsMAX395EWG -40°C to +85°C 24 Wide SOSerial Data-Acquisition Industrial and Process-MAX39 ..
MAX395EAG ,Serially Controlled, Low-Voltage, 8-Channel SPST SwitchFeaturesThe MAX395 8-channel, serially controlled, single-pole/sin-♦ SPI™/QSPI™, Microwire™-Compati ..
MAX3964AETP ,+3 V to +5.5 V, 125 Mbps to 155 Mbps limiting amplifier with loss-of-signal detectorApplicationso oMAX3968CEP 0 C to +70 C 20 QSOP125Mbps FDDI Receiverso oMAX3968C/D 0 C to +70 C Dice ..
MAX3964ETP ,+3.0 to +5.5 V, 124 to 266 Mbps limiting amplifier with loss-of-signal detectorApplicationso oMAX3968CEP 0 C to +70 C 20 QSOP125Mbps FDDI Receiverso oMAX3968C/D 0 C to +70 C Dice ..
MAX7456EUI+ ,Single-Channel Monochrome On-Screen Display with Integrated EEPROMApplicationsMAX7456EUI+ 28 TSSOP-EP*JapaneseIn-Cabin Entertainment*EP = Exposed pad.Consumer Electr ..
MAX7456EUI+T ,Single-Channel Monochrome On-Screen Display with Integrated EEPROMELECTRICAL CHARACTERISTICS(V = +4.75V to +5.25V, V = +4.75V to +5.25V, V = +4.75V to +5.25V, T = T ..
MAX745EAP ,Switch-Mode Lithium-Ion Battery-ChargerApplicationsrefer to the MAX1647 and MAX1648. For a low-costlithium-ion charger using a linear-regu ..
MAX745EAP ,Switch-Mode Lithium-Ion Battery-ChargerFeaturesThe MAX745 provides all functions necessary for' Charges 1 to 4 Lithium-Ion Battery Cellsch ..
MAX745EAP+ ,Switch-Mode Lithium-Ion Battery-ChargerApplicationsMAX745C/D 0°C to +70°C Dice*MAX745EAP -40°C to +85°C 20 SSOPLi+ Battery PacksDesktop Cr ..
MAX745EAP+ ,Switch-Mode Lithium-Ion Battery-ChargerFeaturesThe MAX745 provides all functions necessary for ♦ Charges 1 to 4 Li+ Battery Cellscharging ..
MAX3953UGK
+3.3 V, 10 Gbps 1:16 deserializer with clock-recovery
General DescriptionThe MAX3953 is a 9.953Gbps/10.3125Gbps 1:16 dese-
rializer with clock recovery for 10Gbps Ethernet and
OC192 SONET applications. The integrated phase-
locked loop (PLL) recovers a clock from the serial data
input, and the data is then retimed and demultiplexed
into 16 parallel LVDS outputs. Using Maxim’s SiGe
bipolar process, the MAX3953 can achieve 0.75UI of
high-frequency jitter tolerance comprised of 0.50UI of
deterministic jitter and 0.25UI of random jitter.
The MAX3953 includes TTL-compatible loss-of-lock
(LOL) and sync-error (SYNC_ERR) indicators that allow
the user to verify that the part has locked on to incoming
data. In case the incoming data becomes invalid, a
clock holdover function is provided to maintain a valid
reference clock to the upstream device. For proper
operation, a reference clock of baud rate/64 or baud
rate/16 is required.
The MAX3953 operates from a single +3.3V power sup-
ply and typically dissipates 1.5W. The operating tem-
perature range is from 0°C to +85°C. The MAX3953 is
available in a 68-pin QFN package.
Applications10Gbps Ethernet LAN
10Gbps Ethernet WAN
Add/Drop Multiplexers
Digital Cross-Connects
FeaturesSerial Data Rate: 9.953Gbps/10.3125GbpsClock Recovery with 1:16 Demultiplexer0.75UIP-PHigh-Frequency Jitter Tolerance16-Bit Parallel LVDS OutputOIF-Compliant Parallel InterfaceLoss-of-Lock (LOL) IndicatorDifferential Input Range: 100mVP-Pto 1.2VP-PClock Holdover Reference Clock: Baud Rate/64 or Baud Rate/16 Temperature Range: 0°C to +85°C10mm ✕10mm 68-Pin QFN Package
MAX3953
10Gbps 1:16 Deserializer with Clock Recovery
Ordering Information
Typical Operating Circuit19-2624; Rev 1; 5/04
Pin Configuration and Functional Diagram appear at end of
data sheet.
MAX3953
10Gbps 1:16 Deserializer with Clock Recovery
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCC)............................................-0.5V to +5.0V
Input Voltage Levels
(SDI+, SDI-).................................(VCC- 1.0V) to (VCC+ 0.5V)
LVDS Output Voltage Levels
(PDO[15..0]±, PCLKO+, PCLKO-).........-0.5V to (VCC+ 0.5V)
Voltage at LOL, SYNC_ERR, RATESET, CLKSEL, REFCLK+,
REFCLK-, REFSET, LOS_IN, FIL............-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= 85°C)
68-Lead QFN (derate 30.3mW/°C above +85°C)............2.5W
Operating Temperature Range..............................0°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Processing Temperature (die).........................................+400°C
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at +3.3V and TA= +25°C, unless otherwise noted.)
MAX3953
10Gbps 1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at +3.3V and TA= +25°C, unless otherwise noted.) (Note 2)
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at +3.3V and TA= +25°C, unless otherwise noted.)
MAX3953
10Gbps 1:16 Deserializer with Clock Recovery
Note 3:Measured with 0.45UIP-Pdeterministic jitter and 0.15UIP-Prandom jitter, on top of the specified sinusoidal jitter in a 231- 1
PRBS pattern with a BER = 10-12.
Note 4:The jitter tolerance exceeds IEEE 802.3AE specifications. The jitter tolerance outperforms the instrument’s measurement
capability.
AC ELECTRICAL CHARACTERISTICS(VCC
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX3953
10Gbps 1:16 Deserializer with Clock Recovery
MAX3953
Detailed DescriptionThe MAX3953 deserializer with clock recovery converts
9.953Gbps/10.3125Gbps serial data into 16-bit wide,
622Mbps/644Mbps parallel data. The device combines a
fully integrated phase-locked loop (PLL), TTL-compatible
status monitors, input amplifier, data retiming block,
16-bit demultiplexer, clock dividers, and LVDS output
buffers. The PLL consists of a phase/frequency detec-
tor (PFD), a loop filter, and voltage-controlled oscillator
(VCO). The PLL recovers the serial clock from the input
data stream and retimes the data. The demultiplexer
generates a 16-bit-wide 622Mbps/644Mbps parallel
data output. The MAX3953 is designed to deliver the
best jitter performance by using differential signal
architecture and low-noise design techniques.
Input AmplifierThe serial data input (SDI) amplifier accepts differential
input amplitudes from 100mVP-Pto 1200mVP-P.
Phase-Frequency DetectorThe digital phase-frequency detector (PFD) aids frequen-
cy acquisition during startup conditions. Depending on
the polarity of the frequency input difference between
REFCLK and the VCO clock, the PFD drives the VCO until
the frequency difference is reduced to zero. False locking
is eliminated by this digital phase-frequency detector.
The data phase detector is optimized to achieve 0.75UI
high-frequency jitter tolerance.
Loop Filter and VCOThe phase detector and frequency detector outputs are
summed into the loop filter. A 0.047µF capacitor (CF) is
required to set the PLL damping ratio. The loop filter
output controls the on-chip VCO.
Loss-of-Lock MonitorA loss-of-lock (LOL) monitor is included in the MAX3953
frequency detector. A loss-of-lock condition is signaled
with a TTL low. When the PLL is frequency locked, LOL
switches to TTL high in approximately 56µs.
LOLsignals a TTL low when the VCO frequency is
more than 1000ppm from the reference clock frequen-
cy. LOLsignals a TTL high when the VCO frequency is
within 500ppm of the reference clock frequency.
Low-Voltage Differential Signal (LVDS)
OutputsThe MAX3953 features LVDS outputs for interfacing with
high-speed circuitry. The LVDS standard is based on the
IEEE 1596.3 LVDS specification. This technology uses
500mVP-Pto 800mVP-Pdifferential low-voltage swings to
achieve fast transition times, minimize power dissipation,
and improve noise immunity.
Applications Information
Aquisition ControlsThe MAX3953 has two phase-detector circuits, a Bang-
Bang phase detector to lock the VCOto the serial input
data (BB_PD), and a phase detector to lock the VCOto
the reference clock (REF_PD). The pull-in range for the
REF_PD is wide enough to accomodate the VCO turn-
ing range across the two valid data rates, while the
pull-in range for the BB_PD is narrow. The REF_PDis
activated by CLKSEL= HIGH. The BB_PDis activated
by CLKSEL = LOW. For the MAX3953 CDR to lock to
the serial input data, the frequency of the VCOmust be
pulled within 500ppm of the input data rate by first lock-
ing the VCO to the reference clock (RECLK) via the
REF_PD. Once the VCOis within 500ppm, control can
be transferred to the BB_PD.
For normal operation, connect the SYNC_ERRoutput to
the CLKSEL input. This will force CLKSEL high when
the MAX3953 frequency detector indicates that the
VCO frequency is more than 500ppm from the
REFLECK frequency. Once the VCOis pulled to within
500ppm of the REFCLK frequency, SYNC_ERR(and
thus CLKSEL) will go low and the MAX3953 will lock to
the SDIdata stream.
If a loss-of-signal (LOS) input from the system is available
to the MAX3953, a clock holdover operation can be imple-
mented by connecting the LOSoutput to the LOS_IN
input. This will force the PLL to lock to REFCLK whenever
the incoming data is lost. This keeps the frequency of
PCLKO from drifting during a loss-of-signal condition. If
the LOSsignal from the system is not available, or if the
clock-holdover mode is not required, the LOS_INmust be
connected to VCCto disable the function.
Consecutive Identical Digits (CIDs)The MAX3953 has a low phase and frequency drift in the
absence of data transitions. As a result, long runs of con-
secutive zeros and ones can be tolerated while maintain-
ing a BER of 1 ✕10-12. The CID tolerance is tested using
a 213- 1 pseudorandom bit stream (PRBS), substituting a
long run of zeros to simulate worst case. A CID tolerance
of greater than 2,000 bits is typical.
Exposed-Pad PackageThe exposed pad, 68-pin QFN incorporates features
that provide a very low thermal-resistance path for heat
removal from the IC. The pad is electrical ground on
the MAX3953 and should be soldered to the circuit
board for proper thermal and electrical performance.
See Maxim Application Note HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packagesfor further information.
10Gbps 1:16 Deserializer with Clock Recovery
