MAX3882AETX+ ,2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting AmplifierApplications Ordering InformationSDH/SONET Receivers and RegeneratorsPART TEMP RANGE PIN-PACKAGE MA ..
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MAX388CPN ,High-Voltage, Fault-Protected Analog MultiplexersGeneral Description
The MAX388 8-channel single-ended (I-ot-to and the
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(V+ " 15v. v- = -15v. GND = WA = OV, AB = +2.4v, TA = +25'C ..
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MAX7428EKA/T ,Standard Definition Video Reconstruction Filters and Buffersapplications. ThePackage (MAX7432)MAX7432 triple filter is optimized for component (YP Pb ror embed ..
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MAX742CPP ,Switch-Mode Regulator with +5V to 【12V or 【15V Dual Outputfeatures undervoltage lockout, thermal shut-down, and programmable soft-start. MAX742C/D 0°C to +70 ..
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MAX3882AETX+
2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
General DescriptionThe MAX3882A is a deserializer combined with clock
and data recovery and limiting amplifier ideal for con-
verting 2.488Gbps serial data to 4-bit-wide, 622Mbps
parallel data for SDH/SONET applications. The device
accepts serial NRZ input data as low as 10mVP-Pof
2.488Gbps and generates four parallel LVDS data out-
puts at 622Mbps. Included is an additional high-speed
serial data input for system loopback diagnostic test-
ing. For data acquisition, the MAX3882A does not
require an external reference clock. However, if need-
ed, the loopback input can be connected to an external
reference clock of 155MHz or 622MHz to maintain a
valid clock output in the absence of input data transi-
tions. Additionally, a TTL-compatible loss-of-lock output
is provided. The device provides a vertical threshold
adjustment to compensate for optical noise generated
by EDFAs in WDM transmission systems. The
MAX3882A operates from a single +3.3V supply and
consumes 610mW.
The MAX3882A’s jitter performance exceeds all SDH/
SONET specifications. The device is available in a 6mm6mm, 36-pin TQFN package.
ApplicationsSDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SDH/SONET Test Equipment
DWDM Transmission Systems
FeaturesNo Reference Clock Required for Data AcquisitionSerial Input Rate: 2.488GbpsFully Integrated Clock and Data Recovery with
Limiting Amplifier and 1:4 DemultiplexerParallel Output Rate: 622MbpsDifferential Input Range: 10mVP-Pto 1.6VP-P
without Threshold AdjustDifferential Input Range: 50mVP-Pto 600mVP-P
with Threshold Adjust0.65UI High-Frequency Jitter ToleranceLoss-of-Lock (LOL) IndicatorWide Input Threshold Adjust Range: ±170mVMaintain Valid Clock Output in Absence of Data
TransitionsSystem Loopback Input Available for System
Diagnostic TestingOperating Temperature Range -40°C to +85°CLow Power Dissipation: 610mW at +3.3VGND
VCC_VCO
FIL
VCC_VCO
VCC_OUT
GND
PCLK-
VREF
CAZ-
CAZ+
VCC
TQFNVCC
FREFSET
GND34567892625242322212019
VCC_OUT18PCLK+LREF36
MAX3882A
VCTRL
SIS
SLBI-
SLBI+
SDI-SDI+
GND
PD0+PD1-PD1+GNDPD2-PD2+PD3-PD3+PD0-
LOL
*EP
*EXPOSED PAD.
TOP VIEW
19-2718; Rev 2; 4/09
Pin Configuration+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE MAX3882AETX+-40°C to +85°C36 TQFN-EP*
Typical Application Circuits appear at end of data sheet.
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC................................................-0.5 to +5.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-)...........(VCC- 1.0V) to (VCC + 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA
LVDS Output Voltage Levels
(PCLK±, PD_±).......................................-0.5V to (VCC+ 0.5V)
Voltage at LOL, SIS, LREF, VREF, FIL, CAZ+,
CAZ-, VCTRL, FREFSET..........................-0.5V to (VCC + 0.5V)
Continuous Power Dissipation (TA= +70°C)
36-Pin TQFN (derate 35.7mW/°C above +70°C)......2856mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Supply Current ICC 185 230 mA
Single-Ended Input Voltage
Range VIS Figure 1 VCC -
0.8
VCC +
0.4 V
Input Common-Mode Voltage
Range Figure 1 VCC -
0.4 VCC V
Input Termination to VCC RIN 42.5 50 57.5
Differential Input Voltage Range
with Threshold Adjust Enabled
SDI+, SDI-
Figure 2 100 600 mVP-P
Threshold Adjustment Range VTH Figure 2 -170 +170 mV
Threshold-Control Voltage VCTRL (Note 2) 0.302 2.097 V
Threshold-Control Linearity ±5 %
Threshold Setting Accuracy Figure 2 -18 +18 mV
15mV |VTH| 80mV -6 +6 Threshold Setting Stability 80mV < |VTH| 170mV -12 +12mV
VREF Voltage Output RL = 50k 2.14 2.2 2.24 V
LVDS Output High Voltage VOH 1.475 V
LVDS Output Low Voltage VOL 0.925 V
LVDS Differential Output Voltage |VOD| 250 400 mV
LVDS Change in Magnitude of
Differential Output Voltage for
Complementary States
|VOD| 25 mV
LVDS Offset Output Voltage 1.125 1.275 V
LVDS Change in Magnitude of
Output Offset Voltage for
Complementary States
|VOS| 25 mV
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS LVDS Differential Output
Impedance 80 120
LVDS Output Current Short together or short to GND 12 mA
LVTTL Input High Voltage VIH 2.0 V
LVTTL Input Low Voltage VIL 0.8 V
LVTTL Input Current -10 +10 μA
LVTTL Output High Voltage VOH IOH = +20μA 2.4 V
LVTTL Output Low Voltage VOL IOL = -1mA 0.4 V
Note 1:At -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:Voltage applied to VCTRLpin is from 0.302V to 2.097V when input threshold is adjusted from +170mV to -170mV.
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Serial Input Data Rate 2.488 Gbps
Differential Input Voltage
Threshold Adjust Disabled
SDI+, SDI-
VID(Note 4) Figure 1 10 1600 mVP-P
Differential Input Voltage SLBI+,
SLBI- 50 800 mVP-P
Jitter Peaking JP f 2MHz 0.1 dB
Jitter Transfer Bandwidth JBW 1.7 2.0 MHz
f = 100kHz 3.1 4.1
f = 1MHz 0.62 1.0 Sinusoidal Jitter Tolerance
f = 10MHz 0.44 0.6
UIP-P
f = 100kHz 4.1
f = 1MHz 0.75
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
(Note 5) f = 10MHz 0.41
UIP-P
Jitter Generation JGEN (Note 6) 2.7 psRMS
100kHz to 2.5GHz 17 Differential Input Return Loss 20log|S11|2.5GHz to 4.0GHz 15 dB
Tolerated Consecutive Identical
Digits BER = 10-10 2000 Bits
0011 pattern 0.6 Acquisition Time (Note 7)
Figure 4 PRBS 223 - 1 pattern 0.62 1.5 ms
LOL Assert Time Figure 4 2.3 100.0 μs
Low-Frequency Cutoff for
DC Offset Cancellation Loop CAZ = 0.1μF 4 kHz
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS FREFSET = VCC 155 Reference Clock Frequency FREFSET = GND 622 MHz
Reference Clock Accuracy ±100 ppm
VCO Frequency Drift (Note 8) 400 ppm
Data Output Rate 622 Mbps
Clock Output Frequency 622 MHz
Output Clock-to-Data Delay tCK-Q (Note 9) -80 +80 ps
Clock Output Duty Cycle 45 50 55 %
Clock and Data Output Rise/Fall
Time tR, tF20% to 80% 100 250 ps
LVDS Differential Skew tSKEW1 Any differential pair 50 ps
LVDS Channel-to-Channel Skew tSKEW2 PD_± 100 ps
Note 3:AC characteristics are guaranteed by design and characterization.
Note 4:Jitter tolerance is guaranteed (BER ≤10-10) within this input voltage range. Input threshold adjust is disabled when VCTRLis
connected to VCC.
Note 5:Measured with the input amplitude set at 100mVP-Pdifferential swing with a 20mV offset and an input edge speed of 145ps
(4th-order Bessel filter with f3dB= 1.8GHz).
Note 6:Measured with 10mVP-POC-48 differential input with PRBS 223- 1 and BW = 12kHz to 20MHz.
Note 7:Measured at OC-48 data rate using a 0.068µF loop-filter capacitor.
Note 8:Under LOL condition, the CDR clock output is set by the external reference clock.
Note 9:Relative to the falling edge of PCLK+. See Figure 3.
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
500ps/div
RECOVERED CLOCK AND DATA
(INPUT = 2.488Gbps, 223 - 1
PATTERN, VIN = 10mVP-P)200mV/div
MAX3882A toc01
SUPPLY CURRENT vs. TEMPERATUREMAX3882A toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)50250-25
JITTER TOLERANCE
(2.48832Gbps, 223 - 1 PATTERN,
VIN = 16mVP-P WITH ADDITIONAL
0.15UI DETERMINISTIC JITTER)
MAX3882A toc03
JITTER FREQUENCY (Hz)
JITTER TOLERANCE (UI
P-P
1001k
0.110k
BELLCORE
MASK
JITTER TOLERANCE vs. INPUT AMPLITUDE
(2.48832Gbps, 223 - 1 PATTERN, WITH
ADDITIONAL 0.15UI DETERMINISTIC JITTER)MAX3882A toc04
INPUT AMPLITUDE (mVP-P)
JITTER TOLERANCE (UI
P-P
0.610,000
JITTER FREQUENCY = 10MHz
JITTER TRANSFERMAX3882A toc05
JITTER FREQUENCY (kHz)
TRANSFER (dB)
-4010,000
BELLCORE
MASK
20ps/div
PARALLEL CLOCK OUTPUT JITTERMAX3882A toc06
fCLK = 622.08MHz
TOTAL WIDEBAND
RMS JITTER = 2.720ps
PEAK-TO-PEAK
JITTER = 20.80ps
BIT-ERROR RATE vs. INPUT AMPLITUDEMAX3882A
toc07
INPUT VOLTAGE (mVP-P)
BIT-ERROR RATIO32
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-11
PULLIN RANGEMAX3882A toc08
AMBIENT TEMPERATURE (°C)
FREQUENCY (GHz)3510-15
S11
MAX3882A toc09
FREQUENCY (MHz)
-404000
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
Pin Description
PINNAMEFUNCTION1, 11, 16, 23, 29 GND Supply Ground
2, 5, 31, 32 VCC +3.3V Supply Voltage SDI+ Positive Data Input. 2.488Gbps serial data stream, CML. SDI- Negative Data Input. 2.488Gbps serial data stream, CML. SLBI+ Positive System Loopback Input or Positive Reference Clock Input, CML SLBI- Negative System Loopback Input or Negative Reference Clock Input, CML SIS Signal Input Selection, LVTTL. Low for normal data, high for system loopback. LOL Loss-of-Lock Output, LVTTL, Active Low LREFTTL Control Input for PLL Clock Holdover. Low for PLL lock to reference clock, high for PLL
lock to input data.
12, 14 VCC_VCO Supply Voltage for the VCO
13 FIL PLL Loop-Filter Capacitor Input. Connect a 0.068μF loop-filter capacitor between FIL and
VCC_VCO.
15, 28 VCC_OUT Supply Voltage for LVDS Output Buffers
17 PCLK- Negative Clock Output, LVDS
18 PCLK+ Positive Clock Output, LVDS
19 PD0- Negative Data Output, LVDS
20 PD0+ Positive Data Output, LVDS
21 PD1- Negative Data Output, LVDS
22 PD1+ Positive Data Output, LVDS
24 PD2- Negative Data Output, LVDS
25 PD2+ Positive Data Output, LVDS
26 PD3- Negative Data Output, LVDS, MSB
27 PD3+ Positive Data Output, LVDS, MSB
30 FREFSET Sets Reference Frequency. LVTTL low for 622MHz/667MHz reference, high for
155MHz/167MHz reference.
33 CAZ+ Positive Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1μF capacitor
between CAZ+ and CAZ-.
34 CAZ- Negative Capacitor Input for DC Offset-Cancellation Loop. Connect a 0.1μF capacitor
between CAZ+ and CAZ-.
35 VREF 2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment.
36 VCTRL Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust.
— EP Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper
thermal and electrical performance.
Detailed DescriptionThe MAX3882A deserializer with clock and data recov-
ery and limiting amplifier converts 2.488Gbps serial
data to clean 4-bit-wide, 622Mbps LVDS parallel data.
The device combines a limiting amplifier with a fully inte-
grated phase-locked loop (PLL), data retiming block, 4-
bit demultiplexer, clock divider, and LVDS output buffer
(Figure 5). The PLL consists of a phase/frequency
detector (PFD), loop filter, and voltage- controlled oscil-
lator (VCO). The MAX3882A is designed to deliver the
best combination of jitter performance and power dissi-
pation by using a fully differential signal architecture
and low-noise design techniques.
The input signal to the device (SDI) passes through a
DC offset control block, which balances the input signal
to a zero crossing at 50%. The PLL recovers the serial
clock from the serial input data stream and produces
the properly aligned data and the buffered recovered
clock. The frequency of the recovered clock is divided
by four and converted to differential LVDS parallel out-
put PCLK. The demultiplexer generates 4-bit-wide
622Mbps parallel data.
MAX3882A
2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier 800mV
5mV
VCC
VCC - 0.4V
VCC + 0.4V
VCC - 0.4V
VCC - 0.8V
VCC
(b) DC-COUPLED SINGLE-ENDED INPUT
(a) AC-COUPLED SINGLE-ENDED INPUT5mV
800mV
Figure 1. Definition of Input Voltage Swing
+188
+170
+152
VTH (mV)
THRESHOLD-SETTING STABILITY
(OVER TEMPERATURE AND POWER SUPPLY)
THRESHOLD-SETTING ACCURACY
(PART-TO-PART VARIATION OVER PROCESS)
VCTRL (V)
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
tCK-Q
tCK
PCLK+
(PD+) - (PD-)
Figure 3. Definition of Clock-to-Q Delay
LOL OUTPUT
LOL ASSERT TIMEACQUISITION TIME
INPUT DATA
2.488Gbps PRBS 223 - 1 2.488Gbps PRBS 223 - 1
Figure 4. LOLAssert Time and PLL Acquisition Time
Measurement
