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MAX3880ECB+D
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery
General DescriptionThe MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
Applications2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
FeaturesSingle +3.3V Supply910mW Operating PowerFully Integrated Clock Recovery and Data
RetimingExceeds ANSI, ITU, and Bellcore SpecificationsAdditional High-Speed Input Facilitates System
Loopback Diagnostic Testing2.488Gbps Serial to 155Mbps Parallel ConversionLVDS Data Outputs and Synchronization InputsTolerates >2000 Consecutive Identical DigitsLoss-of-Lock Indicator
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock RecoveryMAX3866
MAX3880PRE/POSTAMPLIFIER
OVERHEAD
TERMINATION
100Ω*
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
+3.3V
PHADJ-VCC
LOLGNDFIL-FIL+SIS
TTLTTL
SDI+OUT+
VCC
IN+
FIL
OUT-
LOP
TTL
SDI-
SLBI-
SLBI+
SYSTEM
LOOPBACK
SYNC+
SYNC-
PD15+
PD15-
100Ω*
PD0+
PD0-
100Ω*
PCLK+
PCLK-
PHADJ+0.01μF
+3.3V
1μF
ypical Application Circuit19-1467; Rev 2; 12/05
PARTMAX3880ECB-40°C to +85°C
TEMP. RANGEPIN-PACKAGE64 TQFP-EP*
Ordering Information*Exposed pad
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.MAX3880ECB+-40°C to +85°C64 TQFP-EP*
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Positive Supply Voltage (VCC)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,
SYNC+, SYNC-)...........................(VCC- 0.5V) to (VCC+ 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at LOL, SIS, PHADJ+, PHADJ-,
FIL+, FIL-.................................................-0.5V to (VCC+ 0.5V)
Output Current LVDS Outputs............................................10mA
Continuous Power Dissipation (TA= +85°C)
TQFP (derate 33.3mW/°C above +85°C).......................1.44W
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Figure 1
Common-mode voltage = 50mV
Figure 2
Differential input voltage = 100mV
CONDITIONS±2.5±10∆RO
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs4095140ROSingle-Ended Output
Resistance±25∆VOS
Change in Magnitude of Output
Offset Voltage for
Complementary States1.1251.275VOSOutput Offset Voltage±25∆|VOD|
Change in Magnitude of
Differential Output Voltage for
Complementary States250400|VOD|Differential Output Voltage0.925VOLOutput Low Voltage
mVp-p50800VIDDifferential Input Voltage275380ICCSupply Current1.475VOHOutput High Voltage85100115RINDifferential Input Resistance78VHYSTThreshold Hysteresis-100100VIDTHDifferential Input ThresholdVCC- 0.4VCC+ 0.2VISSingle-Ended Input Voltage50RINInput Termination to Vcc02.4VIInput Voltage Range
UNITSMINTYPMAXSYMBOLPARAMETER0.8VILInput Low Voltage2.0VIHInput High Voltage2.4VCCVOHOutput High Voltage-10+10Input Current0.4VOLOutput Low Voltage
SERIAL DATA INPUTS (SDI±, SLBI±)
LVDS INPUTS AND OUTPUTS (SYNC±, PCLK±, PD_±)
TTL INPUTS AND OUTPUTS (SIS, LOL)
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, differential loads = 100Ω±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +3.3V, TA= +25°C.) (Note 1)
Note 1:AC characteristics are guaranteed by design and characterization.
Note 2:At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
Figure 5
100kHz to 2.5GHz
f = 10MHz
f = 70kHz (Note 2)
f = 100kHz
f = 1MHz
2.5GHz to 4.0GHz
CONDITIONS-11Input Return Loss (SDI±, SLBI±)200450900tCLK-QParallel Clock-to-Data Output
Delay
Mbps155.52
Gbps2.488SDISerial Data Rate
Parallel Output Data Rate
Bits>2,000Tolerated Consecutive Identical
Digits
UIp-p
Jitter Tolerance
UNITSMINTYPMAXSYMBOLPARAMETER
SDI+
SDI-
VID(SDI+) - (SDI-)50mVp-p MIN
800mVp-p MAX
25mV MIN
400mV MAX
SINGLE-ENDED OUTPUT|VOD|
VPD-VOH
VOS
VOD, p-p = VPD+ - VPD-
-VOD
+VOD0V (DIFF)
VOLVPD+
DIFFERENTIAL OUTPUT
VPD+ - VPD-
PD+
RL = 100ΩVOD
PD-
Figure 1. Input Amplitude
Figure 2. Driver Output Levels
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery1,000100
JITTER TOLERANCE vs. INPUT VOLTAGEMAX3880-04
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE (UIp-p)
JITTER FREQUENCY = 1MHz
JITTER FREQUENCY
= 5MHz
SONET SPEC
BIT ERROR RATE vs. INPUT VOLTAGE
MAX3880-05
INPUT VOLTAGE (mVp-p)
BIT ERROR RATE
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3880-06
TEMPERATURE (°C)
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
1.64ns/div
DATA
CLOCK
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)MAX3880-0123 - 1 PATTERN
SUPPLY CURRENT vs. TEMPERATURE
MAX3880-02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VCC = 3.6V
VCC = 3.0V
0.11,00010,000
JITTER TOLERANCEMAX3880-03
JITTER FREQUENCY (kHz)
INPUT JITTER (UIPp-p)
100
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
NAMEFUNCTION1, 17, 25, 33,
41, 49, 56,
62, 64
GNDGround
PIN
Pin DescriptionFIL+Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.FIL-Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
4, 7, 10, 13,
24, 32, 40,
48, 57
VCC+3.3V Supply VoltagePHADJ+Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCCif not
used.PHADJ-Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCCif not
used.SDI+Positive Serial Data Input. 2.488Gbps data stream.SDI-Negative Serial Data Input. 2.488Gbps data stream.SLBI+Positive System Loopback Input. 2.488Gbps data stream.SLBI-Negative System Loopback Input. 2.488Gbps data stream.SISSignal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).SYNC-Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.SYNC+Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.PCLK-Negative Parallel Clock LVDS OutputPCLK+Positive Parallel Clock LVDS Output
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
PD0- to
PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PD0+ to
PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).LOLLoss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩpull-up resistor). The
LOLmonitor is valid only when a data stream is present on the inputs to the MAX3880.Exposed PadGround. This must be soldered to a circuit board for proper thermal performance (see Package
Information).
MAX3880
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock RecoveryMAX3880
SDI+
AMP
LVDS
PD15+
PD15-
LVDS
LVDS
LVDS
LVDS
LOL
TTL
100Ω
50Ω
50Ω
MUXPHASE &
FREQUENCY
DETECTOR
SDI-
SLBI+
AMP
SLBI-
SIS
VCC
VCC
SYNC-
SYNC+
LOOP
FILTERVCO
16-BIT
DEMULTIPLEXERQ
PHADJ+PHADJ-FIL+FIL-
CLOCK
DIVIDER
PD1+
PD1-
PD0+
PD0-
PCLK+
PCLK-
Figure 3. MAX3880 Functional Diagram
Detailed DescriptionThe MAX3880 deserializer with clock recovery converts
2.488Gbps serial data to 16-bit-wide, 155Mbps parallel
data. The device combines a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
16-bit demultiplexer, clock divider, and LVDS output
buffer (Figure 3). The PLL consists of a phase/frequen-
cy detector (PFD), a loop filter, and a voltage-controlled
oscillator (VCO). The MAX3880 is designed to deliver
the best combination of jitter performance and power
dissipation by using a fully differential signal architec-
ture and low-noise design techniques. The PLL recov-
ers the serial clock from the serial input data stream.
The demultiplexer generates a 16-bit-wide 155Mbps
parallel data output.
The synchronization inputs (SYNC+, SYNC-) realign the
output data word. Realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. During synchronization, the first
incoming bit of data during that PCLK cycle is
