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MAX3873AEGP-T-MAX3873AETP+-MAX3873AETP+T
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC
General DescriptionThe MAX3873A is a compact, low-power 2.488Gbps/
2.67Gbps clock-recovery and data-retiming IC for
SDH/SONET applications. The phase-locked loop (PLL)
recovers a synchronous clock signal from the serial NRZ
data input. The input data is then retimed by this recov-
ered clock, providing a clean data output. The MAX3873A
meets all SDH/SONET jitter specifications, does not
require an external reference clock to aid in frequency
acquisition, and provides excellent tolerance to both
deterministic and sinusoidal jitter. The MAX3873A pro-
vides a PLL loss-of-lock (LOL) output to indicate whether
the CDR is in lock. The recovered data and clock outputs
are CML with on-chip 50Ωback terminations on each line.
The clock output can be powered down if not used.
The MAX3873A is implemented in Maxim’s second-gener-
ation SiGe process and consumes only 260mW at 3.3V
supply (output clock disabled, low output swing). The
device is available in a 4mm x 4mm 20-pin QFN
exposed-pad package and operates from -40°C to +85°C.
ApplicationsSwitch Matrix Backplanes
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SDH/SONET Test Equipment
DWDM Transmission Systems
FeaturesFully Integrated Clock Recovery and Data
RetimingPower Dissipation: 260mW with +3.3V SupplyClock Jitter Generation: 5mUIRMSExceeds ANSI, ITU, and Bellcore SDH/SONET
Jitter SpecificationsDifferential Input Range: 50mVP-Pto 1.6VP-PSingle +3.3V Power SupplyPLL Fast Track (FASTRACK) Mode AvailableClock Output Can Be DisabledInput Data Rate: 2.488Gbps or 2.67GbpsSelectable Output AmplitudeTolerates 2000 Consecutive Identical DigitsLoss-of-Lock IndicatorDifferential CML Data and Clock Outputs Operating Temperature Range: -40°C to +85°C
MAX3873A
Low-Power, Compact 2.5Gbps/2.7Gbps
Clock-Recovery and Data-Retiming IC19-2577; Rev 2; 5/07
EVALUATION KIT
AVAILABLE
Ordering Information
Typical Application Circuit appears at end of data sheet.
Pin Configuration
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX3873AEGP-40°C to +85°C20 QFN
(4mm x 4mm)G2044-3AX 3873AE TP + -40°C to +85°C20 TQFN
(4mm x 4mm)T2044-319181716
GNDFIL+FIL-GNDLOL789
FASTRACK
VCC_VCO
MODE
SCLKEN
**NOTE: THE EXPOSED PAD MUST BE
SOLDERED TO THE SUPPLY GROUND.
SCLKO-
SCLKO+
VCC_BUF
SDO-
SDO+
VCC
SDI-
SDI+
VCC
RATESET
MAX3873A
QFN/TQFN**TOP VIEWDenotes lead-free package.
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, TA= -40°C to +85°C. Typical values are at 2.488Gbps, VCC= 3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +5.0V
Voltage at SDI±..............................(VCC- 1.0V) to (VCC+ 0.5V)
CML Output Current at SDO±, SCLKO±............................22mA
Voltage at LOL, FASTRACK, FIL±, SCLKEN
MODE, RATESET...................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
20-Lead QFN (derate 20.0mW/°C above +85°C).....1300mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-50°C to +150°C
Processing Temperature..................................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMODE = GND, SCLKEN = low7999Supply Current (Note 2)ICCMODE = OPEN, SCLKEN = high112142mA
CML INPUT SPECIFICATIONS (SDI+, SDI-)Differential Input VoltageVIDFigure 1501600mVP-P
Single-Ended Input
VoltageVISFigure 1VCC - 0.8 VCC + 0.4V
Input Common-Mode
VoltageDC-coupled, Figure 1VCC - VID/4V
Input Termination to VCCRIN405060Ω
CML OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-)MODE = open6408001000
MODE = VCC400600800Differential Output Swing
(Note 3)
MODE = GND200400600
mVP-P
Differential Output
ResistanceRO80100120Ω
MODE = OpenVCC - 0.17
MODE = VCCVCC - 0.13Output Common-Mode
Voltage (Note 3)MODE = GNDVCC - 0.08
TTL INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET)Input High VoltageVIH2.0V
Input Low VoltageVIL0.8V
Input Current-30+30µA
Output High VoltageVOHIOH = sourcing 40µA2.4V
Output Low VoltageVOLIOL = sinking 2mA0.4V
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
AC ELECTRICAL CHARACTERISTICS(VCC= 3.0V to 3.6V, CF= 0.022µF, TA= -40°C to +85°C. Typical values are at VCC= 3.3V, 2.488Gbps, TA= +25°C, unless otherwise
noted.) (Note 4)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRATESET = low2.488Serial Input Data RateRATESET = high2.67Gbps
Clock-to-Q DelaytCLK-QFigure 2 (Note 5)-70+70ps
Jitter PeakingJPf ≤ 2MHz0.1dB
Jitter Transfer BandwidthJBWRATESET = Low2.0MHz
f = 70kHz, 0.4UI deterministic jitter
on input data6.9
f = 100kHz, 0.4UI deterministic jitter
on input data2.124.5
f = 1MHz, 0.4UI deterministic jitter
on input data0.330.6
(Notes 6, 8)
f = 10MHz, 0.4UI deterministic jitter
on input data0.150.3
f = 70kHz, 0.4UI deterministic jitter
on input data6.9
f = 100kHz, 0.4UI deterministic jitter
on input data2.124.5
f = 1MHz, 0.4UI deterministic jitter
on input data0.330.6
Sinusoidal Jitter Tolerance
(Notes 6, 9)
f = 10MHz, 0.37UI deterministic jitter
on input data0.150.3
UIP-P6.8mUIRMS(Notes 7, 8)4562mUIP-P7.65mUIRMSJitter GenerationJGEN
(Notes 7, 9)4086mUIP-P
Clock Output Edge
Speed20% to 80%60110ps
Data Output Edge
Speed20% to 80%60110ps
Tolerated Consecutive
Identical Digits2000bits
100kHz to 2.5GHz17SDI± Input Return Loss
(-20log(S11))2.5GHz to 4.0GHz14dB
Frequency Acquisition
TimeFigure 41msLOL Assert TimeFigure 41.6
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming ICFigure 1. Definition of Input Voltage Swing
Figure 2. Definition of Clock-to-Q Delay
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
25mV
800mV
800mV
VCC + 0.4V
VCC
VCC - 0.4V
VCC
VCC - 0.4V
VCC - 0.8V
SCLKO+
SDO
tCLK
tCLK-Q
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL OUTPUT
LOL ASSERT TIME
Figure 3. Definition of Phase Acquisition Time
SERIAL DATA
1200 BITS OF 1–0 PATTERN
<2μs
FASTRACK
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= 3.0V to 3.6V, CF= 0.022µF, TA= -40°C to +85°C. Typical values are at VCC= 3.3V, 2.488Gbps, TA= +25°C, unless otherwise
noted.) (Note 4)
Note 1:At TA= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:CML outputs open.
Note 3:RL= 50Ωto VCC.
Note 4:AC characteristics are guaranteed by design and characterization.
Note 5:Relative to the falling edge of SCLKO+. See Figure 2.
Note 6:Measured with 223- 1 PRBS.
Note 7:Jitter BW = 12kHz to 20MHz.
Note 8:RATESET = low.
Note 9:RATESET = high.
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
RECOVERED CLOCK AND DATA
(2.488Gbps, 223 - 1 PATTERN,
VIN = 50mVP-P)MAX3873A toc01
125mV/div
100ps/div
RECOVERED CLOCK AND DATA
(2.67Gbps, 223 - 1 PATTERN,
VIN = 50mVP-P)MAX3873A toc02
125mV/div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)MAX3873A toc03
10ps/div
223 - 1 PATTERN
RMS = 2.0psRMS
0.1100100010,000
JITTER TOLERANCE
(2.488Gbps, 223 - 1 PATTERN,
VIN = 50mVP-P)MAX3873A toc04
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
BELLCORE
MASK
WITH 0.2UI OF PWD
WITH 0.4UI OF
DETERMINISTIC
JITTER
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
JITTER TRANSFER
MAX3873A toc05
FREQUENCY (Hz)
TRANSFER (dB)
BELLCORE
MASK
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO DISABLED)
MAX3873A
toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MED OUTPUT SWINGMAX OUTPUT SWING
MIN OUTPUT SWING
SUPPLY CURRENT vs. TEMPERATURE
(SCLKO ENABLED)
MAX3873A
toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MED OUTPUT SWINGMAX OUTPUT SWING
MIN OUTPUT SWING
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
Typical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
PULLIN RANGE (RATESET = 0)
MAX3873A toc08
AMBIENT TEMPERATURE (°C)
FREQUENCY (GHz)
BIT-ERROR RATIO
vs. INPUT AMPLITUDE
MAX3873A toc09
INPUT VOLTAGE (mVp-p)
BIT ERROR RATIO
JITTER TOLERANCE vs. INPUT
DETERMINISTIC JITTER
MAX3873A toc10
DETERMINISTIC JITTER (UIP-P)
SINUSOIDAL JITTER TOLERANCE (UI
P-P
fJITTER = 1MHz
fJITTER = 10MHz
PRBS = 223 - 10
JITTER TOLERANCE vs. PULSE-WIDTH
DISTORTION
MAX3873A toc11
INPUT PULSE-WIDTH DISTORTION (%)
SINUSOIDAL JITTER TOLERANCE (UI
P-PPRBS = 223 - 1fJITTER = 1MHz
fJITTER = 10MHz
INPUT DATA FILTERED BY
1870MHz 4TH-ORDER
BESSEL FILTER
PINNAMEFUNCTIONRATESETInput Rate Select. Connect to TTL low for 2.488Gbps data and to TTL high for 2.67Gbps data.
2, 5, 6VCC3.3V Supply VoltageSDI+Positive Serial Data InputSDI-Negative Serial Data InputFASTRACKPLL Fast Track Control, TTL Input. When FASTRACK is TTL high, the PLL is switched to a fast-
track mode for fast phase acquisition. When FASTRACK is TTL low, the PLL operates normally.VCC_VCO3.3V VCO Supply VoltageMODEOutput Amplitude Mode Select. MODE = open sets the CML output amplitude to high; MODE =
high sets the output amplitude to medium; MODE = low sets the output amplitude to low.
Pin Description
