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MAX3872ETJ+-MAX3872ETJ+T
Multirate Clock and Data Recovery with Limiting Amplifier
General DescriptionThe MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ωback termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
ApplicationsSONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
FeaturesMultirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)Reference Clock Not Required for Data
AcquisitionExceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications2.7mUIRMSJitter Generation10mVP-PInput Sensitivity Without Threshold
Adjust0.65UIP-PHigh-Frequency Jitter Tolerance±170mV Input Threshold Adjust Range
Clock Holdover Capability Using Frequency-
Selectable Reference ClockSerial Loopback Input Available for System
Diagnostic TestingLoss-of-Lock (LOL)Indicator
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
Ordering InformationSDI+
CAZ-CAZ+FREFSETVCC
CAZ
0.1μF
SDI-
SLBI-
SISLREFLOL
+3.3V
SYSTEM
LOOPBACK DATA
+3.3V
VCTRL
MAX3872
SLBI+
CML
CML
SDO+
SDO-
SCLKO-
CFIL
0.82μF
SCLKO+
RATESETRS2RS1GND
VREF
+3.3V+3.3V
VCC_VCOFIL
+3.3V
FILTER
GND
OUT+
OUT-
VCC
+3.3V
MAX3745
Typical Application Circuit19-2709; Rev 3; 2/07
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGEPKG
CODEMAX3872EGJ-40°C to +85°C32 QFN-EP*G3255-1
MAX3872ETJ+-40°C to +85°C32 TQFN-EP*T3255-3
*EP= Exposed pad.
+Denotes lead-free package.
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC= +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +5.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-)..........(VCC- 1.0V) to (VCC+ 0.5V)
Input Current Levels
(SDI+, SDI-, SLBI+, SLBI-)............................................±20mA
CML Output Current
(SDO+, SDO-, SCLKO+, SCLKO-)...............................±22mA
Voltage at LOL, LREF, SIS, FIL,
RATESET, FREFSET, RS1, RS2,
VCTRL, VREF, CAZ+, CAZ-......................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
32-Pin QFN (derate 21.3mW/°C above +85°C).........1384mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range.............................-55°C to +150°C
Processing Temperature (die).........................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSSupply CurrentICC(Note 2)175215mA
INPUT SPECIFICATIONS (SDI±, SLBI±)Single-Ended Input Voltage
RangeVISFigure 1VCC
- 0.8
VCC
+ 0.4V
Input Common-Mode VoltageFigure 1VCC
- 0.4VCCV
Input Termination to VCCRIN42.55057.5Ω
THRESHOLD-SETTING SPECIFICATIONS (SDI±)Differential Input Voltage Range
(SDI±)Threshold adjust enabled50600mVP-P
Threshold Adjustment RangeVTHFigure 2-170+170mV
Threshold Control VoltageVCTRLFigure 2 (Note 3)0.32.1V
Threshold Control Linearity±5%
Threshold Setting AccuracyFigure 2-18+18mV
15mV ≤ |VTH| ≤ 80mV-6+6Threshold Setting Stability80mV < |VTH| ≤ 170mV-12+12mV
Maximum Input CurrentICTRL-10+10µA
Reference Voltage OutputVREF2.142.22.24V
CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±)CML Differential Output Swing(Note 4)6008001000mVP-P
CML Differential Output
ImpedanceRO85100115Ω
CML Output Common-Mode
Voltage(Note 4)VCC
- 0.2V
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA = -40°C to +85°C. Typical values at VCC= +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL, LREF, RATESET, RS1, RS2, FREFSET)LVTTL Input High VoltageVIH2.0V
LVTTL Input Low VoltageVIL0.8V
LVTTL Input Current-10+10µA
LVTTL Output High VoltageVOHIOH = +20µA2.4V
LVTTL Output Low VoltageVOLIOL = -1mA0.4V
Note 1:At -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:CML outputs open.
Note 3:Voltage applied to VCTRLpin is from +0.3V to +2.1V when input threshold is adjusted from +170mV to -170mV.
Note 4:RL= 50Ωto VCC.
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC= +3.3V and TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITSSerial Input Data RateTable 2
Differential Input Voltage (SDI±)VIDThr eshol d ad j ust d i sab l ed , Fi g ur e 1 ( N ote 6) 101600mVP-P
Differential Input Voltage (SLBI±)BER ≤ 10-1050800mVP-P
OC-380130
OC-12370500Jitter Transfer BandwidthJBW
OC-4815002000
kHz
Jitter PeakingJPf ≤ JBW0.1dB
f = 100kHz3.18.0
f = 1MHz0.620.93Sinusoidal Jitter Tolerance
OC-48
f = 10MHz0.440.65
UIP-P
f = 25kHz2.98.3
f = 250kHz0. 591.03Sinusoidal Jitter Tolerance
OC-12
f = 2.5MHz0.420.63
UIP-P
f = 6.5kHz2.97.8
f = 65kHz0.591.05Sinusoidal Jitter Tolerance
OC-3
f = 650kHz0.420.64
UIP-P
f = 100kHz7.1
f = 1MHz0.82
Sinusoidal Jitter Tolerance with
Threshold Adjust Enabled
OC-48 (Note 7)f = 10MHz0.54
UIP-P
Jitter GenerationJGEN(Note 8)2.74.0mUIRMS
100kHz to 2.5GHz16Differential Input Return Loss
(SDI±, SLBI±)
-20log
| S11 |2.5GHz to 4.0GHz15dB
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC= +3.3V and TA = +25°C, unless otherwise noted.) (Note 5)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±)Output Edge Speedtr, tf20% to 80%110ps
CML Output Differential SwingRC = 100Ω differential6008001000mVP-P
Clock-to-Q DelaytCLK-Q(Note 9)-50+50ps
PLL ACQUISITION/LOCK SPECIFICATIONSTolerated Consecutive Identical
DigitsBER ≤ 10-102000bits
Acquisition TimeFigure 4 (Note 10)5.5ms
LOL Assert TimeFigure 42.3100.0µs
Low-Frequency Cutoff for
DC-Offset CancellationCAZ = 0.1µF4kHz
CLOCK HOLDOVER SPECIFICATIONSReference Clock FrequencyTable 3
Maximum VCO Frequency Drift(Note 11)400ppm
Note 5:AC characteristics are guaranteed by design and characterization.
Note 6:Jitter tolerance is guaranteed (BER ≤10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL
connected to VCC.
Note 7:Measured at OC-48 data rate using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4th-
order Bessel filter with f3dB= 1.8GHz).
Note 8:Measured with 10mVP-Pdifferential input, 223- 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz.
Note 9:Relative to the falling edge of the SCLKO+ (Figure 3).
Note 10:Measured using a 0.82µF loop-filter capacitor initialized to +3.6V.
Note 11:Measured at OC-48 data rate under LOLcondition with the CDR clock output set by the external reference clock.
(a) AC-COUPLED SINGLE-ENDED INPUT
(b) DC-COUPLED SINGLE-ENDED INPUT
5mV
5mV
800mV
800mV
VCC + 0.4V
VCC
VCC - 0.4V
VCC
VCC - 0.4V
VCC - 0.8V
Figure 1. Definition of Input Voltage Swing
THRESHOLD-
SETTING
ACCURACY
(PART-TO-PART
VARIATION OVER
PROCESS)
VCTRL (V)
VTH (mV)
+188
+170
+152
THRESHOLD-SETTING STABILITY
(OVERTEMPERATURE AND POWER SUPPLY)
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
Timing Diagrams
MAX3872
Multirate Clock and Data Recovery
with Limiting Amplifier
RECOVERED CLOCK AND DATA
(2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)MAX3872toc01
200mV/
div
100ps/div
RECOVERED CLOCK AND DATA
(2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)MAX3872toc02
200mV/
div
100ps/div
RECOVERED CLOCK JITTER
(2.488Gbps)MAX3872toc03
10ps/div
TOTAL WIDEBAND RMS JITTER = 1.60ps
RECOVERED CLOCK JITTER
(622.08Mbps)MAX3872toc04
10ps/div
TOTAL WIDEBAND RMS JITTER = 2.17ps
JITTER GENERATION
vs. POWER-SUPPLY WHITE NOISE
MAX3872toc05
WHITE-NOISE AMPLITUDE (mVRMS)
JITTER GENERATION (ps
RMS
OC-48
PRBS = 223 - 1
Typical Operating Characteristics(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
SCLKO+
SDO
tCLK
tCLK-Q
Figure 3. Definition of Clock-to-Q Delay
INPUT DATA
ACQUISITION TIME
DATADATA
LOL OUTPUT
LOL ASSERT TIME
Figure 4. LOLAssert Time and PLL Acquisition Time
Measurement
Timing Diagrams (continued)
