MAX3861ETG+ ,2.7Gbps Post Amp with Automatic Gain ControlApplications Ordering InformationOC-48/STM-16 Transmission SystemsTEMP PIN- PACKAGEPARTRANGE PACKAG ..
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MAX3861ETG+
2.7Gbps Post Amp with Automatic Gain Control
General DescriptionThe MAX3861 is a low-power amplifier with automatic
gain control (AGC), designed for WDM transmission
systems employing optical amplifiers and requiring a
vertical threshold adjustment after the post amp.
Operating from a single 3.3V supply, this AGC amplifier
linearly amplifies/attenuates the input signal while main-
taining a fixed output-voltage swing at data rates up to
2.7Gbps. The input and output are on-chip terminated
to match 50Ωinterfaces.
This amplifier has a small-signal bandwidth of 3.4GHz
and an input-referred noise of 0.26mVRMS. Over an
input signal range of 6mVP-Pto 1200mVP-P(46dB), the
MAX3861 delivers a constant output amplitude
adjustable from 400mVP-Pto 920mVP-P. Variation in
output swing is controlled within 0.2dB over a 16dB
input range. The MAX3861 provides a received-signal-
strength indicator (RSSI) that is linear, within 2.5%, for
input signal levels up to 100mVP-Pand an input signal
detect (SD) with programmable threshold.
ApplicationsOC-48/STM-16 Transmission Systems
WDM Optical Receivers
Long-Reach Optical Receivers
Continuous Rate Receivers
FeaturesSingle 3.3V Power Supply72mA Supply Current 3.4GHz Small-Signal Bandwidth0.26mVRMSInput-Referred Noise6mVP-Pto 1200mVP-PInput Range (46dB) Input Signal Detect with Programmable ThresholdRSSI (Linear Up to 100mVP-P)Adjustable Output Amplitude0.2dB Output Voltage Variation (Over 16dB Input
Signal Variation)
MAX3861
2.7Gbps Post Amp with Automatic Gain Control232221201989101112
CZ+CZ-GNDCD+CD-RSSI
REF
GND
CG+
CG-
GND
VCC
VCC
OSM
OUT+
OUT-
VCC
VCC
*NOTE: MAXIM RECOMMENDS SOLDERING THE EXPOSED PAD TO GROUND.
IN+
IN-
THIN QFN*TOP VIEW
MAX3861
Pin Configurations
Ordering Information19-2342; Rev 2; 2/05
PARTTEMP
RANGE
PIN-
PACKAGE
PACKAGE
CODEAX 3861E TG + - 40°C to + 85°C 24 Thi n Q FN - E P *T2444-3AX 3861E GG - 40°C to + 85°C 24 QFN-EP*G2444-1
EVALUATION KIT
AVAILABLECONTROLLED IMPEDANCE LINE
50Ω
MAX3861
50Ω
50Ω50Ω
MAXIM
2.7Gbps
TIA
MAXIM
MAX3873
CDR
RRSSI
50kΩ
RTH
1.8kΩ
CCZ
0.22µF
CCD
0.1µF
CCG
2200pF
ROSM
50kΩ
CZ+
CZ-
IN+
IN-
RSSIEN
CD+CG+
CG-
OUT+
OUT-
OSM
VREF
CD-
0.1µF
0.1µF
Typical Application Circuit+Denotes lead-free package.
*EP = Exposed pad.
Pin Configurations continued at end of data sheet.
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage......................................................-0.5V to +4.0V
Voltage at IN+, IN-..........................(VCC- 1.5V) to (VCC+ 0.5V)
Voltage at CZ+, CZ-, CG+,
CG-, CD+, CD-............................(VCC- 3.5V) to (VCC+ 0.5V)
Voltage at SC, SD, EN, TH,
OSM, VREF, RSSI....................................-0.5V to (VCC+ 0.5V)
CML Input Current at IN+, IN-.............................................25mA
CML Output Current at OUT+, OUT-..................................25mA
Continuous Power Dissipation TA= +85°C
(24-Pin QFN and 24-Pin Thin QFN)
(derate 20.8mW/°C above +85°C...................................1.35W
Storage Temperature Range.............................-55°C to +150°C
Operating Junction Temperature Range...........-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAt minimum gain7286RSSI and SD enabled
(Notes 2, 3)At maximum gain94112
At minimum gain5769Supply CurrentICC
RSSI and SD disabled
(Notes 2, 3)At maximum gain7894
VIN = 1000mVP-P35
Power-Supply Noise RejectionPSNR
VNOISE = 100mVP-P,
fNOISE ≤ 10MHz,
VSC = 2V (Note 4)VIN = 10mVP-P25
Input Data Rate2.7Gbps
Input ResistanceRINSingle-ended to VCC405060Ω
≤2.7GHz21Input Return Loss2.7GHz to 4.0GHz15dB
Input Common-Mode LevelVCC -
0.3VCCV
Input-Referred NoiseUp to 6GHz at max gain, CCZ = 0.1µF0.260.35mVRMS
Input Voltage RangeVINDifferential61200mVP-P
VSC = 0700Maximum Differential Input
Voltage for Linear Operation0.9 ≤ linearity ≤ 1.1VSC = 2V650mVP-P
Output ResistanceROUTSingle-ended to VCC405060Ω
≤2.7GHz16Output Return Loss2.7GHz to 4.0GHz11dB
VSC = 0VCC -
0.13Output Common-Mode LevelRL = 50Ω to VCC
VSC = 2VVCC -
6mVP-P ≤ VIN ≤
700mVP-P±3±14VSC = 0,
RL = 50Ω to VCC
(Note 5)700mVP-P ≤ VIN ≤
1200mVP-P±8
6mVP-P ≤ VIN ≤
700mVP-P±5.5±28
Maximum Differential Output
Offset
VSC = 2V,
RL = 50Ω to VCC
(Note 5)700mVP-P ≤ VIN ≤
1200mVP-P±11
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Note 1)
Note 1:Electrical characteristics are measured or characterized using a 223- 1PRBS at 2.7Gbps with input edge speeds ≤200ps,
unless otherwise noted. All AC specifications are guaranteed by design and characterization, unless otherwise noted.
Note 2:Supply current measurement is taken with AC-coupled inputs and excludes output currents into 50Ωloads.
Note 3:Minimum gain is defined as VIN= 1200mVP-Pand VOUT= 400mVP-P. Maximum gain is defined as VIN= 6mVP-P, and
VOUT= 920mVP-P. Reference gain is measured at 100MHz.
Note 4:Power-supply noise rejection is characterized with a 2.7Gbps 1100 pattern on the input. It is calculated by the equation
PSNR = 20log(∆VCC/ (∆VOUT)), where ∆VOUTis the change in differential output voltage because of power-supply noise.
See the Power-Supply Noise Rejection vs. Frequency graph in the Typical Operating Characteristics.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVSC = 0300400500Differential Output AmplitudeVOUTRL = 50Ω to VCC
(Note 6)VSC = 2V7609201050mVP-P
Output Amplitude VariationΔVOUTVIN ≥ 6mVP-P, RL = 50Ω to VCC (Notes 6, 7)0.21.0dB
At minimum gain2.53.45.5Small Signal BandwidthBW(Note 3)At maximum gain2.22.94.3GHz
Low-Frequency CutoffCCZ = 0.1µF7.613kHz
Deterministic Jitter(Note 8)1550psP-P
VOUT = 920mVP-P2.0
Output Signal Monitor VoltageVOSMROSM ≥ 2kΩ
(Note 6)VOUT = 400mVP-P0.9V
Output Signal Monitor Linearity0V ≤ VSC ≤ 2V (Note 6)1.0%
SC Input Range(Note 9)02.0V
AGC Loop ConstantWithout external capacitor CCG,
VSC = 0 (Note 10)16µs
VIN = 2mVP-P55
RSSI Output VoltageRSSI
RRSSI ≥ 2kΩ,
VSC = 0
(Note 6)VIN = 100mVP-P1800
2mVP-P ≤ VIN ≤ 100mVP-P (Note 14)±2.5±12RSSI Linearity6mVP-P ≤ VIN ≤ 100mVP-P±2.5±8%
Minimum SD Assert Input2mVP-P
Maximum SD Assert Input100mVP-P
SD Assert Time1070µs
SD Deassert TimeCG+ and CG- are open (Note 11)1044µs
SD Accuracy(Note 12)±10%
10mVP-P ≤ VIN ≤ 100mVP-P2.84.56.3SD Hysteresis2mVP-P ≤ VIN ≤ 10mVP-P (Note 13)4.5dB
SD Output High VoltageSourcing 20µA current2.4V
SD Output Low VoltageSinking 2mA current0.44V
EN Input Low VoltageVIL0.8V
EN Input High VoltageVIH2.0V
EN Input Low CurrentIILVIL = 010µA
EN Input High CurrentIIHVIH = 2.0V10µA
VREF Output VoltageRVREF ≥ 40kΩ2.0V
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
Typical Operating Characteristics(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
OUTPUT AMPLITUDE
vs. INPUT AMPLITUDE
MAX3861 toc01
INPUT AMPLITUDE (mVP-P)
OUTPUT AMPLITUDE (mV
P-P
VSC = 2.0V
VSC = GND
223 - 1PRBS AT 2.7Gbps
DISTRIBUTION OF SD HYSTERESIS
(WORST-CASE CONDITIONS)MAX3861 toc02
SD HYSTERESIS (dB)
PERCENT OF UNITS (%)
VCC = 3.0V
VSC = 2.0V
VIN = 2mVP-P
TA = -40°C
MEAN = 4.52dB
σ = 0.79dB
DETERMINISTIC JITTER
vs. INPUT AMPLITUDEMAX3861 toc03
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER (ps
P-P
10001001010,000
SUPPLY CURRENT vs. TEMPERATURE
MAX3861 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
EN = VCC
EN = GND
EXCLUDES OUTPUT
LOAD CURRENTS
VIN = 1200mVP-P
VSC = 0
76ps/div
EYE DIAGRAM, MINIMUM INPUTMAX3861 toc05
VIN = 6mVP-P
223 - 1PRBS
76ps/div
MAX3861 toc06
VIN = 1200mVP-P
223 - 1PRBS
EYE DIAGRAM, MAXIMUM INPUT
Note 5:See the Distribution of Differential Output Offset (Worst-Case Conditions) graph in the Typical Operating Characteristics.
Note 6:Characterized with a 675Mbps 1-0 pattern.
Note 7:Measurements are taken over an input signal range of 16dB.
Note 8:Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).
Deterministic jitter is the difference between total jitter and random jitter, with system jitter calibrated out. It is measured
with a 27- 1PRBS, and 80CIDs with DC-coupled outputs.
Note 9:Thetypical input resistance of the SC pin is 40kΩ.
Note 10:AGC loop time constant is measured with a 20dB change in the input and VSCheld constant. With an external capacitor
CCGof 0.022µF connected between CG+ and CG-, a typical AGC loop time constant of 760µs is achieved.
Note 11:SD deassert time depends on the AGC loop time constant set by CCG.
Note 12:SD accuracy is defined as the part-to-part variation of the SD threshold at a fixed RTHvalue.
Note 13:See the Distribution of SD Hysteresis (Worst-Case Conditions) graph in the Typical Operating Characteristics.
Note 14:Measurements are taken over an input signal range of 20dB.
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Note 1)
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
|S11| vs. FREQUENCYMAX3861 toc10
FREQUENCY (Hz)
| (dB)100M
50M10G
MEASURED ON
EVALUATION BOARD
DISTRIBUTION OF DIFFERENTIAL
OUTPUT OFFSET (WORST-CASE CONDITIONS)MAX3861 toctoc13
DIFFERENTIAL OUTPUT OFFSET (mV)
PERCENT OF UNITS (%)6420-2-4-6-8
VCC = 3.6V
VSC = 0V
VIN = 700mVP-P
TA = -40°C
OUTPUT SIGNAL AMPLITUDE
vs. SC PIN VOLTAGE (VIN = 1.0VP-P)
MAX3861 toc11
VSC (V)
OUT
(mV
P-P
RSSI OUTPUT vs. INPUT AMPLITUDE
MAX3861 toc12
INPUT AMPLITUDE (mVP-P)
RSSI OUTPUT (V)
223 - 1PRBS
ypical Operating Characteristics (continued)(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
POWER-SUPPLY NOISE REJECTION
vs. FREQUENCYMAX3861 toc07
FREQUENCY (Hz)
POWER-SUPPLY NOISE REJECTION (dB)100k10k10M
VIN = 1000mVP-P
VIN = 10mVP-P
|S22| vs. FREQUENCYMAX3861 toc08
FREQUENCY (Hz)
| (dB)100M
50M10G
MEASURED ON
EVALUATION BOARD
SIGNAL DETECT THRESHOLD vs. RTHMAX3861 toc09
RTH (Ω)
SD ASSERT THRESHOLD (mV
P-P
10,0001000
100,000100
DISTRIBUTION OF DIFFERENTIAL
OUTPUT OFFSET (WORST-CASE CONDITIONS)
MAX3861 toc14
DIFFERENTIAL OUTPUT OFFSET (mV)
PERCENT OF UNITS (%)812-8-404-12
VCC = 3.6V
VSC = 2.0V
VIN = 700mVP-P
TA = -40°C
MAX3861
2.7Gbps Post Amp with Automatic Gain Control
Pin Description
PINNAMEFUNCTION1TH
Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to
program the input signal detect assert threshold. Leaving this pin open sets the signal detect
threshold to its absolute minimum value (<2mVP-P). See the Design Procedure section.
2, 5, 14, 17VCCSupply Voltage Connection. Connect all VCC pins to the board VCC plane.IN+Positive CML Signal Input with On-Chip Termination ResistorIN-Negative CML Signal Input with On-Chip Termination Resistor
6ENSignal Detect Enable. Set high (≥2.0V) or leave open to enable the input signal detection (RSSI and
SD) circuitry. Set low (≤0.4V) to power down the input signal detection circuitry.
7VREFReference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing.
8SCOutput Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or
connect SC directly to VREF for maximum output amplitude.
9, 12, 22GNDGround. Connect all GND pins to the board ground plane.CG+Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.CG-Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC
loop time constant.OSMOutput Signal Monitor. This DC signal is linearly proportional to the output signal amplitude.OUT-Negative CML Data Output with On-Chip Back-Termination ResistorOUT+Positive CML Data Output with On-Chip Back-Termination ResistorSDInput Signal Detect. Asserts logic low when the input signal level drops below the programmed
threshold.RSSIReceived Signal Strength Indicator. Outputs a DC signal linearly proportional to the input signal
amplitude.CD-
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.CD+
Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the
offset-cancellation loop time constant of the input signal detection. See the Detailed Description
section.CZ-
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.CZ+
Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZ-
sets the offset-cancellation loop time constant of the main signal path. See the Detailed Description
section.Exposed PadMaxim recommends connecting the exposed pad to board ground.
Detailed DescriptionFigure 1 is a functional diagram of the MAX3861 auto-
matic gain-control amplifier. The MAX3861 is divided
into three sections: main signal path, input signal
detection, and output signal detection.
Main Signal PathThe main signal path consists of variable gain ampli-
fiers with CML output levels and an offset-cancellation
loop. This configuration allows for overall gains from
-9.5dB to 43.5dB.
Offset-Cancellation LoopThe offset-cancellation loop partially reduces additional
offset at the input. In communications systems using
NRZ data with a 50% duty cycle, pulse-width distortion
present in the signal or generated by the transimped-
ance amplifier appears as input offset and is partially
removed by the offset-cancellation loop. An external
capacitor is required between CZ+ and CZ- to com-
pensate the offset-cancellation loop and determine the
lower 3dB frequency of the signal path.
Input Signal Detection and
SD CircuitryThe input signal detection circuitry consists of variable
gain amplifiers and threshold voltages. Input signal
detection information is compared to an internal refer-
ence and creates the RSSI voltage and an internal ref-
erence signal. The signal detect (SD) circuitry indicates
when the input signal is below the programmed thresh-
old by comparing a voltage proportional to the RSSI
signal with internally generated control voltages. The
SD threshold is set by a control voltage developed
across the external TH resistor (RTH). Two control volt-
ages, VASSERTand VDEASSERT, define the signal
detect assert and deassert levels. To prevent SD chat-
ter in the region of the programmed threshold, 2.8dB to
6.3dB of hysteresis is built into the SD assert/deassert
function. Thus, once asserted, SD is not deasserted
until sufficient gain is retained. When input signal
detection (SD and RSSI) is not required, connect EN to
a TTL low to power down this circuitry.
Output Signal Monitor and
Amplitude ControlOutput amplitude typically can be adjusted from
400mVP-Pto 920mVP-Pby applying a control voltage
(0V to 2.0V) to the SC pin. See the Output Signal
Amplitude vs. SC Pin Voltage graph in the Typical
Operating Characteristics. Connect the VREFpin (2.0V)
to the SC pin for maximum output amplitude. The output
signal monitor pin provides a DC voltage linearly pro-
portional to the output signal.
Design Procedure
Program the SD ThresholdThe SD threshold is programmed by an external resis-
tor, RTH, between the range of 2mVP-Pto 100mVP-P.
The circuit is designed to have approximately 4.5dB of
hysteresis over the full range. See the Signal Detect
Threshold vs. RTHgraph in the Typical Operating
Characteristicsfor proper sizing.
MAX3861
2.7Gbps Post Amp with Automatic Gain ControlVCC
MAIN SIGNAL PATH
CONTROL
BLOCK
AND
OUTPUT
SIGNAL
DETECT
INPUT SIGNAL DETECT
CZ+CZ-
OUT+
OUT-
OSM
VREF
CG+
CG-
SD CIRCUITRY
GND
RTHEN
CD-
RSSI
CD+
IN-
IN+
MAX3861
Figure 1. Functional Diagram
