MAX3841ETG+ ,12.5Gbps, CML, 2 x 2 Crosspoint Switchapplications.♦ +3.3V Core SupplyThe MAX3841 has 150mV minimum differential inputP-Psensitivity, and ..
MAX3845UCQ+D ,DVI/HDMI 2:4 TMDS Fanout Switch and Cable DriverELECTRICAL CHARACTERISTICS(V = 3.0V to +3.6V, T = -10°C to +85°C. Typical values are at V = +3.3V, ..
MAX384CPN ,Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers with Latchable InputsFeaturesThe MAX382/MAX384 are low-voltage, CMOS, 1-of-8' Pin-Compatible with Industry-Standardand d ..
MAX384CWN ,Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers with Latchable InputsELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = V = 2.4V, V = ..
MAX3850EGJ ,+3.3 V, 2.7 Gbps, DC-coupled laser driverApplications*Dice are designed to operate over this range, but are testedSDH/SONET Transmission Add ..
MAX385CSE ,Precision, Low-Voltage Analog SwitchesGeneral Description ________
MAX7405EPA ,8th-Order, Lowpass, Bessel, Switched-Capacitor FiltersApplicationsPART TEMP. RANGE PIN-PACKAGEADC Anti-Aliasing CT2 Base StationsMAX7401CSA 0°C to +70°C ..
MAX7405ESA ,8th-Order, Lowpass, Bessel, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7401 (continued)(V = +5V, filter output measured at OUT, 10kΩ || 50pF ..
MAX7408EUA ,5th-Order, Lowpass, Elliptic, Switched-Capacitor FiltersApplicationsMAX7408EPA -40°C to +85°C 8 Plastic DIPADC Anti-Aliasing CT2 Base StationsMAX7408EUA -4 ..
MAX7408EUA+T ,5th Order, Lowpass, Elliptic, Switched-Capacitor FiltersApplicationsMAX7408EPA -40°C to +85°C 8 Plastic DIPADC Anti-Aliasing CT2 Base StationsMAX7408EUA -4 ..
MAX7409CUA ,5th-Order, Lowpass, Switched-Capacitor Filtersapplications. They feature a+5V (MAX7409/MAX7410)shutdown mode, which reduces the supply current to ..
MAX7409EPA ,5th-Order, Lowpass, Switched-Capacitor FiltersELECTRICAL CHARACTERISTICS—MAX7409/MAX7410(V = +5V, filter output measured at OUT, 10kΩ || 50pF loa ..
MAX3841ETG+
12.5Gbps, CML, 2 x 2 Crosspoint Switch
General DescriptionThe MAX3841 is a low-power, 12.5Gbps 2 ×2 cross-
point switch IC for high-speed serial data loopback,
redundancy, and switching applications. The MAX3841
current-mode logic (CML) inputs and outputs have iso-
lated VCCconnections to enable DC-coupled interfaces
to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal
paths and Maxim’s second-generation SiGe technology
provide optimum signal integrity, minimizing jitter,
crosstalk, and signal skew. The MAX3841 is ideal for
serial OC-192 and 10GbE optical module, line card,
switch fabric, and similar applications.
The MAX3841 has 150mVP-Pminimum differential input
sensitivity, and 500mVP-Pnominal differential output
swing. Unused outputs can be powered down individu-
ally to conserve power. In addition to functioning as a 22 switch, the MAX3841 can be configured as a 2:1
multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841
is available in a 4mm ×4mm 24-pin thin QFN package,
and consumes only 215mW with both outputs enabled.
ApplicationsOC-192, 10GbE Switch/Line Cards
OC-192, 10GbE Optical Modules
System Redundancy/Self Test
Clock Fanout
FeaturesUp to 12.5Gbps OperationLess Than 10psP-PDeterministic JitterLess Than 0.7psRMSRandom Jitter1.8V, 2.5V, and 3.3V DC-Coupled CML I/OIndependent Output Power-Down4mm ×4mm Thin QFN Package-40°C to +85°C Operation+3.3V Core Supply215mW Power Consumption (Excluding
Termination Currents)
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch
Ordering InformationMAX3841
10Gbps
SERIAL
OPTICAL
MODULE
SDI+
SDI-
SDO+
SDO-
OUT1+
OUT1-
IN1+
IN1-
SEL1SEL2ENO1ENO2
LOOPBACK
3.3V
VCCVCC1OUT
VCC1IN
2.5V
2.5V
2.5V
IN2+
IN2-
OUT2+
OUT2-
SDO+
SDO-
SDI+
SDI-
VCC2IN
VCC2OUT
1.8V
1.8V
GND
10Gbps
CDR/SERDES
ASIC
3.3V
1.8V
Typical Application Circuit19-2905; Rev 1; 3/09
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX3841ETG -40°C to +85°C 24 Thin QFN-EP*
MAX3841ETG+ -40°C to +85°C 24 Thin QFN-EP*
Pin Configuration appears at end of data sheet.+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, VCC_IN = +1.71V to VCC, VCC_OUT = +1.71V to VCC, TA= -40°C to +85°C. Typical values are at VCC=
+3.3V, VCC_IN = VCC_OUT = 1.8V, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:Guaranteed by design and characterization.
Note 2:Differential swing is defined as VIN= (IN_+) - (IN_-) and VOUT= (OUT_+) - (OUT_-). See Figure 1.
Note 3:Measured using a 0000011111 pattern at 12.5Gbps, and VIN= 400mVP-Pdifferential.
Note 4:Measured at 9.953Gbps using a pattern of 100 ones, 27 - 1 PRBS, 100 zeros, 27 - 1 PRBS, and at 12.5Gbps using a ±K28.5
pattern. VCC_IN = VCC_OUT = 1.8V, and VIN = 400mVP-Pdifferential.
Note 5:Refer to Application Note 1181:HFAN-04.5.1: Measuring Random Jitter on a Digital Sampling Oscilloscope.
Supply Voltage, VCC..............................................-0.5V to +4.0V
CML Supply Voltage (VCC_IN, VCC_OUT)...........-0.5V to +4.0V
Continuous Output Current (OUT1±, OUT2±)...................±25mA
CML Input Voltage (IN1±, IN2±)...........-0.5V to (VCC_IN + 0.5V)
LVCMOS Input Voltage (SEL1, SEL2,
ENO1, ENO2).........................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
24-Pin Thin QFN (derate 20.8mW/°C
above +85°C).............................................................1352mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCore Supply Current ICC Excluding CML termination currents 65 90mA
Data Rate (Note 1) 0 12.5 Gbps
CML Input Differential VIN AC-coupled or DC-coupled (Note 2) 150 1200 mVP-P
CML Input Common Mode DC-coupled VCC_IN - 0.3 VCC_IN V
CML Input Termination Single ended 42.5 50 57.5
CML Input Return Loss Up to 10GHz 12 dB
CML Output Differential VOUT (Note 2) 400 500 600 mVP-P
CML Output Termination Single ended 42.5 5057.5
CML Output Transition Time tR, tF 20% to 80% (Notes 1, 3) 30 ps
Deterministic Jitter (Notes 1, 4) 10 psP-P
Random Jitter VIN = 150mVP-P (Notes 1, 5) 0.3 0.7 psRMS
Propagation Delay Any input to output (Note 1) 100 140ps
Channel-to-Channel Skew (Note 1) 12 ps
Output Duty-Cycle Skew 50% input duty cycle (Notes 1, 3) 8 ps
LVCMOS Input Current IIH, IIL -10 +10 μA
LVCMOS Input High Voltage VIH 1.7 V
LVCMOS Input Low Voltage VIL 0.7 V
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch
Typical Operating Characteristics(VCC= 3.3V, VCC_IN, VCC_OUT = 1.8V, VIN= 500mVP-P, TA= +25°C, unless otherwise noted.)
CORE SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES CML I/O CURRENTS)MAX3841 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
0 OUTPUTS ENABLE
2 OUTPUTS ENABLE
1 OUTPUT ENABLE
SUPPLY CURRENT vs. TEMPERATURE
(CORE PLUS CML I/O CURRENTS)MAX3841 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
0 OUTPUTS ENABLE
2 OUTPUTS ENABLE
1 OUTPUT ENABLE
CML INPUTS AND OUTPUTS AC-COUPLED
OUTPUT EYE DIAGRAM
(12.5Gbps, 223 - 1 PRBS)MAX3841 toc03
14ps/div
60mV/div
OUTPUT EYE DIAGRAM
(10.7Gbps, 223 - 1 PRBS)MAX3841 toc04
16ps/div
60mV/div
OUTPUT EYE DIAGRAM
(6.25Gbps, 223 - 1 PRBS)MAX3841 toc05
28ps/div
60mV/div
OUTPUT EYE DIAGRAM
(622Mbps, 223 - 1 PRBS)MAX3841 toc06
270ps/div
60mV/div
DETERMINISTIC JITTER
vs. TEMPERATUREMAX3841 toc07
TEMPERATURE (°C)
DETERMINISTIC JITTER (ps)35-1510
-40857 - 1 PRBS + 100CIDs
AT 10.7Gbps
±K28.5 AT 12.5Gbps
DIFFERENTIAL OUTPUT SWING
vs. TEMPERATUREMAX3841 toc08
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT (mV
P-P3510-15
PROPAGATION DELAY
MAX3841 toc09
100ps/div
OUT1
IN1
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch
Pin Description
PINNAMEFUNCTION1, 12 VCC +3.3V Core Supply Voltage
2, 5 VCC1IN Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V. IN1+ Positive Serial Data Input 1, CML IN1- Negative Serial Data Input 1, CML SEL1 Output 1 Select, LVCMOS Input. See Table 1. SEL2 Output 2 Select, LVCMOS Input. See Table 1.
8, 11 VCC2IN Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V.IN2+ Positive Serial Data Input 2, CML
10 IN2- Negative Serial Data Input 2, CML
13, 24 GND Supply Ground
14, 17 VCC1OUT Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V.
15 OUT1- Negative Serial Data Output 1, CML
16 OUT1+ Positive Serial Data Output 1, CML
18 ENO1 Output 1 Enable, LVCMOS Input. See Table 1.
19 ENO2 Output 2 Enable, LVCMOS Input. See Table 1.
20, 23 VCC2OUT Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V.
21 OUT2- Negative Serial Data Output 2, CML
22 OUT2+ Positive Serial Data Output 2, CML
— EP Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
Detailed DescriptionThe MAX3841 contains a pair of CML inputs that drive
two 2:1 multiplexers, with separate select inputs SEL1
and SEL2, providing a 2 ×2 crosspoint data path. The
outputs of the multiplexers each drive a high-perfor-
mance CML output that can be disabled (powered
down) using the ENO1/ENO2 inputs. All of the data
paths are fully differential to minimize jitter, crosstalk,
and signal skew. See Figure 1 for the functional diagram.
CML Input and Output BuffersThe MAX3841 input and output buffers are terminated
with 50Ωto independent supply lines, and are also com-
patible with 100Ωdifferential terminations. (See Figures 3
and 4.) Separate power-supply connections are provided
for the core, input buffers, and output buffers to allow DC-
coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the
CML inputs and outputs can be AC-coupled.
The CML inputs accept serial NRZ data with differential
amplitude from 150mVP-Pto 1200mVP-P(see Figure 2).
The CML outputs provide 500mVP-Pnominal differential
swing, resulting in low power consumption.
MAX3841
CML
CML
CML
CML
OUT1
ENO1
SEL1
OUT2
ENO2
SEL2
IN1
IN2
Figure 1. Functional Diagram
Applications Information
Select and Enable ControlsThe MAX3841 provides two LVCMOS-compatible
select inputs, SEL1 and SEL2. Either data input can be
connected to either or both data outputs. The MAX3841
provides two LVCMOS-compatible enable inputs,
ENO1 and ENO2, so each output can be disabled
independently. The MAX3841 can also be used as a
1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using
the LVCMOS control inputs accordingly (see Table 1).
Power-Supply ConnectionsEach of the input and output power-supply connections
(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-
dent and need not be connected to the same voltage.
The input and output supplies can be connected to
1.8V, 2.5V, or 3.3V, but the core supply (VCC) must be
connected to 3.3V for proper operation.
Input and Output InterfacesThe MAX3841 inputs and outputs can be AC-coupled
or DC-coupled according to the application. If an input
or output is not used it should be terminated with 50Ω
to the correct input or output supply voltage. For more
information about interfacing with logic families, refer to
Application Note 291:HFAN-01.0: Introduction to
LVDS, PECL, and CML.
Package and Layout ConsiderationsThe MAX3841 is packaged in a 4mm ×4mm 24-pin thin
QFN with exposed pad. The exposed pad provides
thermal and electrical connectivity to the IC and must
be soldered to a high-frequency ground plane. Use
multiple vias to connect the exposed pad underneath
the package to the PC board ground plane.
Use good layout techniques for the 10Gbps PC board
transmission lines, and configure the layout near the IC to
minimize impedance discontinuities. Power-supply
decoupling capacitors should be located as close as
possible to the IC.
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch(V+) - (V-)1200mV
MAX
600mV
MAX
75mV
MIN
150mV
MIN
Figure 2. Definition of Differential Voltage Swing
MAX3841
50Ω50Ω
VCC_IN
IN_+
IN_-
MAX3841
50Ω50Ω
VCC_OUT
OUT_+
OUT_-
Figure 3. Equivalent CML Input Circuit
Table 1. Output Controls
ENO1ENO2SEL1SEL2OUT1OUT20 0 0 0 IN2 IN1
0 0 0 1 IN2 IN2
0 0 1 0 IN1 IN1
0 0 1 1 IN1 IN2
1 1 X X Disabled Disabled
MAX3841
12.5Gbps CML 2 ×2 Crosspoint Switch
Chip InformationTRANSISTOR COUNT: 950
PROCESS: SiGe BiCMOSVCCVCC1ININ1+IN1-VCC1INSEL1
SEL2
VCC2IN
IN2+
IN2-
VCC2INGNDVCC1OUTOUT1-OUT1+VCC1OUTENO1
ENO2
VCC2OUT
OUT2-
OUT2+
VCC2OUT
GND
MAX3841
THIN QFN*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE
SOLDERED TO GROUND FOR PROPER THERMAL AND
ELECTRICAL OPERATION.
TOP VIEW
*EP
Pin Configuration
Package InformationFor the latest package outline information and land patterns, go
to /packages.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.24 TQFN-EPT2444-3
21-0139
