MAX3804ETE+ ,12.5Gbps Settable Receive EqualizerFeaturesThe MAX3804 driver with integrated analog equalizer Compensates Up to 30in (0.75m) of 6-mi ..
MAX3812USA ,Multirate SMPTE SD/HD Cable Driver with Selectable Slew RateApplications♦ 0°C to +85°C Operating Temperature RangeSMPTE 292M, SMPTE 344M, SMPTE 259M, andDVB-AS ..
MAX3814CHJ+T ,DVI/HDMI TMDS FR-4 and Cable Equalizer/DriverFeaturesThe MAX3814 TMDS™ EQ/driver IC compensates for ♦ Equalizes FR-4 Board Microstrip and Cable ..
MAX3815CCM+TD ,TMDS Digital Video Equalizer for DVI/HDMI CablesELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +70°C. Typical Values are at V = +3.3V, e ..
MAX3816ACUE+ ,I²C 2-Wire Extender for DDC in DVI, HDMI, and VGA InterfacesApplicationsFront-Projector DVI/HDMI InputsPART TEMP RANGE PIN-PACKAGE High-Definition Televisions, ..
MAX381CPE ,Precision, Low-Voltage Analog SwitchesMAX381/MAX383/MAX38519-0300; Rev 0; 9/94Precision, Low-Voltage Analog Switches_______________
MAX738AEWE ,5V / Step-Down / Current-Mode PWM DC-DC ConvertersMAX730A/MAX738A/MAX744A19-0165; Rev 2; 1/965V, Step-Down,Current-Mode PWM DC-DC Converters_________ ..
MAX739CPD ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorslVI/lXI/VI
-5V, -12V, -15V, and Adjustable
Inverting Gurrent-Mode PWM Regulators
MAX739CWE ,-5V,-12V,-15V, and Adjustable Inverting Current-Mode PWM RegulatorsGeneral Description
The MAX736/MAX737/MAX739/MAX759 are CMOS, in-
verting, switch-mode regulato ..
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. Pre-Set -5V, -12V, -15V or Adjustable Outputs
. Convert Positive Voltages to Negative
..
MAX7400CSA ,8th-Order, Lowpass, Elliptic, Switched-Capacitor Filtersapplications. They fea-' Single-Supply Operationture a shutdown mode that reduces the supply curren ..
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MAX3804ETE+
12.5Gbps Settable Receive Equalizer
General DescriptionThe MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter-
symbol interference. The MAX3804 can extend the practi-
cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal-
ization for 10.7Gbps signals is typically 24psP-Pon the
maximum path length.
The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm ✕3mm package affords optimal placement and
routing flexibility. It has separate VCCconnections for
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso-
lated supplies, providing independent DC-coupled inter-
facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con-
trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per-
formance over a wide range of data rates and formats.
ApplicationsOC-192 and 10Gb Ethernet Switches and Routers
OC-192 and 10Gb Ethernet Serial Modules
High-Speed Signal Distribution
FeaturesCompensates Up to 30in (0.75m) of 6-mil FR-4
Transmission Line Loss115mW Operating PowerUp to 12.5Gbps Data RateCompatible with 8B10B, 64B66B, and PRBS DataLess than 30psP-PResidual Jitter After
Equalization3-Bit Equalization Level Select Input3mm x 3mm Thin QFN PackageDC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O-40°C to +85°C Operation+3.3V Core Supply Voltage
MAX3804
Ordering Information
Typical Operating Circuit19-2713; Rev 1; 11/03
Pin Configuration appears at end of data sheet.
MAX3804
12.5Gbps Settable Receive Equalizer
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, VCC1= VCC2= +1.65V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC = VCC1= VCC2= +3.3V,
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCC)............................................-0.5V to +4.0V
CML Supply Voltage (VCC1, VCC2)............-0.5V to (VCC+ 0.5V)
Current at Serial Output (SDO+, SDO-)............................±25mA
Input Voltage (SDI+, SDI-, EQ1,
EQ2, EQ3)..............................................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
16-Lead Thin QFN-EP (derate 17.5mW/°C
above +85°C) ........................................................1398mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Note 1:Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z0= 100Ω, 6-mil
microstrip in FR-4, εr=4.5, and tanδ=0.02, VIN= (SDI+ - SDI-).
Note 2:Measured with 0000011111 pattern at 12.5Gbps.
Note 3:Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-
sion line) and equalizer output. Total residual jitter is DJP-P+ 14.2 x RJRMS.
Note 4:Measured at 10.7Gbps using a pattern of 100 ones, 27PRBS, 100 zeros, 27PRBS, and at 12.5Gbps using a K28.5 pattern.
Deterministic jitter at the input is from frequency-dependent, media-induced loss only.
Note 5:VIN= 400mVP-P to 1200mVP-P, input path is 0 to 30in, 6-mil microstrip in FR-4, εr=4.5, and tanδ=0.02.
Note 6:Guaranteed by design and characterization.
MAX3804
12.5Gbps Settable Receive Equalizer
SUPPLY CURRENT vs. TEMPERATUREMAX3804 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
RESIDUAL JITTER
vs. INPUT AMPLITUDE
MAX3804 toc02
INPUT AMPLITUDE (mVP-P)
RESIDUAL JITTER (ps
P-P
RESIDUAL JITTER
vs. FR-4 PATH LENGTH
MAX3804 toc03
FR-4 PATH LENGTH (in)
RESIDUAL JITTER (ps
P-P159
RESIDUAL JITTER
vs. EQUALIZATION SETTING
MAX3804 toc04
EQUALIZATION SETTING (EQ3, EQ2, EQ1)
RESIDUAL JITTER (ps
P-P
EQUALIZER OUTPUT EYE AFTER 18in OF FR-47PRBS WITH 100 CIDs AT 10.7Gbps)
MAX3804 toc05
16ps/div
60mV/
div
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX3804
12.5Gbps Settable Receive Equalizerypical Operating Characteristics (continued)(TA = +25°C, unless otherwise noted.)
MAX3804
12.5Gbps Settable Receive Equalizer
Detailed Description
General Theory of OperationThe MAX3804’s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).
CML Input and Output BuffersThe MAX3804 input and output CML buffers are termi-
nated with 50Ωto VCC1and VCC2, respectively. The
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (VCC), input (VCC1), and output (VCC2) circuit-
ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.
Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50Ωtermination.
The low-frequency cutoff of the input-stage offset-can-
cellation circuit is nominally 21kHz.
