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MAX3761EEP+ |MAX3761EEPMAXN/a500avaiLow-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3762EEP+ |MAX3762EEPMAXIMN/a81avaiLow-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3762EEP+T |MAX3762EEPTMAXIMN/a10000avaiLow-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
MAX3762EEP+TMAXN/a5000avaiLow-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs


MAX3762EEP+T ,Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANsapplications. ♦♦ PECL Data OutputsAn integrated power detector senses the input signal’samplitude. ..
MAX3762EEP+T ,Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANsELECTRICAL CHARACTERISTICS(V = +4.5V to +5.5V, DISABLE = low, T = -40°C to +85°C, unless otherwise ..
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MAX3761EEP+-MAX3762EEP+-MAX3762EEP+T
Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
_______________General Description
The MAX3761/MAX3762 limiting amplifiers, with 4mV
sensitivity and PECL data outputs, are optimized for
operation in low-cost, 622Mbps, LAN/ATM LAN fiber
optics applications.
An integrated power detector senses the input signal’s
amplitude. A received-signal-strength indicator (RSSI)
gives an analog indication of the power level, while the
complementary loss-of-signal (LOS) outputs indicate if
the input power level exceeds the programmed
threshold level. The LOS threshold can be adjusted to
detect signal amplitudes between 3mVp-p and
100mVp-p, providing a 15dB LOS adjustment in fiber
optic receivers. The LOS outputs have 3.5dB of
hysteresis, which prevents chatter when input signal
levels are small. The MAX3761’s LOS outputs are com-
patible with TTL-logic levels. The MAX3762 has PECL
LOS outputs.
DISABLE and LOS can be used to implement a squelch
function, which turns off the data outputs when the
input signal is below the programmed threshold.
________________________Applications

622Mbps LAN/ATM LAN Receivers
155Mbps LAN/ATM LAN Receivers
____________________________Features
Chatter-Free Power Detector with Programmable
Loss-of-Signal Outputs
4mV Input SensitivityPECL Data OutputsSingle 5V Power Supply250ps Output Edge SpeedLow 15ps Pulse-Width DistortionTTL Loss-of-Signal Interface Logic—MAX3761PECL Loss-of-Signal Interface Logic—MAX3762
MAX3761/MAX3762
Low-Power, 622Mbps LimitingAmplifiers
with Chatter-Free Power Detect for LANs

CZN
OUT+
OUT-
LOS-
LOS+
DISABLE
SUB
GND
GNDO
100pF
50Ω
CZP
100kΩ
22kΩ
+VCCVTHINV
MAX3761
CAZ
150pF
50Ω
VCC - 2V
VCC
RSSI
VCCO
VIN+
10nF
100pF
BYPASS
SUPPLY
CIN
5.6nF
CIN
5.6nF
+5V
VIN-
FILTER
CFILTER
_________Typical Operating Circuits

19-1097; Rev 4; 8/08
EVALUATION KIT
AVAILABLE
Ordering Information

*Dice are designed to operate from -40°C to +85°C, but are
tested and guaranteed only at TA= +25°C.
+Denotes a lead-free/RoHS-compliant package.
__________________Pin Configuration

DISABLE
LOS+
LOS-
VCC VCC
RSSI
FILTER
TOP VIEW
VCCO
OUT+
OUT-
GNDOSUB
GND
VIN-
VIN+
VTH
INVCZN
CZP
QSOP

MAX3761
MAX3762
MAX3762 at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX3761EEP+ -40°C to +85°C 20 QSOP

MAX3761E/D -40°C to +85°C Dice*
MAX3762EEP+ -40°C to +85°C 20 QSOP

MAX3762E/D -40°C to +85°C Dice*
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +4.5V to +5.5V, DISABLE = low, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +5.0V, TA= +25°C.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:
Dice are tested at TA = +25°C.
Note 2:
Outputs terminated with 50Ωto VCC- 2V.
Note 3:
Voltage measurements are relative to VCC.
VCC, VCCO............................................................-0.5V to +7.0V
FILTER, RSSI, EN, VIN+, VIN-, CZP, CZN,
DISABLE, LOS+, LOS-, INV, VTH...............-0.5V to (VCC+ 0.5V)
PECL Output Current (OUT+, OUT-, LOS+, LOS-) ............50mA
Continuous Power Dissipation (TA= +85°C)
QSOP (derate 9.1mW/°C above +85°C).......................591mW
Operating Junction Temperature Range...........-40°C to +150°C
Processing Temperature (die).........................................+400°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX3762, IVCC
MAX3761, IVCC
DISABLE = high
DISABLE = high
MAX3761
MAX3761
(Notes 2, 3)
(Notes 2, 3)
Logic high
MAX3762 (Notes 2, 3)
MAX3761
MAX3761
MAX3762 (Note 3)
MAX3762 (Notes 2, 3)
MAX3762 (Note 3)
CONDITIONS
VCC- 0.7VCC-1.2Disabled Common-Mode Output-100100Disabled Differential Output-1830-1555PECL Data Output Voltage Low (VOL)-1150-880PECL Data Output Voltage High (VOH)-1470DISABLE Input PECL Low-1160DISABLE Input PECL High304637Power-Supply Current0.8DISABLE Input Low2.65DISABLE Input High100DISABLE Input Current-1830-1555LOS Output PECL Low2.8LOS Output TTL High0.40LOS Output TTLLow-1150-880LOS Output PECL High
UNITSMINTYPMAXPARAMETER

(TA= +25°C to +85°C)
(TA= -40°C to +25°C)0.44
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
AC ELECTRICAL CHARACTERISTICS

(VCC= +4.5V to +5.5V, PECL outputs terminated with 50Ωto VCC- 2V, input 4mV to 2Vp-p, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC= +5.0V, TA = +25°C.) (Note 5)
Note 5:
AC parameters are guaranteed by design and characterization.
Note 6:
Input signal is a 1-0 pattern, 622Mbps.
Note 7:
PWD = [(width of wider pulse) - (width of narrower pulse)] / 2.= -40°C, 223 - 1 PRBS
(Notes 6, 7)
(Note 6)
Differential
20% to 80%
CONDITIONS
3900Input ResistancePulse-Width Distortion3.2Minimum LOS Assert Input8020Data-Output Overshoot250Data-Output Edge Speed
UNITSMINTYPMAXPARAMETER
__________________________________________Typical Operating Characteristics

(MAX3761/MAX3762 EV kit, VCC= +5.0V, PECL outputs terminated with 50Ωto VCC- 2V, input is a 1-0 pattern, 622Mbps, TA= +25°C,
unless otherwise noted.)
223 - 1 PRBS, VTH = 1.8VdB3.5LOS Hysteresis
MAX3762
SUPPLY CURRENT vs. TEMPERATURE
MAX3761/62-01
AMBIENT TEMPERATURE (°C)
CURRENT (mA)
VCC = 5.5V
VCC = 5.0V
VCC = 4.5V10010001
INPUT SIGNAL (mVp-p)
RSSI VOLTAGE (V)
RSSI vs. INPUT AMPLITUDE
AND DATA PATTERN
MAX3761/62-02223 - 1
PRBS PATTERN
1-0 PATTERN
RSSI vs.
INPUT POWER AND FREQUENCY
MAX3761/62-03
INPUT POWER (dBm)
RSSI VOLTAGE (V)
10MHz
500MHz
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
____________________________Typical Operating Characteristics (continued)

(MAX3761/MAX3762 EV kit, VCC= +5.0V, PECL outputs terminated with 50Ωto VCC- 2V, input is a 1-0 pattern, 622Mbps, TA= +25°C,
unless otherwise noted.)
RSSI vs. TEMPERATURE
(622Mbps 223 - 1 PRBS)
MAX3761/62-04
AMBIENT TEMPERATURE (°C)
RSSI VOLTAGE (V)
VIN = 50mVp-p
VIN = 16mVp-p
VIN = 4mVp-p
LOS HYSTERESIS vs. TEMPERATURE
(622Mbps 223 - 1 PRBS PATTERN)
MAX3761/62-05
AMBIENT TEMPERATURE (°C)
HYSTERESIS (dB)
ASSERT LEVEL SET
TO APPROXIMATELY
2mVp-p
ASSERT LEVEL SET
TO APPROXIMATELY 30mVp-p
LOS HYSTERESIS vs. TEMPERATURE
(622Mbps 1-0 PATTERN)
MAX3761/62-06
AMBIENT TEMPERATURE (°C)
HYSTERESIS (dB)
ASSERT LEVEL SET
TO APPROXIMATELY
2mVp-p
ASSERT LEVEL SET
TO APPROXIMATELY
30mVp-p
DATA OUTPUT LEVELS
(REFERENCE TO VCC)
MAX3761/62-07
AMBIENT TEMPERATURE (°C)
VOLTAGE (V)
VOH
VOL1010.10.01
INPUT SIGNAL (Vp-p)
DIFFERENTIAL OUTPUT (mV)
0.1m
DIFFERENTIAL OUTPUT
vs. INPUT AMPLITUDE
MAX3761/62-08
INPUT SIGNAL (Vp-p)
PULSE-WIDTH DISTORTION (PS)
PULSE-WIDTH DISTORTION
(622Mbps DATA RATE)

MAX3761/62-09
-40°C
+85°C
100mV/
div
5μs/div
LOS OPERATION
WITH SQUELCHING

MAX3761/62-10
DATA IN
LOS+
OUT+
100mV/
div
5μs/div
DATA IN
LOS+
OUT+
LOS OPERATION
WITHOUT SQUELCHING

MAX3761/62-11
50mV/
div
500ps/div
DATA OUTPUT SINGLE-ENDED23 - 1 PRBS PATTERN)

MAX3761/62-12
INPUT = 4mVp-p
TA = +85°C
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
____________________________Typical Operating Characteristics (continued)

(MAX3761/MAX3762 EV kit, VCC= +5.0V, PECL outputs terminated with 50Ωto VCC- 2V, input is a 1-0 pattern, 622Mbps, TA= +25°C,
unless otherwise noted.)
______________________________________________________________Pin Description
NAMEFUNCTION
FILTERSets the integration frequency of the power detector. Impedance at this node is approximately 500Ω.RSSIReceived-Signal-Strength Indicator. An analog DC voltage representing the input power.
PIN
ENConnect to VCC.
4, 17VCC+5V Power Supply VIN+Positive Input Data VIN-Negative Input Data GNDSupply Ground SUBSubstrate. Connect to ground.CZPSets input offset correction, low-frequency cutoff.CZNSets input offset correction, low-frequency cutoff.INVNegative Input to Op Amp. Used for programming the loss-of-signal threshold.VTHLoss-of-Signal Threshold VoltageGNDOGround Power Supply for Output Buffers OUT-Negative PECL Data OutputOUT+Positive PECL Data OutputVCCO+5V Power Supply for Output BuffersLOS-Negative Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762) LOS+Positive Loss-of-Power Flag, TTL (MAX3761) or PECL (MAX3762)DISABLEDisables the data outputs when high. TTL (MAX3761) or PECL (MAX3762).
50mV/
div
500ps/div
DATA OUTPUT SINGLE-ENDED
(223-1 PRBS PATTERN)

MAX3761/62-13
INPUT = 2Vp-p
TA = +85°C
200mV/
div
200ps/div
RANDOM JITTER

MAX3761/62-14
DIFFERENTIAL OUTPUT
(OUT+ - OUT-)
INPUT = 16mVp-p
TA = +27°C
1-0 PATTERN 622Mbps
FREQUENCY ON POWER SUPPLY (Hz)
RANDOM JITTER (ps rms)
RANDOM JITTER vs.
POWER-SUPPLY NOISE FREQUENCY

MAX3761/62-15
DIFFERENTIAL OUTPUT RANDOM JITTER
DATA INPUT AMPLITUDE = 16mVp-p
INPUT AMPLITUDE
POWER SUPPLY = 100mVp-p
MAX3761/MAX3762
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
_______________Detailed Description

Figure 1 shows the functional diagram for the MAX3761/
MAX3762. The input signal is applied to VIN+ and VIN-.
A chain of amplifier stages, each contributing approxi-
mately 12.5dB of gain, amplifies the input signal to
PECL output voltage swings. A 4mVp-p input signal will
cause the output to fully limit.
Received-Signal-Strength
Indicator (RSSI)

Each amplifier stage contains a full-wave logarithmic
detector (FWD). The full-wave detector outputs are
summed at the FILTER pin and used to generate the
received-signal-strength indication (RSSI). The RSSI
output voltage is linearly proportional to the input power
(in decibels), and is approximated by:
where VINis the peak-to-peak input signal in millivolts.
The RSSI output is insensitive to fluctuations in temperature
and supply voltage. The power detector functions as a
broadband power meter that detects the total power of all
signals present in the passband of approximately 750MHz.
Refer to the Typical Operating Characteristicsgraphs show-
ing RSSI output versus input power and signal amplitude.
The high-speed RSSI signal is filtered with one external
capacitor connected from FILTER to VCC. The imped-
ance at the FILTER pin is approximately 500Ω.
The FILTER capacitor (CFILTER) must be connected
to VCCfor proper operation.
Input-Offset Correction

The limiting amplifier provides approximately 60dB of
gain. An input DC offset of even 1mV reduces the
power-detection circuit’s accuracy and can cause the
output to limit. A low-frequency feedback loop is inte-
grated into the MAX3761/MAX3762 to remove input off-
set. DC coupling the inputs is not recommended, as
this prevents the DC-offset-correction circuitry from
functioning properly. Input offset is typically reduced to
less than 100μV.
The capacitance between pins CZP and CZN, in parallel
with a 10pF integrated capacitance, determines the off-
set-correction circuit’s time constant. The input imped-
ance between CZP and CZN is approximately 800kΩ.
The offset correction circuitry requires an average data-
input duty cycle of 50%. If the input data has a different
average duty cycle, the output will have increased
pulse-width distortion.(V)=1.13+0.457log(V)RSSIIN
LIMITER
FWD
LIMITER
FWD
LIMITER
FWD
FILTER
REF
INVVTHR2
GNDO
LOS+/LOS-
VCC - 2V
RSSI
50Ω
OUT+/OUT-
DISABLE
VCCO ENCZN
CAZ
CZPSUBGNDVCC
VIN+/VIN-
CIN
CFILTER
VCC
FWD = FULL-WAVE DETECTOR
LIMITER
FWD
MAX3761/MAX3762
Figure 1. Functional Diagram
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