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MAX3750CEEMAXIMN/a5avai+3.3V / 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs
MAX3750CEEN/a90avai+3.3V / 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs


MAX3750CEE ,+3.3V / 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +70°C, unless otherwise noted. Typical va ..
MAX3750CEE ,+3.3V / 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICsApplicationsTypical Application CircuitTX RX TX RX TX RXC3 C5OUT+ IN+ OUT+ IN+ OUT+ IN+OUT- IN- OUT ..
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MAX3750CEE+T ,+3.3V, 2.125Gbps/1.0625Gbps Fibre-Channel Port Bypass ICsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = 0°C to +70°C, unless otherwise noted. Typical va ..
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MAX3750CEE
+3.3V / 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs
General Description
The MAX3750/MAX3751 are +3.3V, Fibre Channel port
bypass ICs that include a high-speed multiplexer and
output buffer stage for hot swapping a storage device.
These devices are optimized for use in a Fibre Channel
arbitrated loop topology.
The MAX3750 has a 2.125Gbps data rate, while the
MAX3751’s data rate is 1.0625Gbps. Total power con-
sumption (including output currents) is low: just 190mW
for the MAX3750 and 180mW for the MAX3751. Low
10ps jitter makes these devices ideal for cascaded
topologies. The output driver circuitry is tolerant of load
mismatches commonly caused by board vias and
inductive connectors. On-chip termination reduces
external part count and simplifies board layout.
Applications

2.125Gbps Fibre Channel Arbitrated Loop
1.0625Gbps Fibre Channel Arbitrated Loop
Mass Storage Systems
RAID/JBOD Applications
Features
Single +3.3V Supply Low Jitter: 10psLow Power Consumption
190mW (MAX3750)
180mW (MAX3751)
Large Output Signal Swing: >1000mVp-pMismatch Tolerant Output Driver Stage150ΩDifferential On-Chip Termination on All Inputs150ΩOn-Chip Back Termination on All Output
Ports
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
Pin Configuration appears at end of data sheet.
Ordering Informationypical Application Circuit
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VCC= +3.3V and TA= +25°C.)
Note 1:
Output currents included.
Supply Voltage, VCC..............................................-0.5V to +5.0V
Voltage at LOUT+, LOUT-,
OUT+, OUT-..............................(VCC- 1.65V) to (VCC+ 0.5V)
Current Out of LOUT+, LOUT-, OUT+, OUT-...................±22mA
Voltage at SEL, LIN+, LIN-, IN+, IN-..........-0.5V to (VCC+ 0.5V)
Differential Voltage at (LIN+ - LIN-), (IN+ - IN-).....................±2V
Continuous Power Dissipation (TA= +70°C)
16 QSOP (derate 8.3mW/°C above +70°C).................667mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range...............................-55°C to 150°C
Lead Soldering Temperature (soldering, 10sec).............+300°C
AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VCC= +3.3V and TA= +25°C.)
Note 2:
Input tRand tF< 150ps, 20% to 80%.
Note 3:
Input tRand tF< 300ps, 20% to 80%.
Note 4:
Deterministic jitter is measured with 20 bits of the k28.5 pattern (00111110101100000101).
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
Typical Operating Characteristics

(VCC= 3.3V, TA = +25°C, unless otherwise noted.)
Pin Description
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
_________________Circuit Description

A simplified block diagram of the single port bypass is
shown in Figure 1. IN+ and IN- drive an input buffer
(INBUFF) with 150Wof internal differential input termi-
nation. INBUFF drives an output buffer (LOBUFF) and
an input to a multiplexer (MUX).
A low TTL input at SEL selects the signal path of
INBUFF through MUX to the output buffer (OUTBUFF).
When SEL has a high TTL logic level present the signal
path is into LIBUFF, through MUX, to OUTBUFF.
Low-Frequency Cutoff

The low-frequency cutoff is determined by the input
resistance and the coupling capacitor as illustrated by
the following equation:= 1 / (2pRC)
In a typical system where R = 150Ωand C = 100nF,
resulting in fC= 10kHz.
Layout Techniques

The MAX3750/MAX3751 are high-frequency products.
The performance of the circuit is largely dependent
upon layout of the circuit board. Use a multilayer circuit
board with dedicated ground and VCCplanes. Power
supplies should be capacitively bypassed to the
ground plane with surface-mount capacitors placed
near the power-supply pins.
Figure 1. MAX3750/MAX3751 Block Diagram
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs

Figure 2. LOUT/OUT Pins Internal Input/Output Schematic
Figure 4. LIN/IN Pins Internal Input/Output Schematic
Figure 3. SEL Pin Internal Input/Output Schematic
Figure 5. 50ΩTermination Applications
MAX3750/MAX3751
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Package Information
Pin Configuration
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