MAX3680EAI+T ,+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL OutputsApplications ________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RA ..
MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, differential loads = 100W , T = -40°C to +85°C, unle ..
MAX3681EAG ,+3.3V / 622Mbps / SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RA ..
MAX3681EAG+ ,+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS OutputsApplications________________Ordering Information622Mbps SDH/SONET Transmission SystemsPART TEMP RAN ..
MAX368CPN ,Fault-Protected Analog Multiplexer with LatchGeneral Description
Maxim's MAX368/369 are 8 channel single-ended (1 of
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MAX368EJN ,Fault-Protected Analog Multiplexer with Latch19-0982; Rev 1; T/96
Analog Multiplexer with Latch,
MAX7318AUG ,2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion ProtectionELECTRICAL CHARACTERISTICS(V+ = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted. Typical va ..
MAX7318AUG+ ,2-Wire-Interfaced, 16-Bit, I/O Port Expander with Interrupt and Hot-Insertion ProtectionApplicationsPKGPART TEMP RANGE PIN-PACKAGECODEServersMAX7318AWG -40°C to +125°C 24 Wide SO —RAID Sy ..
MAX7319AEE+ ,I²C Port Expander with Eight Inputs and Maskable Transition DetectionFeatures2The MAX7319 2-wire serial-interfaced peripheral ● 400kHz, +5.5V -Tolerant I C Serial Inte ..
MAX7319AEE+ ,I²C Port Expander with Eight Inputs and Maskable Transition DetectionApplications● Cell Phones ● Notebooks● SAN/NAS ● Satellite Radio● ServersSelector GuidePART INPUTS ..
MAX731CPA ,+5V/Adjustable Step-Up Current-Mode DC-DC ConvertersELECTRICAL CHARACTERISTICS - MAX731
(Circuit of Figure 1a, VIN = +3V, ILOAD = 0mA, TA = TMIN to ..
MAX731CPA ,+5V/Adjustable Step-Up Current-Mode DC-DC ConvertersFeatures
. 200mA Load Currents Guaranteed with
No External M
OSFET
. Step-Up from a 2.5 ..
MAX3680EAI+-MAX3680EAI+T
+3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs
_________________General DescriptionThe MAX3680/MAX3680A deserializer is ideal for con-
verting 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data in ATM and SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts PECL serial clock and data inputs, and deliv-
ers TTL clock and data outputs. The MAX3680 also pro-
vides a TTL synchronization input that enables data
realignment and reframing.
The MAX3680/MAX3680A is available in the extended-
industrial temperature range (-40°C to +85°C), in a 28-
pin SSOP package.
__________________________Applications622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross-Connects
______________________________Features♦
Single +3.3V Supply♦
622Mbps Serial to 77Mbps Parallel Conversion♦
165mW Power♦
Synchronization Input for Data Realignment and
Reframing (MAX3680)♦
Differential 3.3V PECL Clock and Data Inputs♦
TTL Data Outputs
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL OutputsMAX3675
MAX3664
MAX3680/
MAX3680A
DATA
AND
CLOCK
RECOVERY
OVERHEAD
TERMINATION
LIMITING
AMP
PREAMP100Ω
PHOTODIODE
VCC = +3.3V
VCC = +3.3V
SD+
SD-
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.
VCC
GND
130Ω130Ω
82Ω82Ω
VCC = +3.3V
130Ω130Ω
82Ω82Ω
VCC = +3.3V
SCLK+
SCLK-
SYNC
PCLK
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
___________________________________________________________________Typical Operating Circuit19-1210; Rev 3; 3/07
________________Ordering Information
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE+Denotes lead-free package.
PART TEMP RANGE PIN-PACKAGE MAX3680EAI -40°C to +85°C 28 SSOP
MAX3680EAI+ -40°C to +85°C 28 SSOP
MAX3680AEAI -40°C to +85°C 28 SSOP
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:AC characteristics guaranteed by design and characterization.
Note 1:The SYNC input is available only on the MAX3680.
Terminal Voltage (with respect to GND)
VCC........................................................................-0.5V to +5V
PECL Inputs (SD+/-, SCLK+/-)................-0.5V to (VCC+ 0.5V)
TTL Input (SYNC)....................................-0.5V to (VCC+ 0.5V)
TTL Outputs (PCLK, PD_)........................-0.5V to (VCC+ 0.5V)
Continuous Power Dissipation (TA= +85°C)
SSOP (derate 9.52mW/°C above +85°C).....................619mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
TTL outputs = high
VIN= VIL(MAX)
VIN= VIH(MAX)
VIN= VIH(MAX)
VIN= VIL(MAX)
Output sinking = 400µA
Output sourcing = 400µA
CONDITIONS00.44VOLOutput Low Voltage2.4VCCVOHOutput High VoltageVCC- 1.16VCC- 0.88VIHInput High Voltage255090ICCSupply Current-1010IILInput Low Current-1010IIHInput High Current0.8VILInput Low Voltage2.0VIHInput High VoltageVCC- 1.81VCC- 1.48VILInput Low Voltage-1010IIHInput High Current-1010IILInput Low Current
UNITSMINTYPMAXSYMBOLPARAMETER
CONDITIONS50tHSerial Data Hold Time800tSU
MHz622fSCLKMaximum Serial Clock Frequency
Serial Data Setup Time
UNITSMINTYPMAXSYMBOLPARAMETER
PECL INPUTS(SD+/-, SCLK+/-)
TTL INPUT AND OUTPUTS(SYNC, PCLK, PD_) (Note 1)
AC ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= +25°C, unless otherwise noted.) (Note 2)
VCC= +3.3V, CL= 18pFps-2005002000tCLK-QParallel Clock to Data Output Delay
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL OutputsMAXIMUM SERIAL-CLOCK FREQUENCY
vs. TEMPERATURE
MAX3680-01
SERIAL CLOCK FREQUENCY (GHz)
TEMPERATURE (°C)
SERIAL DATA SETUP TIME
vs. TEMPERATURE
MAX3680-02
SERIAL DATA-SETUP TIME (ps)
TEMPERATURE (°C)
SERIAL DATA HOLD TIME
vs. TEMPERATURE
MAX3680-03
SERIAL DATA-HOLD TIME (ps)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3680-04
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
VCC = +3.6V
VCC = +3.0V
VCC = +3.3V
__________________________________________Typical Operating Characteristics(VCC= +3.0V to +3.6V, unless otherwise noted.)
MAX3680/MAX3680A
Detailed DescriptionThe MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
Pin Description8-BIT
SHIFT
REGISTER
8-BIT
PARALLEL
OUTPUT
REGISTER
3-BIT
COUNTER
TTL
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLK
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTLTTL
PECL
PECL
SYNC
MAX3680/
MAX3680A
SD+
SD-
SCLK+
SCLK-
Figure 1. Functional Diagram
PIN
MAX3680MAX3680A
NAMEFUNCTION1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25 VCC +3.3V Supply Voltage
3 3 SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
4 4 SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6 6 SCLK+ Noninverting PECL Serial Clock Input
7 7 SCLK- Inverting PECL Serial Clock Input
9, 11, 12,
16, 20, 23,
27
11, 12, 16,
20, 23, 27 GND Ground
10 — SYNC TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
— 9, 10 N.C. No Connection
13 13 PCLK TTL Parallel Clock Output
15, 17, 19,
21, 22, 24,
26, 28
15, 17, 19,
21, 22, 24,
26, 28
PD0–PD7 TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL OutputsSCLK*
SD*
PCLK
PD7
PD6
PD5
PD4
D1-D0D1
D8-D9D7-D10D6-D11D5-D12PD3
PD2
PD1
PD0
D4-D13D3-D14D2-D15D1-D8D3D4D5D6D7D9D10D11D12D13D14D15D16D17D18D8
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2a. Functional Timing Diagram—Normal Operation
MAX3680/MAX3680A
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL OutputsSCLK*
SD*
SYNC
PCLK
PD7
PD6
PD5
PD4
D1-D0D1
D8-D1D9
D7-D2D10
D6-D3D11
D5-D4D12
PD3
PD2
PD1
PD0
D4-D5D13
D3-D6D14
D2-D7D15
D1-D8D16D3D4D5D6D7D9D10D11D12D13D14D15D16D17D18D8
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2b. Functional Timing Diagram—SYNC Operation (MAX3680)
SCLK*
SD*
PCLK
PD0–PD7
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
tSCLK = 1 / fSCLK
tSUtH
tCLK-Q
Figure 3. Timing Parameters
