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MAX3664EUAMAXIMN/a1000avai622Mbps, ultra-low-power, 3.3V transimpedance preamplifier for SDH/SONET.


MAX3664EUA ,622Mbps, ultra-low-power, 3.3V transimpedance preamplifier for SDH/SONET.applications consumes only' 55nA Input-Referred NoiseRMS85mW. Operating from a single +3.3V supply, ..
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MAX7311AUG+ ,2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion ProtectionELECTRICAL CHARACTERISTICS+ +(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted. Typical ..
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MAX7311AUG+T ,2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion ProtectionELECTRICAL CHARACTERISTICS (continued)+ +(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise not ..
MAX7312AAG+ ,2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion ProtectionApplications(4mm x 4mm)Servers/BladesMAX7312AUG -40°C to +125°C 24 TSSOP —RAID SystemsSMBus is a tr ..
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MAX3664EUA
622Mbps, ultra-low-power, 3.3V transimpedance preamplifier for SDH/SONET.
________________General Description
The MAX3664 low-power transimpedance preamplifier
for 622Mbps SDH/SONET applications consumes only
85mW. Operating from a single +3.3V supply, it converts
a small photodiode current to a measurable differential
voltage. A DC cancellation circuit provides a true differ-
ential output swing over a wide range of input current
levels, thus reducing pulse-width distortion. The differen-
tial outputs are back-terminated with 60Ωper side.
The transimpedance gain is nominally 6kΩ. For input
signal levels beyond approximately 100µAp-p, the
amplifier will limit the output swing to 900mV. The
MAX3664’s low 55nA input noise provides a typical
sensitivity of -33.2dBm in 1300nm, 622Mbps receivers.
The MAX3664 is designed to be used in conjunction
with the MAX3675 clock recovery and data retiming IC
with limiting amplifier. Together, they form a complete
3.3V, 622Mbps SDH/SONET receiver.
In die form, the MAX3664 is designed to fit on a header
with a PIN diode. It includes a filter connection, which
provides positive bias for the photodiode through a 1kΩ
resistor to VCC. The device is also available in 8-pin SO
and µMAX packages.
________________________Applications

SDH/SONET Receivers
PIN/Preamplifier Receivers
Regenerators for SDH/SONET
____________________________Features
Single +3.3V Supply Operation55nARMSInput-Referred Noise6kΩGain85mW Power300µA Peak Input Current200ps Max Pulse-Width DistortionDifferential Output Drives 100ΩLoad590MHz Bandwidth
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
__________________________________________________Typical Application Circuit
Pin Configuration appears at end of data sheet.

* Contact factory for package availability.
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCC= +3.3V ±0.3V, COMP = GND, 100Ωload between OUT+ and OUT-, TA= -40°C to +85°C. Typical values are at TA= +25°C,
unless otherwise noted.) (Notes 1, 2)
AC ELECTRICAL CHARACTERISTICS

(VCC= +3.3V ±0.3V, CCOMP= 400pF, CIN= 1.1pF, outputs terminated into 50Ω, 8-pin SO package in MAX3664 EV board,= +25°C, unless otherwise noted.) (Notes 3, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 3:
AC Characteristics are guaranteed by design.
Note 4:
CINis the total capacitance at IN.
Note 5:
PWD = ||2
Note 6:
DC to 470MHz, measured with 3-pole Bessel filter at output.
Note 1:
Dice are tested at Tj= +27°C.
Note 2:
µMAX package tested at TA= +25°C to +85°C.
VCC........................................................................-0.5V to +5.5V
Continuous Current
IN, INREF1, INREF2, COMP, FILT....................................5mA
OUT+, OUT-...................................................................25mA
Continuous Power Dissipation (TA= +85°C)
SO (derate 5.88mW/°C above +85°C)........................383mW
µMAX (derate 4.1mW/°C above +85°C).....................268mW
Operating Junction Temperature (die)..............-40°C to +150°C
Processing Temperature (die).........................................+400°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
__________________________________________Typical Operating Characteristics

(VCC= +3.3V, CCOMP= 400pF, TA= +25°C, unless otherwise noted.)
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
_____________________________Typical Operating Characteristics (continued)

(VCC= +3.3V, CCOMP= 400pF, TA= +25°C, unless otherwise noted.)
________________Detailed Description
The MAX3664 is a transimpedance amplifier designed
for 622Mbps SDH/SONET applications. It comprises a
transimpedance amplifier, a paraphase amplifier with
emitter-follower outputs, and a DC cancellation loop.
Figure 1 is a functional diagram of the MAX3664.
Transimpedance Amplifier

The signal current at IN flows into the summing node of
a high-gain amplifier. Shunt feedback through RFcon-
verts this current to a voltage with a gain of 6kΩ. Diode
D1 clamps the output voltage for large input currents.
INREF1 is a direct connection to the emitter of the input
transistor, and must be connected directly to the pho-
todetector AC ground return for best performance.
Paraphase Amplifier

The paraphase amplifier converts single-ended inputs to
differential outputs, and introduces a voltage gain of 2.
This signal drives a pair of internally biased emitter follow-
ers, Q2 and Q3, which form the output stage. Resistors
R1 and R2 provide back-termination at the output,
absorbing reflections between the MAX3664 and its load.
The output emitter followers are designed to drive a
100Ωdifferential load between OUT+ and OUT-. They
can also drive higher output impedances, resulting in
increased gain and output voltage swing.
DC Cancellation Loop

The DC cancellation loop removes the DC component
of the input signal by using low-frequency feedback.
This feature centers the signal within the MAX3664’s
dynamic range, reducing pulse-width distortion on
large input signals.
The output of the paraphase amplifier is sensed through
resistors R3 and R4 and then filtered, amplified, and fed
back to the base of transistor Q4. The transistor draws
the DC component of the input signal away from the
transimpedance amplifier’s summing node.
The COMP pin sets the DC cancellation loop’s
response. Connect 400pF or more between COMP and
GND for normal operation. Connect the pin directly to
GND to disable the loop. The DC cancellation loop can
sink up to 300µA of current at the input. When operated
with CCOMP= 400pF, the loop takes approximately
20µs to stabilize.
The MAX3664 minimizes pulse-width distortion for data
sequences that exhibit a 50% duty cycle. A duty cycle
other than 50% causes the device to generate pulse-
width distortion.
DC cancellation current is drawn from the input and
adds noise. For low-level signals with little or no DC
component, this is not a problem. Preamplifier noise will
increase for signals with significant DC component.
___________Applications Information

The MAX3664 is a low-noise, wide-bandwidth transim-
pedance amplifier that is ideal for 622Mbps SDH/
SONET receivers. Its features allow easy design into a
fiber optic module, in four simple steps.
Step 1: Selecting a Preamplifier for a 622Mbps
Receiver

Fiber optic systems place requirements on the band-
width, gain, and noise of the transimpedance preampli-
fier. The MAX3664 optimizes these characteristics for
SDH/SONET receiver applications that operate at
622Mbps.
In general, the bandwidth of a fiber optic preamplifier
should be 0.6 to 1 times the data rate. Therefore, in a
622Mbps system, the bandwidth should be between
375MHz and 622MHz. Lower bandwidth causes pat-
tern-dependent jitter and a lower signal-to-noise ratio,
while higher bandwidth increases thermal noise. The
MAX3664 typical bandwidth is 590MHz, making it ideal
for 622Mbps applications.
The preamplifier’s transimpedance must be high
enough to ensure that expected input signals generate
output levels exceeding the sensitivity of the limiting
amplifier (quantizer) in the following stage. The
MAX3675 clock recovery and limiting amplifier IC has
an input sensitivity of 3.6mVp-p, which means that
3.6mVp-p is the minimum signal amplitude required to
produce a fully limited output. Therefore, when used
with the MAX3664, which has a 6kΩtransimpedance,
the minimum detectable photodetector current is 600nA.
It is common to relate peak-to-peak input signals to
average optical power. The relationship between opti-
cal input power and output current for a photodetector
is called the responsivity (r), with units Amperes/Watt
(A/W). The photodetector peak-to-peak current is relat-
ed to the peak-to-peak optical power as follows:
Ip-p = (Pp-p)(r)
Based on the assumption that SDH/SONET signals
maintain a 50% duty cycle, the following equations
relate peak-to-peak optical power to average optical
power and extinction ratio (Figure 2):
Average Optical Power = PAVE= (P0 + P1) / 2
Extinction Ratio = re= P1 / P0
Peak-to-Peak Signal Amplitude = Pp-p = P1 - P0
Therefore,
PAVE= Pp-p (1 / 2)[(re+ 1) / (re- 1)]
MAX3664
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET
MAX3664
In a system where the photodiode responsivity is
0.9A/W and the extinction ratio is 10, the MAX3664/
MAX3675 receiver with 670nA gain sensitivity will deliv-
er a fully limited output for signals of average optical
power larger than:
(600nA / 0.9A/W)(1 / 2)(11 / 9) = 407nW ⇒-33.9dBm
Sensitivity is a key specification of the receiver module.
The ITU/Bellcore specifications for SDH/SONET
receivers require a link sensitivity of -27dBm with a bit
error rate (BER) of 1E - 10. There is an additional 1dB
power penalty to accommodate various system losses;
therefore, the sensitivity of a 622Mbps receiver must be
better than -28dBm.
Although several parameters affect sensitivity (such as
the quantizer sensitivity and preamplifier gain, as previ-
ously discussed), most fiber optic receivers are designed
so that noiseis the dominant factor. Noise from the high-
gain transimpedance amplifier, in particular, determines
the sensitivity. The noise generated by the MAX3664 can
be modeled with a Gaussian distribution. In this case, a
BER of 1E - 10 corresponds to a peak-to-peak signal
amplitude to RMS noise ratio (SNR) of 12.7. The
MAX3664’s typical input-referred noise, in, (bandwidth-
limited to 470MHz) is 55nARMS. Therefore, the minimum
input for a BER of 1E - 10 is (12.7 x 55nA) = 700nAp-p.
Rearranging the previous equations in these terms
results in the following relation:
Optical Sensitivity (dBm) =
-10log[(in/ r)(SNR)(1/2)(re+ 1) / (re- 1)(1000)]
At room temperature, with re= 10, SNR = 12.7, in=
55nA, and r= 0.9A/W, the MAX3664 sensitivity is
-33.2dBm. At +85°C, noise increases to 62nA and sen-
sitivity decreases to -32.7dBm. The MAX3664 provides
4.7dB margin over the SDH/SONET specifications, even
at +85°C.
The largest allowable input to an optical receiver is called
the input overload. The MAX3664’s largest input current
(Imax) is 300µAp-p, with 200ps of pulse-width distortion.
The pulse-width distortion and input current are closely
related (see Typical Operating Characteristics). If the
clock recovery circuit can accept more pulse-width dis-
tortion, a higher input current might be acceptable. For
worst-case responsivity and extinction ratio, r= 1A/W
and re= ¥, the input overload is:
Overload (dBm) = -10log (Imax)(1 / 2)(1000)
For Imax= 300µA, the MAX3664 overload is -8.2dBm.
Step 2: Selecting Time Constants

A receiver built with the MAX3664 will have a bandpass
frequency response. The low-frequency cutoff causes
unwanted data-dependent jitter and sensitivity loss.
Because SDH/SONET data streams contain scrambled
data, certain data sequences may generate continuous
successions of 1s or 0s. The low-frequency cutoff
forces the output of such sequences to zero, ultimately
causing a sensitivity reduction. The SDH specifications
state that a receiver must be able to handle up to 72
consecutive bits of the same value within the data.
Therefore, choose the low-frequency cutoff to ensure
an acceptable amount of data-dependent jitter and
sensitivity loss.
Determine the reduction in signal-to-noise ratio due to a
transitionless sequence of duration t as follows:
SNRloss= 1 - e-t/ t= 1-e-(2pfct)
where tis the time constant of the offset correction, fc
is the low-frequency cutoff, and t is the time for 72 bits
(116ns for a 622Mbps data rate).
Suppose that the receiver should not have more than
0.25dB (6%) of sensitivity loss due to a 72-bit transition-
less sequence. This means that:
(1 - e-(2pfc)(116ns))< 0.06= (ln 0.94) / [(-2p)(116ns)] = 85kHz (max)
The loss of sensitivity is a concern only when the SNR is
small (close to 12.7), which occurs with input currents
less than 3µAp-p.
622Mbps, Ultra-Low-Power, 3.3V
Transimpedance Preamplifier for SDH/SONET

Figure 2. Optical Power Definitions
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