MAX3645ESE+T ,+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal DetectorApplications+Denotes lead-free package.SONET 155Mbps Transceivers Pin ConfigurationFast Ethernet Re ..
MAX3646ETG ,155Mbps to 622Mbps SFF/SFP Laser Driver with Extinction Ratio ControlApplicationsMODTCOMP 1 18MDMultirate OC-3 to OC-12 FEC TransceiversV 2 VCC 17 CC125Mbps Ethernet SF ..
MAX3646ETG+ ,155Mbps to 622Mbps SFF/SFP Laser Driver with Extinction Ratio Controlfeatures♦ Automatic Power Control (APC)of automatic power control (APC), modulation compensa-tion, ..
MAX3646ETG+T ,155Mbps to 622Mbps SFF/SFP Laser Driver with Extinction Ratio Controlfeaturesof automatic power control (APC), modulation compensa- ♦ Automatic Power Control (APC)tion, ..
MAX364CPE ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V = 2.4V, V = 0.8V ..
MAX364CPE ,Precision, Quad, SPST Analog SwitchesApplicationsMAX365CPE 0°C to +70°C 16 Plastic DIPSample-and-Hold Circuits Communication SystemsMAX3 ..
MAX7301AAI+T ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderGeneral Description Beneits and
MAX7301AAX ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderApplicationsWhite GoodsTypical Operating CircuitAutomotiveGaming Machines 3V36 32V+ P4 I/O 4Industr ..
MAX7301AAX ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderFeaturesThe MAX7301 compact, serial-interfaced I/O expander♦ High-Speed 26MHz SPI-/QSPI-™/MICROWIRE ..
MAX7301AAX+ ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderApplications MAX7301 P10 I/O 1035 11CHIP SELECT P11 I/O 11CS● White Goods33 6CLOCK IN SCLK P12I/O 1 ..
MAX7301AAX+ ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderGeneral Description Beneits and
MAX7301AAX+T ,4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and 28-Port I/O ExpanderElectrical Characteristics(Typical Operating Circuit, V+ = 2.5V to 5.5V, T = T to T , unless otherw ..
MAX3645EEE+-MAX3645EEE+T-MAX3645ESE+T
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
neral DescriptionThe MAX3645 limiting amplifier functions as a data
quantizer and is pin compatible with the Mindspeed
MC2045-2 and MC2045-2Y postamplifiers. The amplifi-
er accepts a wide range of input voltages and provides
constant-level positive emitter-coupled logic (PECL)
output voltages with controlled edge speeds.
The MAX3645 features an integrated power detector
with complementary PECL loss-of-signal (LOS) outputs
that indicate when the input power level drops below a
programmable threshold. An optional squelch function
holds the data outputs at static levels during a
LOS condition.
The MAX3645 operates from a single +3.3V or +5.0V
power supply over a -40°C to +85°C temperature
range. It is available in 16-pin SO and 16-pin QSOP
packages.
ApplicationsSONET 155Mbps Transceivers
Fast Ethernet Receivers
FDDI 125Mbps Receivers
FTTx Receivers
ESCON Receivers
FeaturesPin Compatible with the Mindspeed
MC2045-2/MC2045-2Y500μV Input Sensitivity (BER = 10-12)Compatible with 4B/5B Data CodingProgrammable LOS ThresholdStable LOS Threshold Over Supply RangeOutput Disable Function and Automatic SquelchSingle +3.3V or +5.0V Power Supply18mA Supply Current.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal Detector
Ordering Information19-3026; Rev 1; 11/04
PARTTEMP RANGEPIN-PACKAGEMAX3645ESE-40°C to +85°C16 SO
MAX3645EEE-40°C to +85°C16 QSOP
MAX3645EEE+-40°C to +85°C16 QSOP
CAZ2TH
N.C.
VCCE
DOUT+
DOUT-
GNDE
LOS
TOP VIEW
MAX3645
SO/QSOPCAZ1
GNDA
VCCA
DIN+
DIN-
CSD
DIS
LOS
Pin ConfigurationMAX3645MAX3644*
PIN K
VCC
VCCVCC
VCC
OUT-
OUT+DIN+
DIN-
GNDA
DOUT+
DOUT-
LOS
LOS
DIS
CSDVCCACAZ1CAZ2
GND
*FUTURE PRODUCT
VCCEGNDE
N.C.0.1μF
0.1μF
CSD
1nF
CAZ
0.1μF
RTH
100Ω50Ω
50Ω50Ω50Ω
VCC - 2V
VCC - 2V
Typical Application Circuit+Denotes lead-free package.
2.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal DetectorABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +2.97V to +5.5V, PECL outputs are terminated with 50Ωto VCC- 2V, RTH= 100Ω, CAZ= 0.1μF, CSD= 1nF, TA= -40°C to
+85°C. Typical values are at VCC= +3.3V, TA = +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCCA, VCCE)....................-0.5V to +7.0V
Voltage at CAZ1, CAZ2, DIN+,
DIN-, CSD, DIS, TH................................-0.5V to (VCC+ 0.5V)
PECL Output Current (DOUT+, DOUT-, LOS, LOS)...........50mA
Differential Voltage between CAZ1 and CAZ2......-1.5V to +1.5V
Differential Voltage between DIN+ and DIN-........-1.5V to +1.5V
Continuous Power Dissipation (TA= +85°C)
16-Pin SO (derate 8.7mW/°C above +85°C)................565mW
16-Pin QSOP (derate 8.3mW/°C above +85°C)...........540mW
Storage Ambient Temperature Range (TS)…….-65°C to +160°C
Lead Temperature (soldering, 10s)...........……………….+300°C
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
POWER SUPPLYSupply CurrentICCExcludes PECL termination currents1827mA
INPUT SPECIFICATIONSInput ResistanceRINSingle ended; VIN = ±200mV3.34.86.4kΩ
Single ended0.5Input Sensitivity (Note 1)VIN-MINDifferential1.0mVP-P
Single ended750Input Overload (Note 1)VIN-MAXDifferential1500mVP-P
Input-Referred Offset VoltageUnterminated input, output offset divided by
DC gain (Note 2)240μV
Input Common-Mode VoltageVCMMVCC -
0.87V
Input-Referred RMS NoiseVIN-NOISE(Notes 2, 3)3650μVRMS
DIS Input HighVIHPECL or CMOS logicVCC -
1160VCCmV
DIS Input LowVILPECL or CMOS logic0VCC -
1480mV
DIS Input CurrentIIL, IIH0V ≤ VDIS ≤ VCC-10+10μA
OUTPUT SPECIFICATIONSPECL Output-Voltage High(Notes 1, 2)VCC -
VCC -
880mV
PECL Output-Voltage Low(Notes 1, 2)VCC -
VCC -
1555mV
Data Output Transition TimetR, tF20% to 80% (Notes 1, 2, 4)0.71.4ns
Pulse-Width DistortionPWD(Notes 1, 2, 4, 5)30200ps
.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal DetectorNote 1:Between sensitivity and overload, the output amplitude is >95% of the fully limited amplitude and all AC specifications are met.
Note 2:Guaranteed by design and characterization.
Note 3:Noise is derived from BER measurement.
Note 4:The data input transition time is controlled by a 4th-order Bessel filter with f-3dB= 0.75 ×data rate.
Note 5:PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 155Mbps 0011 pattern.
Note 6:All LOS specifications are measured using a 155Mbps 223- 1 PRBS pattern.
Note 7:The signal at the input is switched between two amplitudes, SIGNAL_ON and SIGNAL_OFF, as shown in Figure 1.
ELECTRICAL CHARACTERISTICS (continued)(VCC= +2.97V to +5.5V, PECL outputs are terminated with 50Ωto VCC- 2V, RTH= 100Ω, CAZ= 0.1μF, CSD= 1nF, TA= -40°C to
+85°C. Typical values are at VCC= +3.3V, TA = +25°C, unless otherwise noted.)
PARAMETERSYM B O L CONDITIONSMINTYPMAXUNITS
TRANSFER CHARACTERISTICSBandwidthGain = 60dB150250MHz
CAZ = open500Low-Frequency CutoffCAZ = 0.1μF0.5kHz
LOSS-OF-SIGNAL SPECIFICATIONS (Notes 2, 4, 6)LOS Sensitivity Range0Ω ≤ RTH ≤ 2kΩ220mVP-P
LOS Hysteresis10log (VDEASSERT/VASSERT)1.42dB
LOS Assert/Deassert Time(Note 7)2.380.0μs
RTH = 0Ω, low setting0.50.91.3
RTH = 1kΩ, medium setting4.86.68.3LOS Assert Level
RTH = 2kΩ, high setting121722
mVP-P
RTH = 0Ω, low setting1.11.51.9
RTH = 1kΩ, medium setting8.010.813.5LOS Deassert Level
RTH = 2kΩ, high setting202836
mVP-P
Signal-Dectect Filter ResistanceRSDPin 7142026kΩ
Figure 1. Signal Levels for LOS Assert/Deassert Time
Measurement
TIME
VIN
MAXIMUM DEASSERT LEVEL1dB
6dBMAXIMUM POWER-DETECT WINDOW
SIGNAL ON
SIGNAL OFF
MINIMUM ASSERT LEVEL
2.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal DetectorTypical Operating Characteristics(VCC= 3.3V, PECL outputs terminated with 50Ωto VCC- 2V, RTH= 100Ω, CAZ= 0.1μF, CSD= 1nF, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES PECL OUTPUT CURRENTS)AX3645 toc01
TEMPERATURE (°C)
(m3510-15
VCC = 5.0V
VCC = 3.3V
OUTPUT EYE DIAGRAM
(VIN = 1mVP-P, 155Mbps, 223 - 1PRBS)MAX3654 toc02
1ns/div
200mV/
div
OUTPUT EYE DIAGRAM
(VIN = 1500mVP-P, 155Mbps, 223 - 1PRBS)MAX3645 toc03
1ns/div
200mV/
div
TRANSFER FUNCTIONAX3654 toc04
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
(m
-P)10.1
RTH = 1kΩ
RTH = 2kΩ
RTH = 100Ω
RTH = 0Ω
BIT-ERROR RATIO vs.
DIFFERENTIAL INPUT VOLTAGEAX3645 toc05
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
155Mbps, 223 - 1 PRBS
INPUT-REFERRED RMS NOISE
vs. TEMPERATUREAX3645 toc06
TEMPERATURE (°C)
(μ3510-15
VCC = +5.0V
VCC = +3.3V
SMALL-SIGNAL GAIN vs. RTH3645 toc07
RTH (kΩ)
(V
) (d
VIN = 0.1mVP-P
LOSS-OF-SIGNAL THRESHOLD
vs. RTH (VCC = +3.3V AND +5.0V)3645 toc08
RTH (kΩ)
IN
(m
-P)
LOS DEASSERT
LOS ASSERT
155Mbps, 223 - 1 PRBS
LOSS-OF-SIGNAL HYSTERESIS
vs. TEMPERATUREAX3645 toc09
TEMPERATURE (°C)
(D
) (d3510-15
RTH = 2kΩ
RTH = 100ΩRTH = 1kΩ
155Mbps, 223 - 1 PRBS
.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal DetectorTypical Operating Characteristics (continued)(VCC= 3.3V, PECL outputs terminated with 50Ωto VCC- 2V, RTH= 100Ω, CAZ= 0.1μF, CSD= 1nF, TA= +25°C, unless otherwise noted.)
LOSS-OF-SIGNAL WITH SQUELCH
(155Mbps, 223 - 1PRBS)MAX3654 toc10
10μs/div
LOS
VOUT
VIN
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGEAX3645 toc11
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
(p
0.110,000
155Mbps 0011 PATTERN
DATA OUTPUT TRANSITION TIME
vs. DIFFERENTIAL INPUT VOLTAGE3645 toc12
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
(n
0.110,000
Detailed DescriptionThe MAX3645 consists of gain stages, offset correction,
power detector, LOS indicators, and PECL output buffers.
See Figure 2 for the functional diagram.
Data InputThe data inputs have a single-ended input resistance of
4.8kΩand are internally DC-biased to VCC- 0.87V (see
Figure 3). External capacitors are required to AC-cou-
ple the data signals. Pattern-dependent jitter is mini-
mized by using coupling capacitor values large enough
to pass the lowest frequencies of interest (consecutive
ones and zeros) with the given input resistance.
Typically, 0.1μF coupling capacitors yield a -3dB fre-
quency of 354Hz. Capacitor tolerance and input resis-
tance variation (3.3kΩto 6.4kΩ) must be considered to
accurately calculate the -3dB frequency. Capacitor val-
ues should be chosen that set the -3dB frequency at
least a factor of 10 below the lowest frequency of inter-
est. A capacitor value of 0.1μF is recommended.
Gain Stage and Offset CorrectionThe limiting amplifier provides approximately 74dB
(RTH= 100Ω) of gain. This large gain makes the ampli-
fier susceptible to small DC offsets in the signal path.
To correct DC offsets, the amplifier has an internal feed-
back loop that acts as a DC autozero circuit. By cor-
recting the DC offsets, the limiting amplifier improves
receiver sensitivity and power-detector accuracy.
2.97V to +5.5V, 125Mbps to 200Mbps Limitingplifier with Loss-of-Signal Detector
PIN
MINDSPEED
MC2045-2
MC2045-2Y
PIN NAME
MAXIM
MAX3645
PIN NAME
FUNCTIONCAZ-CAZ2
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ1 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ1 and CAZ2 pins are shorted together.CAZ+CAZ1
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ2 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ2 and CAZ1 pins are shorted together.GNDAGNDAAnalog Supply Ground. Must be at the same potential as the GNDE pin.DINDIN+Positive Data InputDINDIN-Negative Data InputVCCAVCCA+2.97V to +5.5V Analog Supply Voltage. Must be at same potential as the VCCE pin.CFCSDS i g nal - D etect- Fi l ter C ap aci tor C onnecti on. C onnect the C S D cap aci tor b etw een C S D and V C C A .JAMDIS
Disable Input, PECL or CMOS Compatible. Data outputs are held to a static logic 0 when DIS is
asserted high. The LOS function remains active when the outputs are disabled. When
connected to the LOS pin, an automatic squelch function is enabled.STLOS
Positive Loss-of-Signal Output, PECL. LOS is high when the level of the input signal drops
below the threshold set by the TH input. LOS is low when the signal level is above the
threshold. LOS can be connected directly to DIS for automatic squelch.STLOS
Negative Loss-of-Signal Output, PECL. LOS is low when the level of the input signal drops
below the threshold set by the TH input. LOS is high when the signal level is above the
threshold.GNDEGNDEDigital Supply Ground. Must be at the same potential as the GNDA pin.DOUTDOUT-Negative Data Output, PECL. A high at DIS forces DOUT- high.DOUTDOUT+Positive Data Output, PECL. A high at DIS forces DOUT+ low.VCCEVCCE+2.97V to +5.5V Digital Supply Voltage. Must be at the same potential as the VCCA pin.NCN.C.No ConnectionVSETTHLoss-of-Signal Threshold Pin. Resistor (RTH) to ground sets the LOS threshold. This pin cannot
be left open.
Pin Description
