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MAX3421EEHJ+
USB Peripheral/Host Controller with SPI Interface
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
EVALUATION KIT AVAILABLE
General Description
The MAX3421E USB peripheral/host controller contains
the digital logic and analog circuitry necessary to
implement a full-speed USB peripheral or a full-/low-
speed host compliant to USB specification rev 2.0. A
built-in transceiver features ±15kV ESD protection and
programmable USB connect and disconnect. An inter-
nal serial interface engine (SIE) handles low-level USB
protocol details such as error checking and bus retries.
The MAX3421E operates using a register set accessed
by an SPI interface that operates up to 26MHz. Any SPI
master (microprocessor, ASIC, DSP, etc.) can add USB
peripheral or host functionality using the simple 3- or 4-
wire SPI interface.
The MAX3421E makes the vast collection of USB
peripherals available to any microprocessor, ASIC, or
DSP when it operates as a USB host. For point-to-point
solutions, for example, a USB keyboard or mouse inter-
faced to an embedded system, the firmware that oper-
ates the MAX3421E can be simple since only a
targeted device is supported.
Internal level translators allow the SPI interface to run at
a system voltage between 1.4V and 3.6V. USB-timed
operations are done inside the MAX3421E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3421E includes eight general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3421E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
TQFP package (5mm x 5mm) and a 32-pin TQFN pack-
age (5mm x 5mm).
Applications
FeaturesMicroprocessor-Independent USB SolutionSoftware Compatible with the MAX3420E USB
Peripheral Controller with SPI InterfaceComplies with USB Specification Revision 2.0
(Full-Speed 12Mbps Peripheral, Full-/Low-Speed
12Mbps/1.5Mbps Host)Integrated USB TransceiverFirmware/Hardware Control of an Internal D+
Pullup Resistor (Peripheral Mode) and D+/D-
Pulldown Resistors (Host Mode)Programmable 3- or 4-Wire, 26MHz SPI InterfaceLevel Translators and VLInput Allow Independent
System Interface VoltageInternal Comparator Detects VBUSfor Self-
Powered Peripheral ApplicationsESD Protection on D+, D-, and VBCOMPInterrupt Output Pin (Level- or Programmable-
Edge) Allows Polled or Interrupt-Driven SPI
InterfaceEight General-Purpose Inputs and Eight General-
Purpose OutputsInterrupt Signal for General-Purpose Input Pins,
Programmable Edge PolarityIntelligent USB SIEAutomatically Handles USB Flow Control and
Double BufferingHandles Low-Level USB Signaling DetailsContains Timers for USB Time-Sensitive
Operations so SPI Master Does Not Need to Time
EventsSpace-Saving Lead-Free TQFP and TQFN
Packages (5mm x 5mm)Embedded Systems
Medical Devices
Microprocessors and
DSPs
Custom USB Devices
Cameras
Desktop Routers
PLCs
Set-Top Boxes
PDAs
MP3 Players
Instrumentation
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARKAX 3421E E H J+ - 40°C to + 85°C 32 TQFP —AX 3421E E TJ+ - 40°C to + 85°C 32 TQFN - E P *BTBG
Ordering Information
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Features in Host OperationEleven Registers (R21–R31) are Added to the
MAX3420E Register Set to Control Host OperationHost Controller Operates at Full Speed or Low
SpeedFIFOS
SNDFIFO: Send FIFO, Double-Buffered 64-Byte
RCVFIFO: Receive FIFO, Double-Buffered 64-ByteHandles DATA0/DATA1 Toggle Generation and
CheckingPerforms Error Checking for All TransfersAutomatically Generates SOF (Full-Speed)/EOP
(Low-Speed) at 1ms IntervalsAutomatically Synchronizes Host Transfers with
Beginning of Frame (SOF/EOP)Reports Results of Host RequestsSupports USB HubsSupports ISOCHRONOUS TransfersSimple Programming
SIE Automatically Generates Periodic SOF
(Full-Speed) or EOP (Low-Speed) Frame
Markers
SPI Master Loads Data, Sets Function Address,
Endpoint, and Transfer Type, and Initiates the
Transfer
MAX3421E Responds with an Interrupt and
Result Code Indicating Peripheral Response
Transfer Request Can be Loaded Any Time
SIE Synchronizes with Frame Markers
For Multipacket Transfers, the SIE
Automatically Maintains and Checks the
Data Toggles
Features in Peripheral OperationBuilt-In Endpoint FIFOS
EP0: CONTROL (64 bytes)
EP1: OUT, BULKor INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, BULKor INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, BULKor INTERRUPT(64 Bytes)Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrent with USB TransfersSETUP Data Has its Own 8-Byte FIFO, Simplifying
Firmware
The MAX3421E connects to any microprocessor (µP)
using 3 or 4 interface pins (Figure 1). On a simple
microprocessor without SPI hardware, these can be
bit-banged general-purpose I/O pins. Eight GPIN and
eight GPOUT pins on the MAX3421E more than
replace the µP pins necessary to implement the inter-
face. Although the MAX3421E SPI hardware includes
separate data-in (MOSI, master-out, slave-in) and data-
out (MISO, master-in, slave-out) pins, the SPI interface
can also be configured for the MOSI pin to carry bidi-
rectional data, saving an interface pin. This is referred
to as half-duplex mode.
Typical Application Circuits
3.3V
REGULATOR
SPI
3, 4
INT
USBμPMAX3421E
Figure 1. The MAX3421E Connects to Any Microprocessor
Using 3 or 4 Interface Pins
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
3.3V
REGULATORPOWER RAIL
ASIC,
DSP,
ETC.
SPI
3, 4
INT
MAX3421EUSB
Figure 2. The MAX3421E Connected to a Large Chip
3.3V
REGULATOR
MISO
LOCAL
GND
LOCAL
POWER
INT
MAX3421E
SCLK
MOSI
MICRO
ASIC
DSP
USB
Figure 3. Optical Isolation of USB Using the MAX3421E
MICRO,
ASIC,
DSP
USB
PERIPHERAL
USB
"A"
USB
"B"
VBUS
SWITCH
FAULT
SPI
3, 4
INT
VBUS
GND
VBUS
POWER
ON/OFF
3.3V
REGULATOR
MAX3421E
Figure 4. The MAX3421E in an Embedded Host Application
Two MAX3421E features make it easy to connect to
large, fast chips such as ASICs and DSPs (Figure 2).
First, the SPI interface can be clocked up to 26MHz.
Second, the VLpin and internal level translators allow
running the system interface at a lower voltage than
the 3.3V required for VCC.
The MAX3421E provides an ideal method for electrically
isolating a USB interface (Figure 3). USB employs flow
control in which the MAX3421E automatically answers
host requests with a NAK handshake, until the micro-
processor completes its data-transfer operations over
the SPI port. This means that the SPI interface can run
at any frequency up to 26MHz. Therefore, the designer
is free to choose the interface operating frequency and
to make opto-isolator choices optimized for cost or per-
formance.
Figure 4 shows a block diagram for a system in which
the MAX3421E operates as a USB host. A USB host
supplies 5V power to the VBUSpin of the USB “A” con-
nector to power USB peripherals. A system that pro-
vides power to an external peripheral should use
protection circuitry on the power pin to prevent an
external overcurrent situation from damaging the sys-
tem. A VBUSswitch, such as the MAX4789, provides
power control plus two additional features: it limits the
current delivered to the peripheral (for example to
200mA), and it indicates a fault (overcurrent) condition
to the SPI controller. Maxim offers a variety of VBUS
switches with various current limits and features.
Consult the Maxim website for details.
A 3.3V regulator (for example, the MAX6349TL) powers
the MAX3421E, and optionally the system controller. If
the system controller operates with a lower voltage, the
MAX3421E SPI and I/O interface can run at the lower
voltage by connecting the system voltage (for exam-
ple, 2.5V or 1.8V) to the MAX3421E VLpin.
Typical Application Circuits (continued)
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Functional Diagram
GPIN0
1V TO 3V
VBCOMP
VCC
RGPIN
VBUS
COMP
MISO
SCLK
INT
SPI SLAVE
INTERFACE
USB SIE
(SERIAL-
INTERFACE
ENGINE)
FULL-SPEED/
LOW-SPEED
USB
TRANSCEIVER
RESET
LOGIC
1.5kΩ
INTERNAL
POR
RESXIXO
POWER
DOWN
OSC
AND
4x PLL
48MHz
ESD
PROTECTION
ESD
PROTECTION
GPX
OPERATESOF
BUSACT/
INIRQ
MUX23
MOSI
VBUS_DET
ENDPOINT
BUFFERS
MAX3421E
GND
GPIN1
GPIN2
GPIN3
GPIN4
GPIN5
GPIN6
GPIN7
GPOUT0
GPOUT1
GPOUT2
GPOUT3
GPOUT4
GPOUT5
GPOUT6
GPOUT7
RIN
15kΩ
15kΩ
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Pin Description
PINNAMEINPUT/
OUTPUTFUNCTIONGPIN7InputGeneral-Purpose Input. GPIN7–GPIN0 are connected to VL with internal pullup resistors.
GPIN7–GPIN0 logic levels are referenced to the voltage on VL.
2VLInputLevel-Translator Voltage Input. Connect VL to the system’s 1.4V to 3.6V logic-level power
supply. Bypass VL to ground with a 0.1µF capacitor as close to VL as possible.
3, 19GNDInputGroundGPOUT0GPOUT1GPOUT2GPOUT3GPOUT4GPOUT5GPOUT6GPOUT7
OutputGeneral-Purpose Push-Pull Outputs. GPOUT7–GPOUT0 logic levels are referenced to the
voltage on VL.RESInput
Device Reset. Drive RES low to clear all of the internal registers except for PINCTL (R17),
USBCTL (R15), and SPI logic. The logic level is referenced to the voltage on VL. (See the
Device Reset section for a description of resets available on the MAX3421E.) Note: The
MAX3421E is internally reset if either V C C or V L is not present. The register file is not accessible
under these conditions.SCLKInputP I S er i al - C l ock Inp ut. An exter nal S P I m aster sup p l i es S C LK w i th fr eq uenci es up to 26M H z. Theog i c l evel i s r efer enced to the vol tag e on V L . D ata i s cl ocked i nto the S P I sl ave i nter face on thei si ng ed g e of S C LK. D ata i s cl ocked out of the S P I sl ave i nter face on the fal l i ng ed g e of S C LK.SSInput
SPI Slave Select Input. The SS logic level is referenced to the voltage on VL. When SS is driven
high, the SPI slave interface is not selected, the MISO pin is high impedance, and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition and ends with a
low-to-high SS transition.MISOOutputSPI Serial-Data Output (Master-In Slave-Out). MISO is a push-pull output. MISO is tri-stated in
half-duplex mode or when SS = 1. The MISO logic level is referenced to the voltage on VL.MOSI
Input or
Input/
Output
SPI Serial-Data Input (Master-Out Slave-In). The logic level on MOSI is referenced to the
voltage on VL. MOSI can also be configured as a bidirectional MOSI/MISO input and output.
(See Figure 15.)GPXOutputener al - P ur p ose M ul ti p l exed P ush- P ul l O utp ut. The i nter nal M AX 3421E si g nal that ap p ear s onP X i s p r og r am m ab l e b y w r i ti ng to the G P X B and G P X A b i ts of the P IN C TL ( R17) r eg i ster and theE P IRQ b i t of the M O D E ( R27) r eg i ster . GP X i nd i cates one of fi ve si g nal s ( see the G P X secti on) .INTOutput
Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage on VL and is
a push-pull output with programmable polarity. In level mode, INT is open-drain and active low.
Set the IE bit in the CPUCTL (R16) register to enable INT.D-Input/
Output
USB D- Signal. Connect D- to a USB connector through a 33Ω ±1% series resistor. A
switchable 15kΩ D- pulldown resistor is internal to the device.
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Pin Description (continued)
PINNAMEINPUT/
OUTPUTFUNCTIOND+Input/
Output
USB D+ Signal. Connect D+ to a USB connector through a 33Ω ±1% series resistor. A
switchable 1.5kΩ D+ pullup resistor and 15kΩ D+ pulldown resistor is internal to the device.VBCOMPInput
VBUS Comparator Input. VBCOMP is internally connected to a voltage comparator to allow the
SPI master to detect (through an interrupt or checking a register bit) the presence or loss of
power on VBUS. Bypass VBCOMP to ground with a 1.0µF ceramic capacitor. VBCOMP is pulled
down to ground with RIN (see Electrical Characteristics).VCCInputU S B Tr anscei ver and Log i c C or e P ow er - S up p l y Inp ut. C onnect V C C to a p osi ti ve 3.3V p ow er
sup p l y. Byp ass V C C to g r ound w i th a 1.0µF cer am i c cap aci tor as cl ose to the V C C p i n as p ossi b l e.XIInputCrystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz ±0.25% crystal
and a load capacitor to GND. XI can also be driven by an external clock referenced to VCC.XOOutputC r ystal Osci l l ator O utp ut. C onnect X O to the other si d e of a p ar al l el r esonant 12M H z ± 0.25% cr ystal
and a l oad cap aci tor to GN D . Leave X O unconnected i f X I i s d r i ven w i th an exter nal sour ce.GPIN0GPIN1GPIN2GPIN3GPIN4GPIN5GPIN6
InputGeneral-Purpose Inputs. GPIN7–GPIN0 are connected to VL with internal pullup resistors.
GPIN7–GPIN0 logic levels are referenced to the voltage on VL.EPInputE xp osed P ad , C onnected to G r ound . C onnect E P to G N D or l eave unconnected . E P i s l ocated on
the b ottom of the TQ FN p ackag e. The TQFP p ackag e d oes not have an exp osed p ad .
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Register Description
The SPI master controls the MAX3421E by reading and
writing 26 registers in peripheral mode (see Table 1) or
reading and writing 23 registers in host mode (see Table
2). Setting the HOST bit in the MODE (R27) register con-
figures the MAX3421E for host operation. When operating
as a USB peripheral, the MAX3421E is register-compati-
ble with the MAX3420E with the additional features listed
in Note 1b below Table 1. For a complete description of
register contents, refer to the MAX3421E Programming
Guide on the Maxim website.
A register access consists of the SPI master first writing
an SPI command byte followed by reading or writing the
contents of the addressed register. All SPI transfers are
MSB first. The command byte contains the register
address, a direction bit (read = 0, write = 1), and the
ACKSTAT bit (Figure 5). The SPI master addresses the
MAX3421E registers by writing the binary value of the
register number in the Reg4 through Reg0 bits of the
command byte. For example, to access the IOPINS1
(R20) register, the Reg4 through Reg0 bits would be as
follows: Reg4 = 1, Reg3 = 0, Reg2 = 1, Reg1 = 0, Reg0
= 0. The DIR (direction) bit determines the direction for
the data transfer. DIR = 1 means the data byte(s) are
written to the register, and DIR = 0 means the data
byte(s) are read from the register. The ACKSTAT bit sets
the ACKSTAT bit in the EPSTALLS (R9) register (periph-
eral mode only). The SPI master sets this bit to indicate
that it has finished servicing a CONTROL transfer. Since
the bit is frequently used, having it in the SPI command
byte improves firmware efficiency. The ACKSTAT bit is
ignored in host mode. In SPI full-duplex mode, the
MAX3421E clocks out eight USB status bits as the com-
mand byte is clocked in (Figures 6, 7). In half-duplex
mode, these status bits are accessed as register bits.
The first five registers (R0–R4) address FIFOs in both
peripheral and host modes. Repeated accesses to these
registers freeze the internal register address so that mul-
tiple bytes may be written to or read from a FIFO in the
same SPI access cycle (while SSis low). Accesses to
registers R5–R19 increment the internal register address
for every byte transferred during the SPI access cycle.
Accessing R20 freezes access at that register, access-
ing R21–R31 increments the internal address, and
repeated accesses to R31 freeze at R31.
The register maps in Table 1 and Table 2 show which
register bits apply in peripheral and host modes.
Register bits that do not apply to a particular mode are
shown as zeros. These register bits read as zero values
and should not be written to with a logic 1.
Register Map in Peripheral Mode
The MAX3421E maintains register compatibility with the
MAX3420E when operating in USB peripheral mode
(MAX3421E HOST bit is set to 0 (default)). Firmware
written for the MAX3420E runs without modification on
the MAX3421E. To support new MAX3421E features,
the register set includes new bits, described in Note 1b
at the bottom of Table 1.
Register Map in Host Mode
As Table 2 shows, in host mode (HOST = 1), some
MAX3420E registers are renamed (for example R1
becomes RCVFIFO), some are not used (shown with
zeros), and some still apply to host mode. In addition, 11
registers (R21–R31) add the USB host capability.
Figure 7. USB Status Bits Clocked Out as First Byte of Every Transfer in Host Mode (Full-Duplex Mode Only)
STATUS BITS (HOST MODE)b6b5b4b3b2b1b0
HXFRDNIRQFRAMEIRQCONNIRQSUSDNIRQSNDBAVIRQRCVDAVIRQRSMREQIRQBUSEVENTIRQ
*The ACKSTAT bit is ignored in host mode.
Figure 5. SPI Command Byteb6b5b4b3b2b1b0
Reg4Reg3Reg2Reg1Reg00DIRACKSTAT*
Figure 6. USB Status Bits Clocked Out as First Byte of Every Transfer in Peripheral Mode (Full-Duplex Mode Only)
STATUS BITS (PERIPHERAL MODE)b6b5b4b3b2b1b0
SUSPIRQURESIRQSUDAVIRQIN3BAVIRQIN2BAVIRQOUT1DAVIRQOUT0DAVIRQIN0BAVIRQ
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b)EG NAMEb 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c EP0 F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C EP1 O U T F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C EP2 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C EP3 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C SU D F IF O b 7b 6b 5b 4b 3b 2b 1b 0RS C EP0 B C 0b 6b 5b 4b 3b 2b 1b 0RS C EP1 O U T B C 0b 6b 5b 4b 3b 2b 1b 0RS C EP2 IN B C 0b 6b 5b 4b 3b 2b 1b 0RS C EP3 IN B C 0b 6b 5b 4b 3b 2b 1b 0RS C EPST A L L S0AC KS TATS TLS TATS TLE P 3IN S TLE P 2IN S TLE P 1OU TS TLE P 0OU TS TLE P 0IN RS C
R10C L R T O G SE P 3D IS ABE P 2D IS ABE P 1D IS ABC TG E P 3IN C TG E P 2IN C TG E P 1OU T00RS C
R11EPI R Q 00S U D AV IRQIN 3BAV IRQ IN 2BAV IRQ OU T1D AV IRQOU T0D AV IRQIN 0BAV IRQ RC
R12EPI EN 00S U D AV IE IN 3BAV IE IN 2BAV IE OU T1D AV IE OU T0D AV IE IN 0BAV IE RS C
R13U SB IR Q U RE S D N IRQ V BU S IRQN OV BU S IRQ S U S P IRQU RE S IRQBU S AC TIRQ RWU D N IRQOS C OKIRQRC
R14U SB IEN U RE S D N IE V BU S IE N OV BU S IE S U S P IE U RE S IE BU S AC TIE RWU D N IE OS C OKIE RS C
R15U SB C T L H OS C S TE N V BG ATE C H IP RE S P WRD OWN C ON N E C TS IG RWU 00RS C
R16C PU C T L P U LS E WID 1P U LS E WID 000000IE RS C
R17PIN C T L E P 3IN AKE P 2IN AKE P 0IN AKFD U P S P IIN TLE V E LP OS IN TGP X BGP X ARS C
R18R EVISIO N 00010011R
R19F N A D D R 0b 6b 5b 4b 3b 2b 1b 0R
R20IO PIN S1 GP IN 3GP IN 2GP IN 1GP IN 0GP O U T3GP O U T2GP O U T1GP O U T0RS C
R21IOPINS2GP IN 7GP IN 6GP IN 5GP IN 4GP O U T7GP O U T6GP O U T5GP O U T4RS C
R22GPINIRQGP IN IRQ7GP IN IRQ6GP IN IRQ5GP IN IRQ4GP IN IRQ3GP IN IRQ2GP IN IRQ1GP IN IRQ0RS C
R23GPINIENGP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2GP IN IE N 1GP IN IE N 0RS C
R24GPINPOLGP IN P OL7GP IN P OL6GP IN P OL5GP IN P OL4GP IN P OL3GP IN P OL2GP IN P OL1GP IN P OL0RS C
R25—00000000—
R26—00000000—
R27MODE000S E P IRQ000H OS T = 0RS C
R28—00000000—
R29—00000000—
R30—00000000—
R31—00000000—
Note 1a:The acc (access) column indicates how the SPImaster can access the register.
R = read, RC = read or clear, RSC = read, set, or clear.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Note 1b:In peripheral mode, the MAX3421E performs identically to the MAX3420E with the following enhancements:
1) R16 adds the PULSEWID0 and PULSEWID1 bits to control the INT pulse width in edge interrupt mode
(see Figure 12.) These bits default to the MAX3420E setting of 10.6µs.
2) R21 adds four more GPIO bits.
3) R22 and R23 add general-purpose input pins to the interrupt system. R24 controls the edge polarity.
4) R27 controls the peripheral/host mode and the SEPIRQ bit.
5) When [GPXB:GPXA] = [1:0] and the bit SEPIRQ = 1 (R27 bit 4), the GPX output replaces the BUSACT
signal with a second IRQ pin dedicated to the GPIN pin interrupts.
Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2)EG NAMEb 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a c c —00000000—RCVFIFOb 7b 6b 5b 4b 3b 2b 1b 0RS C SNDFIFOb 7b 6b 5b 4b 3b 2b 1b 0RS C —00000000—SUDFIFOb 7b 6b 5b 4b 3b 2b 1b 0RS C —00000000—RCVBC0BC 6BC 5BC 4BC 3BC 2BC 1BC 0RS C SNDBC0BC 6BC 5BC 4BC 3BC 2BC 1BC 0RS C —00000000——00000000—
R10—00000000—
R11—00000000—
R12—00000000—
R13USBIRQ0V BU S IRQN OV BU S IRQ 0000OS C OKIRQRC
R14USBIEN0V BU S IE N OV BU S IE 0000OS C OKIE RS C
R15USBCTL00C H IP RE S P WRD OWN 0000RS C
R16CPUCTLP U LS E WID 1P U LS E WID 000000IE RS C
R17PINCTLE P 3IN AKE P 2IN AKE P 0IN AKFD U P S P IIN TLE V E LP OS IN TGP X BGP X ARS C
R18REVISION00010011R
R19—00000000—
R20IOPINS1GP IN 3GP IN 2GP IN 1GP IN 0GP O U T3GP O U T2GP O U T1GP O U T0RS C
R21IOPINS2GP IN 7GP IN 6GP IN 5GP IN 4GP O U T7GP O U T6GP O U T5GP O U T4RS C
R22GPINIRQGP IN IRQ7GP IN IRQ6GP IN IRQ5GP IN IRQ4GP IN IRQ3GP IN IRQ2GP IN IRQ1GP IN IRQ0RC
R23GPINIENGP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2GP IN IE N 1GP IN IE N 0RS C
R24GPINPOLGP IN P OL7GP IN P OL6GP IN P OL5GP IN P OL4GP IN P OL3GP IN P OL2GP IN P OL1GP IN P OL0RS C
R25HIRQH X FRD N IRQ FRAM E IRQC ON N IRQS U S D N IRQS N D BAV IRQ RC V D AV IRQ RS M RE QIRQ BU S E V E N TIRQRC
R26HIENH X FRD N IE FRAM E IE C ON N IE S U S D N IE S N D BAV IE RC V D AV IE RS M RE QIE BU S E V E N TIE RS C
R27MODED P P U LLD N D M P U LLD N D E LAY IS OS E P IRQS OFKAE N ABH U BP RE S P E E D H OS T = 1RS C
R28PERADDR0b 6b 5b 4b 3b 2b 1b 0RS C
R29HCTLS N D TOG1S N D TOG0RC V TOG1RC V TOG0S IG RS M BU S S AM P LE FRM RS TBU S RS TLS
R30HXFRH S IS O OU TN IN S E TU P E P 3E P 2E P 1E P 0LS
Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b) (continued)
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
MAX3421E
TQFP
(5mm x 5mm)
TOP VIEW
GPOUT0GPOUT1GPOUT2GPOUT3
GPIN7D-XIGNDINT
GPIN2672422201918
GPIN3
GPIN4
SCLK
RES
GPOUT7
GND
VBCOMP10GPIN5GPOUT69GPIN6GPOUT5
GPIN115MISOGPIN016MOSI
GPOUT4
GPX
Pin Configurations
Note 2:The acc (access) column indicates how the SPI master can access the register.
R = read; RC = read or clear; RSC = read, set, or clear; LS = load-sensitive.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.
Writing to an LS register initiates a host operation based on the contents of the register.
MAX3421E
TQFN
(5mm x 5mm)
TOP VIEW OF BOTTOM LEADS
GPOUT0GPOUT1GPOUT2GPOUT3
GPIN7D-XIGNDINT
GPIN2672422201918
GPIN3
GPIN4
SCLK
RES
GPOUT7
GND
VBCOMP10GPIN5GPOUT69GPIN6GPOUT5
GPIN115MISOGPIN016MOSI
GPOUT4
GPX
*EXPOSED PAD CONNECTED TO GROUND
*EP
Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2) (continued)
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3V to +3.6V, VL= +1.4V to +3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, VL=
+2.5V, TA= +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
VCC.........................................................................-0.3V to +4V.............................................................................-0.3V to +4V
VBCOMP .................................................................-0.3V to +6V
D+, D-, XI, XO ............................................-0.3V to (VCC + 0.3V)
SCLK, MOSI, MISO, SS, RES, GPOUT7–GPOUT0,
GPIN7–GPIN0, GPX, INT..........................-0.3V to (VL+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFN (derate 21.3mW/°C above +70°C).......1702mW
32-Pin TQFP (derate 13.1mW/°C above +70°C)........1047mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC CHARACTERISTICS
Supply Voltage VCCVCC3.03.33.6V
Logic-Interface Voltage VLVL1.43.6V
VCC Supply CurrentICC
Continuously transmitting on D+ and D- at
12Mbps, CL = 50pF on D+ and D- to GND,
CONNECT = 0mA
VL Supply CurrentILSCLK toggling at 20MHz, SS = low,
GPIN7–GPIN0 = 02.3510mA
VCC Supply Current During IdleICCIDD+ = high, D- = low8.715mA
VCC Suspend Supply CurrentICCSUSCONNECT = 0, PWRDOWN = 13060µAL S usp end S up p l y C urr entILSUSCONNECT = 0, PWRDOWN = 12050µA
LOGIC-SIDE I/O
ILOAD = +1mAV L - 0.4
ILOAD = +5mA, VL < 2.5V (Note 4)V L - 0.45MISO, GPOUT7–GPOUT0, GPX,
INT Output High VoltageVOH
ILOAD = +10mA, VL ≥ 2.5V (Note 4)V L - 0.4
ILOAD = -1mA0.4
ILOAD = -20mA, VL < 2.5V (Note 4)0.6MISO, GPOUT7–GPOUT0, GPX,
INT Output Low VoltageVOL
ILOAD = -20mA, VL ≥ 2.5V (Note 4)0.4
SCLK, MOSI, GPIN7–GPIN0, SS,
RES Input High VoltageVIH2/3 x VLV
SCLK, MOSI, GPIN7–GPIN0, SS,
RES Input Low VoltageVIL0.4V
SCLK, MOSI, SS, RES Input
Leakage CurrentIIL-1+1µA
GP IN 7–GP IN 0 P ul l up Resi stor to V LRGPIN102030kΩ
TRANSCEIVER SPECIFICATIONS
Differential-Receiver Input
Sensitivity|VD+ - VD-|0.2V
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3V to +3.6V, VL= +1.4V to +3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, VL=
+2.5V, TA= +25°C.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Differential-Receiver Common-
Mode Voltage0.82.5V
Single-Ended Receiver Input Low
VoltageVIL0.8V
Single-Ended Receiver Input
High VoltageVIH2.0V
Single-Ended Receiver
Hysteresis Voltage0.2V
D+, D- Output Low VoltageVOLRL = 1.5kΩ from D+ to 3.6V0.3V
D+, D- Output High VoltageVOHRL = 15kΩ from D+ and D- to GND2.83.6V
Driver Output Impedance
Excluding External Resistor(Note 4)2711Ω
D+ Pullup ResistorREXT = 33Ω1.4251.51.575kΩ
D+, D- Pulldown ResistorREXT = 33Ω14.251515.75kΩ
D+, D- Input Impedance300kΩ
ESD PROTECTION (D+, D-, VBCOMP)
Human Body Model1µF ceramic capacitors from VBCOMP and
VCC to GND±15kV
IEC 61000-4-2 Air-Gap Discharge1µF ceramic capacitors from VBCOMP and
VCC to GND±12kV
IEC 61000-4-2 Contact Discharge1µF ceramic capacitors from VBCOMP and
VCC to GND±8kV
THERMAL SHUTDOWN
Thermal-Shutdown Low-to-High+160°C
Thermal-Shutdown High-to-Low+140°C
CRYSTAL OSCILLATOR SPECIFICATIONS (XI, XO)
XI Input High Voltage2/3 x VC C VCCV
XI Input Low Voltage0.4V
XI Input Current10µA
XI, XO Input Capacitance3pF
VBCOMP COMPARATOR SPECIFICATIONS
VBCOMP Comparator ThresholdVTH1.02.03.0V
VBCOMP Comparator HysteresisVHYS375mV
VBCOMP Comparator Input
ImpedanceRIN100kΩ
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Note 3:Parameters are 100% production tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 4:Guaranteed by bench testing. Limits are not production tested.
Note 5:At VL= 1.4V to 2.5V, derate all the SPI timing characteristics by 50%. Not production tested.
Note 6:The minimum period is derived from SPI timing parameters.
Note 7:Time-to-exit suspend is dependent on the crystal used.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
USB TRANSMITTER TIMING CHARACTERISTICS (FULL-SPEED MODE)
D+, D- Rise TimetRISECL = 50pF, Figures 8 and 9420ns
D+, D- Fall TimetFALLCL = 50pF, Figures 8 and 9420ns
Rise-/Fall-Time MatchingCL = 50pF, Figures 8 and 9 (Note 4)90110%
Output-Signal Crossover VoltageCL = 50pF, Figures 8 and 9 (Note 4)1.32.0V
USB TRANSMITTER TIMING CHARACTERISTICS (HOST LOW-SPEED MODE)
D+, D- Rise TimetRISE200pF ≤ CL ≤ 600pF, Figures 8 and 975300ns
D+, D- Fall TimetFALL200pF ≤ CL ≤ 600pF, Figures 8 and 975300ns
Rise-/Fall-Time Matching200p F ≤ C L ≤ 600p F, Fi g ur es 8 and 980120%
Output-Signal Crossover Voltage200p F ≤ C L ≤ 600p F, Fi g ur es 8 and 91.32.0V
SPI BUS TIMING CHARACTERISTICS (VL = 2.5V) (Figures 10 and 11) (Note 5)
VL > 2.5V38.4S eri al C l ock ( SC LK) P eri od ( N ote 6)tCPVL = 1.4V77.7ns
SCLK Pulse-Width HightCH17ns
SCLK Pulse-Width LowtCL17ns
SS Fall to MISO ValidtCSS20ns
SS Leading Time Before the First
SCLK EdgetL30ns
SS Trailing Time After the Last
SCLK EdgetT30ns
Data-In Setup TimetDS5ns
Data-In Hold TimetDH10ns
SS Pulse HightCSW200ns
SCLK Fall to MISO Propagation
DelaytDO14.2ns
SCLK Fall to MOSI Propagation
DelaytDI14.2ns
SCLK Fall to MOSI DrivetON3.5ns
SS High to MOSI High
ImpedancetOFF20ns
SUSPEND TIMING CHARACTERISTICS
Time-to-Enter SuspendPWRDOWN = 1 to oscillator stop5µs
Time-to-Exit SuspendPWRDOWN = 1 to 0 to OSCOKIRQ (Note 7)3ms
TIMING CHARACTERISTICS
(VCC= +3V to +3.6V, VL= +1.4V to +3.6V, TA= TMINto TMAX, unless otherwise noted. Typical values are at VCC= +3.3V, VL=
+2.5V, TA= +25°C.) (Note 3)
MAX3421E
USB Peripheral/Host Controller
with SPI Interface
Test Circuits and Timing Diagrams
Figure 8. Rise and Fall Times
VOL
VOH
tRISEtFALL
90%
10%
Figure 9. Load for D+/D- AC Measurements
MAX3421E
D+ OR D-
TEST
POINT
33Ω
15kΩCL
SCLK
MOSI
MISO
tDS
tDH
tCL
tDO
tCHtT1291016
tCSStCSW
tCP
HIGH
IMPEDANCE
HIGH
IMPEDANCE
SCLK
MOSI
MISO
NOTES:
1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS
FOR FULL-DUPLEX MODE.
2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.
3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-FALLING EDGE, THE MAX3421E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN
OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.
tDS
tDH
tCLtCH
tDItOFF
HI-Z1291016
tCSW
tON
tCP
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 10. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))

Partno	Mfg	Dc	Qty	Available	Descript
MAX3421EEHJ+ \|MAX3421EEHJ	MAXIM	N/a	4	avai	USB Peripheral/Host Controller with SPI Interface