MAX3394EEBL+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX3394EEBL+T ,±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up CircuitryApplicationsSelector Guide appears at end of data sheet.Multivoltage Bidirectional Level Translatio ..
MAX339CEE ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral DescriptionThe MAX338/MAX339 are monolithic, CMOS analog♦ On-Resistance, <400Ω maxmultiplex ..
MAX339CEE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX339CPE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.ApplicationsMAX338MJE -55°C to +125°C 16 CERDIP**Data-Acquisition Systems Sample-and-Hold CircuitsO ..
MAX339CSE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.ELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, GND = 0V, VAH = +2.4V, VAL = +0.8V, ..
MAX339CSE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral DescriptionThe MAX338/MAX339 are monolithic, CMOS analog♦ On-Resistance, <400Ω maxmultiplex ..
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MAX706CSA+T ,Low-Cost, µP Supervisory CircuitsMAX705–MAX708/MAX813L Low-Cost, μP Supervisory Circuits
MAX706CSA-T ,Low-Cost, µP Supervisory CircuitsGeneral Description Beneits and
MAX706CSA-T ,Low-Cost, µP Supervisory CircuitsApplications lead-free by adding the + symbol at the endof the part number when ordering. ● Comput ..
MAX706CUA+ ,Low-Cost, µP Supervisory CircuitsGeneral Description Beneits and
MAX706EPA ,Low-Cost, uP Supervisory CircuitsFeaturesThe MAX705-MAX708/MAX813L microprocessor (µP) ' µMAX Package: Smallest 8-Pin SOsupervisory ..

MAX3394EEBL+T
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry
General Description
The MAX3394E/MAX3395E/MAX3396E bidirectional
level translators provide level shifting required for data
transfer in a multivoltage system. Internal slew-rate
enhancement circuitry features 10mA current-sink and
15mA current-source drivers to isolate capacitive loads
from lower current drivers. In open-drain systems, slew-
rate enhancement enables fast data rates with larger
pullup resistors and increased bus load capacitance.
Externally applied voltages, VCCand VL, set the logic-
high levels for the device. A logic-low signal on one I/O
side of the device appears as a logic-low signal on the
opposite I/O side, and vice-versa. Each I/O line is
pulled up to VCCor VLby an internal pullup resistor,
allowing the devices to be driven by either push-pull or
open-drain drivers.
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on
the VCCside for greater protection in applications that
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept VCCvolt-
ages from +1.65V to +5.5V, and VLvoltages from +1.2V
to VCC, making them ideal for data transfer between low
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396Eoperate at a guaran-
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
The MAX3394E is a dual-level translator available in
9-bump UCSP™ and 8-pin 3mm x 3mm TDFN packages.
The MAX3395E is a quad-level translator available in 12-
bump UCSP, and 12-pin 4mm x 4mm TQFN packages.
The MAX3396E is an octal-level translator available in 20-
bump UCSP and 20-pin 5mm x 5mm TQFN packages.
The MAX3394E/MAX3395E/MAX3396E operate over the
extended -40°C to +85°C temperature range.
Applications
Multivoltage Bidirectional Level Translation
SPI™, MICROWIRE™, and I2C Level Translation
Open-Drain Rise-Time Speed-Up
High-Speed Bus Fan-Out Expansion
Cell Phones
Telecom, Networking, Servers, RAID/SAN
Features±15kV ESD Protection on I/O VCC_LinesBidirectional Level Translation Without Direction
PinI/O VL_and I/O VCC_10mA Sink-/15mA Source-
Current Capability Slew-Rate Enhancement Circuitry Supports
Larger Capacitive Loads or Larger External Pullup
Resistors6Mbps Push-Pull/1Mbps Open-Drain Guaranteed
Data RateWide Supply-Voltage Range: Operation Down to
+1.2V on VLand +1.65V on VCCLow Supply Current in Tri-State Output Mode
(3µA typ)Low Quiescent CurrentThermal-Shutdown ProtectionUCSP, TDFN, and TQFN Packages
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
19-3884; Rev 2; 2/0734765
I/O V
I/O V
GND
*CONNECT EXPOSED PAD TO GROUND
*EP
I/O V
I/O V
MAX3394E
TDFN
TOP VIEW (LEADS ON BOTTOM)
Pin Configurations
Ordering Information
PARTPIN-PACKAGEPKG CODE
MAX3394EETA+T8 TDFN-EP**T833-1
MAX3394EEBL+T9 UCSPB9-5
MAX3395EETC+12 TQFN-EP**T1244-4
MAX3395EEBC+T12 UCSPB12-1
MAX3396EEBP+T*20 UCSPB20-1
MAX3396EETP+*20 TQFN-EP**T2055-4
MICROWIRE is a trademark of National Semiconductor Corp.
SPI is a trademark of Motorola, Inc.
UCSP is a trademark of Maxim Integrated Products, Inc.
Note:All devices specified over the -40°C to +85°C operating
range.
+Denotes lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**EP = Exposed paddle.
Selector Guide appears at end of data sheet.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC.........................................................................-0.3V to +6V............................................................................-0.3V to +6V
I/O VCC_......................................................-0.3V to VCC+ 0.3V
I/O VL_...........................................................-0.3V to VL+ 0.3V
EN ...........................................................................-0.3V to +6V
Short-Circuit Duration I/O VL_, I/O VCC_to GND .....Continuous
Maximum Continuous Current ........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin TDFN (derate 18.2mW/°C above +70°C) ........1455mW
9-Bump UCSP (derate 4.7mW/°C above +70°C) ........379mW
12-Pin TQFN (derate 16.9mW/°C above +70°C)........1349mW
12-Bump UCSP (derate 6.5mW/°C above +70°C) .....519mW
20-Pin TQFN (derate 20.8mW/°C above +70°C)........1667mW
20-Bump UCSP (derate 10.0mW/°C above +70°C).....800mW
Operating Temperature Range .........................-40°C to +85°C
Storage Temperature Range ...........................-65°C to +150°C
Junction Temperature .....................................................+150°C
Bump Temperature (soldering) ......................................+235°C
Lead Temperature (soldering, 10s) ...............................+300°C
ELECTRICAL CHARACTERISTICS
(VCC= +1.65V to +5.5V, VL= +1.2V to VCC; CIOVL≤15pF, CIOVCC≤15pF; TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
VL Supply RangeVL1.2VCCV
VCC Supply RangeVCC1.655.50V
MAX3394E150
MAX3395E300Supply Current from VCCICCI/O lines internally
pulled up
MAX3396E600
MAX3394E30
MAX3395E30Supply Current from VLILI/O lines internally
pulled up
MAX3396E30
VCC Tri-State Supply CurrentICC-3EN = GND, TA = +25°C36µA
VL Tri-State Supply CurrentIL-3EN = GND, TA = +25°C0.72µA
LOGIC I/O
I/O VL_ Input-Voltage High
ThresholdVIHL0.7 xV
I/O VL_ Input-Voltage Low
ThresholdVILL0.3 xV
I/O VL_ Internal Pullup DC
ResistanceRLEN = VCC or VL51020kΩ
I/O VL_ Source Current During
Low-to-High TransitionIIHLVL = +1.2V15mA
I/O VL_ Sink Current During High-
to-Low TransitionIILLVCC = +1.65V10mA
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +1.65V to +5.5V, VL= +1.2V to VCC; CIOVL≤15pF, CIOVCC≤15pF; TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
I/O VL_ Low-to-High Transition
ThresholdVL-THVCC = +3.3V, VL = +1.8V0.3 x
0.5 xV
I/O VL_ sink current = 5mA, VILC = 0V0.25
I/O VL_ Output-Voltage LowVOLLI/O VL_ sink current = 10mA, VILC ≤ 0.4V or
0.2 x VL
VILC +
0.4V
I/O VL_ Tri-State Output Leakage
CurrentEN = GND, TA = +25°C-1+1µA
I/O VCC_ Input-Voltage High
ThresholdVIHC(Note 2)0.7 x
VCCV
I/O VCC_ Input-Voltage Low
ThresholdVILC(Note 2)0.3 x
VCCV
I/O VCC_ Internal Pullup DC
ResistanceRCCEN = VCC or VL51020kΩ
I/O VCC_ Source Current During
Low-to-High TransitionIIHCCVCC = +1.65V15mA
I/O VCC_ Sink Current During
High-to-Low TransitionIILCCVCC = +1.65V10mA
I/O VCC_ Low-to-High Transition
ThresholdVCC-THVCC = +3.3V, VL = +1.8V0.3 x
VCC
0.5 x
VCCV
I/O VCC_ sink current = 5mA, VILL = 0V0.25
I/O VCC_ Output-Voltage LowVOLCI/O VCC_ sink current = 10mA, VILL ≤ 0.4V
or 0.2 x VL
VILL +
0.4V
I/O VCC_ Tri-State Output
Leakage CurrentEN = GND, TA = +25°C-1+1µA
EN Input-Voltage High ThresholdVIHE0.7 xV
EN Input-Voltage Low ThresholdVILE0.3 xV
EN Pin Input Leakage CurrentTA = +25°C-1+1µA
ESD PROTECTION
I/O VCC_ ESD ProtectionCVCC = 1µF, Human Body Model±15kV
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
TIMING CHARACTERISTICS
(VCC= +1.65V to +5.5V, VL= +1.2V to VCC; CIOVL≤15pF, CIOVCC≤15pF; TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Push-pull driver, Figure 150I/O VCC_ Rise TimetRVCCOpen-drain driver, internal pullup, Figure 2500ns
Push-pull driver, Figure 150I/O VCC_ Fall TimetFVCCOpen-drain driver, internal pullup, Figure 250ns
Push-pull driver, Figure 350I/O VL_ Rise TimetRVLOpen-drain driver, internal pullup, Figure 4500ns
Push-pull driver, Figure 350I/O VL_ Fall TimetFVLOpen-drain driver, internal pullup, Figure 450ns
Push-pull driver, Figure 150tI/OVL-VCCOpen-drain driver, internal pullup, Figure 2600
Push-pull driver, Figure 350Propagation Delay
tI/OVCC-VLOpen-drain driver, internal pullup, Figure 4600
Propagation Delay After ENtENPush-pull or open-drain driver, Figure 55µs
Push-pull driver5Channel-to-Channel SkewtSKEWOpen-drain driver, internal pullup100ns
Push-pull driver, Figures 1, 36
Maximum Data RateOpen-drain driver, internal pullup,
Figures 2, 41Mbps
Note 1:All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2:During a low-to-high transition, the threshold at which the I/O changes state is the lower of VILLand VILCsince the two sides
are internally connected by an internal switch while the device is in the logic-low state.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
Typical Operating Characteristics
(VCC= +2.5V, VL= +1.8V, CL= 15pF, TA= +25°C, unless otherwise noted.)
VCC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX3394E–96E toc01
VCC SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
VL = +1.2V
DRIVING I/O VL_
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
VL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX3394E–96E toc02
VL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
VCC = +5.0V
DRIVING I/O VL_
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
VCC SUPPLY CURRENT
vs. TEMPERATURE
MAX3394E–96E toc03
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
DRIVING I/O VL_
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
VL SUPPLY CURRENT
vs. TEMPERATURE
MAX3394E–96E toc04
TEMPERATURE (°C)
L SUPPLY CURRENT (mA)3510-15
DRIVING I/O VL_
1Mbps OPEN-DRAIN
6Mbps PUSH-PULL
MAX3394E-96E toc05
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
VCC SUPPLY CURRENT
vs. LOAD CAPACITANCE
DRIVING I/O VL_
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
MAX3394E-96E toc06
LOAD CAPACITANCE (pF)
SUPPLY CURRENT (mA)
VL SUPPLY CURRENT
vs. LOAD CAPACITANCE
DRIVING I/O VL_
6Mbps PUSH-PULL
1Mbps OPEN-DRAIN
MAX3394E-96E toc07
CAPACITIVE LOAD (pF)
RISE TIME (ns)
OPEN-DRAIN RISE TIME
vs. LOAD CAPACITANCE
DRIVING I/O VL_
DRIVING I/O VCC_
OPEN-DRAIN FALL TIME
vs. LOAD CAPACITANCE
MAX3394E–96E toc08
LOAD CAPACITANCE (pF)
FALL TIME (ns)8070605040302010100
DRIVING I/O VCC_
DRIVING I/O VL_
PUSH-PULL RISE TIME
vs. LOAD CAPACITANCE
MAX3394E–96E toc09
LOAD CAPACITANCE (pF)
RISE TIME (ns)8070605040302010100
DRIVING I/O VCC_
DRIVING I/O VL_
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
Typical Operating Characteristics (continued)
(VCC= +2.5V, VL= +1.8V, CL= 15pF, TA= +25°C, unless otherwise noted.)
MAX3394E-96E toc10
LOAD CAPACITANCE (pF)
FALL TIME (ns)
PUSH-PULL FALL TIME
vs. LOAD CAPACITANCE
DRIVING I/O VL_
DRIVING I/O VCC_
PROPAGATION DELAY
vs. LOAD CAPACITANCE
MAX3394E-96E toc11
LOAD CAPACITANCE (pF)
PROPAGATIN DELAY (ns)
DRIVING I/O VL_ OPEN-DRAIN
tPDHL
tPDLH
MAX3394E-96E toc12
LOAD CAPACITANCE (pF)
PROPAGATION DELAY (ns)
DRIVING I/O VCC_ OPEN-DRAIN
PROPAGATION DELAY
vs. LOAD CAPACITANCE
tPDHL
tPDLH
PROPAGATION DELAY
vs. LOAD CAPACITANCE
MAX3394E–96E toc13
LOAD CAPACITANCE (pF)
PROPAGATION DELAY (ns)8060702030405010100
tPDHL
DRIVING I/O VL_ PUSH-PULL
tPDLH
MAX3394E-96E toc14
LOAD CAPACITANCE (pF)
PROPAGATION DELAY (ns)
DRIVING I/O VCC_ PUSH-PULL
SEE FIGURE 3
PROPAGATION DELAY
vs. LOAD CAPACITANCE
tPDHL
40ns/div
(DRIVING I/O VL_, VCC = +2.5V, VL = +1.8V,
CL = 15pF, DATA RATE = 6Mbps)
I/O VCC_
1V/div
I/O VL_
1V/div
MAX3394E-96E toc15
200ns/div
(DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V,
CL = 100pF, DATA RATE = 1Mbps)
MAX3394E-96E toc16
I/O VCC_
2V/div
I/O VL_
2V/div
200ns/div
(DRIVING I/O VL_, VCC = +5.0V, VL = +3.3V,
CL = 400pF, EXTERNAL 4.7kΩ
PULLUPS, DATA RATE = 1Mbps)
MAX3394E-96E toc17
I/O VCC_
2V/div
I/O VL_
2V/div
Detailed Description
The MAX3394E/MAX3395E/MAX3396E bidirectional
level translators provide level shifting required for data
transfer in a multivoltage system. Internal slew-rate
enhancement circuitry features 10mA current-sink and
15mA current-source drivers to isolate capacitive loads
from lower current drivers. In open-drain systems, slew-
rate enhancement enables fast data rates with larger
pullup resistors and increased bus load capacitance.
Externally applied voltages, VCCand VL, set the logic-
high levels for the device. A logic-low signal on one I/O
side of the device appears as a logic-low signal on the
opposite I/O side and vice-versa. Each I/O line is pulled
up to VCCor VLby an internal pullup resistor, allowing
the devices to be driven by either push-pull or open-
drain drivers.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
Pin Description
PIN
MAX3394EMAX3395EMAX3396E
TDFNUCSPTQFNUCSPTQFNUCSP
NAMEFUNCTIONA111B114D3VCC
VCC Supply Voltage +1.65V ≤ VCC ≤ +5.5V. Bypass
VCC to GND with a 0.1µF ceramic capacitor and a
1µF or greater ceramic capacitor as close to the
device as possible.B16B34A4EN
Enable Input. Drive EN logic high for normal
operation. Drive EN logic low to force all I/O lines to
a high-impedance state and disconnect internal
pullup resistors.A210C118C1I/O VCC1I/O 1 Referred to VCCA39C216D1I/O VCC2I/O 2 Referred to VCCB35B413D4GNDGroundC32A220A1I/O VL2I/O 2 Referred to VLC21A119B1I/O VL1I/O 1 Referred to VLC112B23A3VL
Logic Supply Voltage +1.2V ≤ VL ≤ VCC. Bypass VL
to GND with a 0.1µF or greater ceramic capacitor
as close to the device as possible.—3A31B2I/O VL3I/O 3 Referred to VL—4A42A2I/O VL4I/O 4 Referred to VL—7C415D2I/O VCC4I/O 4 Referred to VCC—8C317C2I/O VCC3I/O 3 Referred to VCC———12C3I/O VCC5I/O 5 Referred to VCC———11D5I/O VCC6I/O 6 Referred to VCC———10C4I/O VCC7I/O 7 Referred to VCC———9C5I/O VCC8I/O 8 Referred to VCC———5B3I/O VL5I/O 5 Referred to VL———6A5I/O VL6I/O 6 Referred to VL———7B4I/O VL7I/O 7 Referred to VL———8B5I/O VL8I/O 8 Referred to VL—EP—EP—EPExposed Pad. Connect exposed pad to GND.
MAX3394E/MAX3395E/MAX3396E
The MAX3394E/MAX3395E/MAX3396E feature a tri-
state output mode, thermal-shutdown protection, and
±15kV Human Body Model (HBM) ESD protection on
the VCCside for greater protection in applications that
route signals externally.
The MAX3394E/MAX3395E/MAX3396E accept VCCvolt-
ages from +1.65V to +5.5V, and VLvoltages from +1.2V
to VCC, making them ideal for data transfer between low-
voltage ASIC/PLDs and higher voltage systems. The
MAX3394E/MAX3395E/MAX3396Eoperate at a guaran-
teed data rate of 6Mbps with push-pull drivers and
1Mbps with open-drain drivers.
Level Translation
The MAX3394E/MAX3395E/MAX3396E utilize a trans-
mission gate architecture to provide bidirectional level
translation between I/O VL_ and I/O VCC_. The trans-
mission gate architecture is comprised of a pass-FET,
gate-control logic, and slew-rate enhancement circuit-
ry. When both I/O VL_ and I/O VCC_ are logic high, the
gate-control logic disables the pass-FET, providing
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
MAX3394E
MAX3395E
MAX3396E
tFVCCtRVCC
tI/OVL-VCC
I/O VL_I/O VCC_
50ΩVCC
10%10%
90%90%
50%50%
50%50%
VCC
CIOVCC
tI/OVL-VCC
VCCENVL
I/O VCC
I/O VL
Figure 1. Push-Pull Driving I/O VL_Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
tFVCCtRVCC
tI/OVL-VCC
I/O VL_I/O VCC_VCC
10%10%
90%90%
50%50%
50%50%
VCC
CIOVCC
tI/OVL-VCC
I/O VCC
VGATEVCCEN
VGATE
Figure 2. Open-Drain Driving I/O VL_Test Circuit and Timing
capacitive isolation between I/O lines. When one or
both I/O lines are at a logic-low level, the gate-control
logic turns the pass-FET on. When the pass-FET is
active, I/O VL_ and I/O VCC_ are connected, allowing
the logic-low signal to be expressed simultaneously on
both I/O lines.
The MAX3394E/MAX3395E/MAX3396E have internal
10kΩ(typ) pullup resistors from I/O VL_ and I/O VCC_
to the respective supply voltages, allowing operation
with open-drain drivers. Internal slew-rate enhancement
circuitry accelerates logic-state transitions, maintaining
a fast data rate with a higher bus load capacitance.
Additionally, the 10mA current sink drivers permit the
use of smaller external pullup resistors.
Internal Slew-Rate Enhancement
Internal slew-rate enhancement circuitry accelerates
logic-state changes by turning on MOSFETs MP1and
MP2during low-to-high logic transitions, and MOSFETs
MN3and MN4during high-to-low logic transitions (see
the Functional Diagram). During logic-state changes,
speed-up MOSFETS are triggered by I/O line voltage
thresholds. MOSFETS MN3and MN4sink 10mA during
high-to-low logic transitions. MP1and MP2source 15mA
during low-to-high logic transitions. Slew-rate enhance-
ment allows a fast data rate despite large capacitive bus
loads, and permits larger external pullup resistors.
MAX3394E/MAX3395E/MAX3396E
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
MAX3394E
MAX3395E
MAX3396E
tFVLtRVL
tI/OVCC-VL
I/O VL_I/O VCC_VCC
10%10%
90%90%
50%50%
50%50%
VCC
CIOVL
tI/OVCC-VL
I/O VCCVLVCCEN
50Ω
I/O VL
Figure 3. Push-Pull Driving I/O VCC_Test Circuit and Timing
MAX3394E
MAX3395E
MAX3396E
tI/OVCC-VL
I/O VL_I/O VCC_VCC
10%10%
90%90%
50%50%
50%50%VCC
CIOVL
tI/OVCC-VL
I/O VLVCCEN
tFVLtRVL
VGATE
Figure 4. Open-Drain Driving I/O VCC_Test Circuit and Timing
MAX3394E/MAX3395E/MAX3396E
Power-Supply Sequencing
The MAX3394E/MAX3395E/MAX3396E require two sup-
ply voltages. For proper operation, ensure that +1.65V ≤
VCC≤+5.5V, and +1.2V ≤VL≤VCC. There are no restric-
tions on power-supply sequencing. During power-up or
power-down, the MAX3394E/MAX3395E/MAX3396E can
withstand either the VLor the VCCsupply floating while
the other supply is applied. The device will not latch up in
Tri-State Output Mode
Connect EN to VLor VCCfor normal operation. Drive
EN low to force the MAX3394E/MAX3395E/MAX3396E
to a tri-state output mode. In tri-state output mode, all
I/O lines are driven to a high-impedance state, and the
pass-FET is disabled to prevent current flow between
I/O lines. Tri-state output mode disables the internal
pullup resistors on I/O VL_ and I/O VCC_, and reduces
supply current to 3µA typ (VCC) and 0.7µA typ (VL).
±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/
Octal-Level Translators with Speed-Up Circuitry
MAX3394E
MAX3395E
MAX3396E
I/O VL_I/O VCC_VCC
VCCVCC
50Ω
RLOAD
CIOVCC
MAX3394E
MAX3395E
MAX3396E
I/O VCC_VCC
VCCVCC
50Ω
RLOAD
I/O VL_
TIME
TIME
tEN
tEN
I/O VCC_
I/O VL_
CIOVL
0.5V
0.2V (VL < 2V)
0.5V (VL ≥ 2V)
Figure 5. Enable Test Circuit and Timing

Partno	Mfg	Dc	Qty	Available	Descript
MAX3394EEBL+T \|MAX3394EEBLT	MAXIM	N/a	3857	avai	±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up Circuitry