MAX2990ECB+ ,10kHz to 490kHz OFDM-Based Power Line Communications ModemFeaturesThe MAX2990 power line communication (PLC) base- ● Combines the Physical Layer (PHY) and Me ..
MAX2991ECM+ ,Power-Line Communications (PLC) Integrated Analog Front-End TransceiverFeaturesThe MAX2991 power-line communication analog front- S Optimized to Operate with the MAX2990 ..
MAX3000EEUP+ ,+1.2V to +5.5V, ±15kV ESD-Protected, 0.1µA, 35Mbps, 8-Channel Level TranslatorsMAX3000E/MAX3001E/ MAX3002–MAX3012+1.2V to +5.5V, ±15kV ESD-Protected, 0.1µA,35Mbps, 8-Channel Leve ..
MAX3001EAUP+ ,+1.2V to +5.5V, ±15kV ESD-Protected, 0.1µA, 35Mbps, 8-Channel Level TranslatorsApplicationsCMOS Logic-Level Translation+1.8V +3.3VCellphonesSPI™ and MICROWIRE™ Level TranslationL ..
MAX3001EEBP+T ,+1.2V to +5.5V, 【15kV ESD-Protected, 0.1UA, 35Mbps, 8-Channel Level TranslatorsELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to V , EN = V (MAX3000E/MAX3001E/MAX3002/ ..
MAX3001EEUP ,+1.2V to +5.5V / 15kV ESD-Protected / 0.1A / 35Mbps / 8-Channel Level TranslatorsFeaturesThe MAX3000E/MAX3001E/MAX3002–MAX3012 8- Guaranteed Data Rate Optionschannel level transl ..
MAX6190AESA+T ,Precision, Micropower, Low-Dropout Voltage ReferencesELECTRICAL CHARACTERISTICS—MAX6190(V = 5V, I = 0nA, T = T to T , unless otherwise noted. Typical va ..
MAX6190BESA ,Precision / Micropower / Low-Dropout Voltage Referencesapplications that require fast settling,Analog-to-Digital and Digital-to-Analog Convertersand are s ..
MAX6190CESA ,Precision / Micropower / Low-Dropout Voltage ReferencesMAX6190–MAX6195/MAX619819-1408; Rev 1; 3/99Precision, Micropower, Low-Dropout Voltage References
MAX6191AESA ,Precision / Micropower / Low-Dropout Voltage ReferencesMAX6190–MAX6195/MAX619819-1408; Rev 1; 3/99Precision, Micropower, Low-Dropout Voltage References
MAX6191BESA ,Precision / Micropower / Low-Dropout Voltage ReferencesELECTRICAL CHARACTERISTICS—MAX6190(V = +5V, I = 0, T = T to T , unless otherwise noted. Typical val ..
MAX6192AESA ,Precision / Micropower / Low-Dropout Voltage ReferencesFeaturesThe MAX6190–MAX6195/MAX6198 precision, micro-' ±2mV (max) Initial Accuracypower, low-dropou ..
MAX2990ECB+
10kHz to 490kHz OFDM-Based Power Line Communications Modem
General DescriptionThe MAX2990 power line communication (PLC) base-
band modem delivers a cost-effective, reliable, halfduplex
asynchronous data communication over AC power lines
at speeds up to 100kbps. The MAX2990 is a highly inte-
grated system-on-chip (SoC) that combines the physical
(PHY) and media access control (MAC) layers using
Maxim’s 16-bit MAXQ microcontroller core. The MAX2990
utilizes OFDM modulation techniques to enable robust
data communication using the same electrical network
that supplies power to all other devices on the network.
The MAX2990 includes the MAXQ microcontroller core.
The MAXQ is a 16-bit RISC microcontroller with 32kB
flash memory, 5.12kB of ROM, and 8kB SRAM, of which
4kB that can be simultaneously accessed by the MCU
and the PHY. The MAX2990 is integrated with modules for
serial communication (SPI™, I2C, UART) and a real-time
clock (RTC) for time stamping, in addition to standard
blocks such as timers, GPIO, and external interrupts.
The MAX2990 transceiver is based on an orthogonal
frequency division multiplexing (OFDM) technique that
allows robust data transmission over poor channel condi-
tions specifically for environments with impulsive noise.
OFDM with binary phase shift key (BPSK) and forward
error correcting (FEC) blocks are used because of their
inherent adaptability in the presence of frequency selec-
tive channels without the use of equalizers, resilience to
jammer signals, robust communications in the presence
of group delay spread, and robustness to impulsive noise.
The MAX2990 features jammer cancellation that removes
constant sinusoidal interference signals for FCC and
ARIB bands. Privacy is provided by DES encryption.
The MAX2990 is available in a 64-pin LQFP package and
is specified over the -40°C to +85°C extended tempera-
ture range.
Applications●Automatic Meter Reading ●Home Automation●Heating Ventilation and Air Conditioning (HVAC)●Building Automation●Industrial Automation●Lighting Control●Sensor Control and Data Acquisition●Remote Monitoring and Control●Voice-Over-Powerline●Security Systems/Keyless Entry
Features●Combines the Physical Layer (PHY) and Media
Access Controller (MAC)●Integrated Microcontroller with 32kB Password-
Protected Flash Memory and 8kB SRAM●Maximum Effective Data Rate in Normal Mode 32kbps at 10kHz to 95kHz and 100kbps at
10kHz to 490kHz●Complies with CENELEC A (10kHz to 95kHz) CENELEC B (95kHz to 120kHz) CENELEC C (120kHz to 140kHz) FCC (10kHz to 490kHz) ARIB (10kHz to 450kHz)●Includes Forward Error Correction (FEC)
Mechanism and CRC16●Includes Fast DES Engine as the
Encryption/Decryption Coprocessor and CRC32●Jammer Cancellation for FCC and ARIB●User-Configured Start and End Operating Frequency●Carrier Sense Multiple Access/Collision
Avoidance (CSMA/CA) Channel Access
Arbitration●Automatic Repeat Request (ARQ) to Enhance
Error Detection and Improve Data Reliability●Supports SPI, I2C, and UART Interfaces●Real-Time Clock (RTC)●PWM Counters●Built-In Test Mode Engine for Identifying Channel
Conditions
SPI is a trademark of Motorola, Inc.
Pin Configuration appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.+Denotes a lead-free package.
PARTTEMP RANGEPIN-PACKAGEMAX2990ECB+-40°C to +85°C64 LQFP
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Ordering Information
VDDIO to DGND ...................................................-0.5V to +3.6V
VDDC to DGND ..................................................-0.5V to +1.98V
AVDD to AGND ...................................................-0.5V to +1.98V
Port0, Port1, Port2 to GPIO .................................-0.5V to +5.5V
XTAL1S, XTAL2S, XTAL1A, XTAL2A .................-0.5V to +1.98V
All Other Pins .......................................................-0.5V to +3.6V
Continuous Power Dissipation (TA = +70°C)
64-Pin LQFP (derate 23.8mW/°C above +70°C) ......1905mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
64-Pin LQFP ..................................................................8°C/WJunction-to-Ambient Thermal Resistance (θJA) (Note 1)
64-Pin LQFP ................................................................42°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ..............................65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS+3.3V I/O Supply VoltageVDDIO 3.03.33.6V
+1.8V Core Supply VoltageVDDC 1.701.801.98V
+1.8V Analog Core SupplyAVDD1.701.801.98V
High-Level Output VoltageVOHIHIGH = -4.0mA2.4 V
Low-Level Output VoltageVOLILOW = 8.0mA 0.4V
High-Level Output Voltage:
GPIO Clock PadVOHGIHIGH = -8.0mA2.4 V
Output Low Voltage GPIOVOLGILOW = 8.0mA0.4V
Input High Voltage
(Port0 to Port2)VIH1 0.7 x
VDDIO 5.5V
Input High Voltage (Port3)VIH20.7 x
VDDIOVDDIOV
Input High Voltage (XTAL1A,
XTAL2A, XTAL1S, XTAL2S)VIHXT0.7 x
VDDCVDDCV
Input Low VoltageVIL VSS 0.3 x
VDDCV
Input HysteresisVIHYS 0.20.5 V
Input Leakage CurrentIIInternal pullup disabled-100 +100µA
GPIO Pullup ResistanceRPUInternal pullup enabled 80 kΩRPU3 40
VDDIO Supply CurrentIDDIO 35mA
VDDC Supply CurrentIDDC 80mA
Idle Mode CurrentIIDLENo peripherals running 5mA
Stop Mode CurrentISTOP1Power monitor on 0.5mAISTOP2Power monitor off 0.25
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
CAUTION! ESD SENSITIVE DEVICE
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 3)
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVDDIO Brownout Trip PointVRSTIO 2.75 3.00V
VDDC/AVDD Power-Fail Warning
LevelVPFWC VRSTC
+ 0.04VV
VDDIO Power-Fail Warning LevelVPFWIO VRSTIO
+ 0.1VV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSystem Clock External Crystal
Frequency1/tCLKS120MHz
System Clock External Crystal
Frequency—PLL 2x Mode1/tCLKS4.016.5MHz
System Clock External Crystal
Frequency—PLL 4x Mode1/tCLKS2.08.25MHz
System Clock External Clock
Frequency1/tCLKS033MHz
System Clock External Clock
Frequency—PLL 2x Mode1/tCLKS4.016.5MHz
System Clock External Clock
Frequency—PLL 4x Mode1/tCLKS2.08.25MHz
System Clock External Clock Duty
Cycle
1/tCLKS_
DUTY60%
System Clock External Crystal
Warmup DelaytECWS65,536tCLKS
System Clock PLL Warmup DelaytPLLWS65,536tCLKS
AFE Clock External Crystal
Frequency1/tCLKA1 20MHz
AFE Clock External Crystal
Frequency—PLL 2x Mode1/tCLKA4 18MHz
AFE Clock External Crystal
Frequency—PLL 4x Mode1/tCLKA2 9MHz
AFE Clock External Clock
Frequency1/tCLKA0 36MHz
AFE Clock External Clock
Frequency—PLL 2x Mode1/tCLKA4 18MHz
AFE Clock External Clock
Frequency—PLL 4x Mode1/tCLKA2 9MHz
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
AC Electrical Characteristics
DC Electrical Characteristics (continued)
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAFE Clock External Clock Duty
Cycle
1/tCLKA_
DUTY40 60%
AFE Clock External Crystal
Warmup DelaytECWA 65,536 tCLKA
AFE Clock PLL Warmup DelaytPLLWA 65,536 tCLKA
Crystal Tolerance 25 ppm
Crystal Input CapacitanceCIN 6 pF
Output Fall-Time GPIO I2C PadtOF_I2C20 + 0.1
x CL 250ns
RTC Crystal Frequency32KIN 32.768 kHz
MCU UART INTERFACE SYNCHRONOUS MODE (Note 4) (Figure 1)TXD Clock PeriodtXLXL
SM2 = 012 x
tCLKS
SM2 = 14 x
tCLKS
TXD Clock High TimetXHXL
SM2 = 03 x
tCLKS
SM2 = 12 x
tCLKS
RXD Output Valid to TXD Clock
Rising EdgetQVXH
SM2 = 010 x
tCLKS - 10
SM2 = 13 x
tCLKS - 10
RXD Output Data Hold from TXD
Clock Rising EdgetXHQH
SM2 = 02 x
tCLKS - 10ns
SM2 = 1tCLKS
- 10
RXD Input Data Valid to TXD
Clock Rising EdgetXHDVSM2 = 0, SM2 = 1tCLKS
+ 50ns
RXD Input Data Hold After TXD
Clock Rising EdgetXHDHSM2 = 00nsSM2 = 10
SPI MASTER (Note 4) (Figure 3)SPI Master Operating Frequency1/tMCK 1/2 x
tCLKSkHz
I/O Rise/Fall TimetRFCL = 15pF, pullup = 560Ω 16ns
SCLK Output Pulse-Width High/
LowtMCH, tMCL tMCK/2
- tRF ns
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
AC Electrical Characteristics (continued)
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMOSI Output Valid to SCLK
Sample Edge (MOSI Setup)tMOH tMCK/2
- tRF ns
MOSI Output Hold After SCLK
Last Sample EdgetMOV tMCK/2
- tRF ns
SCLK Last Sample Edge to MOSI
Output Change (MOSI Last Hold)tMLH tMCK/2
- tRF ns
MISO Input Valid to SCLK Sample
Edge (MISO Setup)tMIS40ns
MISO Input Hold After SCLK
Sample EdgetMIH0ns
SPI SLAVE (Note 4) (Figure 4)SPI Slave Operating Frequency1/tSCK 1/8tCLKSkHz
I/O Rise/Fall TimetRFCL = 15pF, pullup = 560Ω 16ns
SCLK Input Pulse-Width High/LowtSCH, tSCL tSCK/2
- tRF ns
SPICS Active to First Shift EdgetSSE tRF ns
MOSI Input to SCLK Sample
Edge Rise/Fall SetuptSIS tRF ns
MOSI Input from SCLK Sample
Edge Transition HoldtSIH tRF ns
MISO Output Valid After SCLK
Shift Edge TransitiontSOV 50ns
SPICS Inactive to Next SPICS
AssertedtSSH tSCK +
tRF ns
SCLK Inactive to SPICS
DeassertedtSD tRF ns
MISO Output Disabled After
SPICS Edge DeassertedtSLH 2 x tSCK
+ 2 x tRFns
AFE INTERFACE SERIAL MODE (Note 5)AFE Interface Operating
Frequency1/tTRCK tCLKA MHz
Clock Rise/Fall TimetCRFCL = 20pF 6.5ns
RCLK/TCLK Output Pulse-Width
High/Low
tTRCH,
tTRCL 0.4 x
tTRCK/2 0.6 x
tTRCK/2ns
SDI Input Setup to RCLK Active
EdgetRIS 5 ns
SDI Input Hold After RCLK Active
EdgetRIH 0 ns
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
AC Electrical Characteristics (continued)
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRXEN/TXEN Active Level Output
Pulse WidthtTREW tTRCKns
RCLK/TCLK to RXEN/TXEN
ActivetTRED 010ns
TCLK to SDO OutputtTOD 010ns
I2C FULL-SPEED TIMINGSCL Clock FrequencyfSCL400kHz
Input Low VoltageVIL_I2C0.3 x
VDDIOV
Input High VoltageVIH_I2C0.7 x
VDDIOV
Input HysteresisVIHYS_I2CVIO > 2V0.05 x
VDDIOV
SDA Output Logic-LowVOL_I2CVL > 2V, 3mA sink current00.4V
Input Leakage CurrentIIN_I2C0 < VIO < VL-10+10µA
I/O CapacitanceCIO_I2C5pF
SDA Output Fall Time tOF_I2C(Note 6)20 +
0.1Cb250ns
Hold Time After Repeated STARTtHD,STA0.6µs
Clock Low PeriodtLOW_I2C1.3µs
Clock High PeriodtHIGH_I2C0.6µs
Setup Time for Repeated STARTtSU,STA0.6µs
Hold Time for DatatHD,DAT0.9 µs
Setup Time for DatatSU,DAT100ns
SDA/SCL Fall TimetF(Note 6)20 +
0.1Cb300ns
SDA/SCL Rise TimetR(Note 6)20 +
0.1Cb300ns
Setup Time for STOPtSU,STO0.6µs
Bus Free Time Between STOP
and STARTtBUF1.3µs
Capacitive Load for Each Bus
LineCB400pF
Pulse Width of Spike SuppressedtSP_I2C(Note 7)50ns
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
AC Electrical Characteristics (continued)
Note 2: Specifications down to -40°C are guaranteed by design and not production tested.
Note 3: Timing specifications guaranteed by design.
Note 4: tCLKS refers to the system clock without PLL multiplication.
Note 5: tCLKA refers to the AFE clock without PLL multiplication.
Note 6: ISINK ≤ 6mA, CB = total capacitance of one bus line in pF. tR and tF are measured between 0.8V and 2.1V.
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
(VDDIO = +3.0V to +3.6V, VDDC = AVDD = +1.62V to +1.98V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at
VDDIO = +3.3V, VDDC = AVDD = +1.8V, TA = +25°C.) (Note 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNoise Margin at the Low Level
for Each Connected Device
(Including Hysteresis)
VnL_I2C0.1 x
VDDIOV
Noise Margin at the High Level
for Each Connected Device
(Including Hysteresis)
VnH_I2C0.2 x
VDDIOV
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
AC Electrical Characteristics (continued)
PINNAMEFUNCTION1–4, 10–13 P0.0–P0.7
General-Purpose, Digital, I/O, Type-D Port*. Port0 functions as both an 8-bit I/O port and as an
alternate interface for external interrupts. Each interrupt can be individually enabled and the active
edge can be selected. The default reset condition of Port0 is a weak pullup (input). To drive Port0 as
an output, the port direction register must be programmed to enable outputs or the alternate function module must be conigured.
Pin/PortAlternate FunctionAlternate Function DescriptionP0.0T0A/INT0Timer 0 Inout A/External Interrupt 0P0.1T0B/INT1Timer 0 Inout B/External Interrupt 1P0.2T1A/INT2Timer 1 Inout A/External Interrupt 2P0.3T1B/INT3Timer 1 Inout B/External Interrupt 3P0.4T2A/INT4Timer 2 Inout A/External Interrupt 4P0.5T2B/AGC0/INT5Timer 2 Inout B/AGC Control Bit 0/
External Interrupt 5P0.6T3A/AGC1/INT6Timer 3 Inout A/AGC Control Bit 1/
External Interrupt 6P0.7T3B/AGC2/INT7Timer 3 Inout B/AGC Freeze or AGC
Control Bit 2/External Interrupt 7
5, 19, 30, 33,
53, 58DGNDDigital Ground
6, 20, 34,
54, 59VDDC+1.8V Digital Core Supply. Bypass VDDC to DGND with a 0.1µF ceramic capacitor as close as
possible to VDDC. 32KINRTC Crystal Oscillator Input. Connect 32KIN to one side of a 32.768kHz crystal and a load capacitor to ground. 32KIN can be conigured to be driven by an external clock source.RTC Crystal Oscillator Output. Connect 32KOUT to the other side of a 32.768kHz crystal and a load
I2C
GPIO
SPI
MCU (MAXQ)
UART
WATCHDOG
TIMER
TIMER/
PWM
32kB
FLASH
ROM
5k x 8
CSMA/
ARQ
4kB
SRAM
BPSK
DEMOD
JAMMER
CANCELLER
AND SYNCH
AFE
SPI
INTERFACE
DUAL-
PORT
SRAM
4k x 8
REED-
SOLOMON
CONVOLUTIONAL
ENCODER
INSERT
PREAMBLE
AND CYCLIC
PREFIX
REED-
SOLOMON
VITERBI
DECODER
INTERRUPT
CNTL
JTAG
IFFT
OFDM PLC PHY
FFT
RTC
PLC MAC
MAX2990MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Pin Description
Functional Diagram
PINNAMEFUNCTION9, 25,
39, 56VDDIOInput/Output Power Supply. VDDIO is nominally +3.3V and can range from +3.0V to +3.6V. Bypass
VDDIO to DGND with a 0.1µF ceramic capacitor as close as possible to VDDIO.RST
Active-Low Reset Input/Output. RST is an external active-low input that employs an internal pullup
resistor. RST also acts as an output when the source of the reset is internal to the device, such as a
watchdog timer and power-fail. In this case, RST is held low while the processor is in a reset state,
and goes high as the processor exits this state.
15, 50AVDD+1.8V Analog Power Supply. Bypass AVDD to AGND with a 0.1µF ceramic capacitor as close as
possible to AVDD.
16, 49AGNDAnalog GroundXTAL1SSystem Crystal Oscillator Input. Connect XTAL1S to one side of a parallel resonant crystal and a load capacitor to ground. XTAL1S can be conigured to be driven by an external clock source.XTAL2SSystem Crystal Oscillator Output. Connect XTAL2S to the other side of a parallel resonant crystal and a
load capacitor to ground. Leave XTAL2S unconnected if XTAL1S is driven by an external clock source.
21–24,
26–29P1.0–P1.7
General-Purpose, Digital, I/O, Type-C Port*. Port1 functions as both an 8-bit I/O port and as an
alternate interface for serial protocols. The default reset condition of Port1 is a weak pullup (input).
To drive Port1 as an output, the port direction register must be programmed to enable outputs or the alternate function module must be conigured to drive the port.
Pin/PortAlternate FunctionAlternate Function DescriptionP1.0TXDMCU UART TransmitP1.1RXDMCU UART ReceiveP1.2SCLI2C ClockP1.3SDAI2C DataP1.4SCLKSPI SCLKP1.5MOSISPI Master OutP1.6MISOSPI Master InP1.7MSSELSPI Master/Slave SelectPROG
UART Bootloader Input. PROG activates the UART bootloader by being held low for at least three system clock cycles or until the ready lag is detected on TXD. Activating the PROG function
automatically sets the PSPE bit in the ICDF register and initiates an internal reset. Upon code load
completion, the PSPE bit is cleared and an internal reset is issued.TDOJTAG Data Output
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Pin Description (continued)
*Note: Type-D ports are capable of interrupts while type-C ports are not.
PINNAMEFUNCTION35–38,
40–43P2.7–P2.0
General-Purpose, Digital, I/O, Type-C Port*. Port2 functions as both an 8-bit I/O port and as an
alternate interface for serial protocols. The default reset condition of Port2 is a weak pullup (input).
To drive Port2 as an output, the port direction register must be programmed to enable outputs or the alternate function module must be conigured to drive the port.
Pin/PortAlternate FunctionAlternate Function DescriptionP2.0AFE_GP2/AGC0AFE General Purpose 2/AGC Control Bit 0P2.1AFE_GP3/AGC1AFE General Purpose 3/AGC Control Bit 1P2.2AFE_GP4/AGC2AFE General Purpose 4/AGC Freeze or AGC
Control Bit 2P2.3AFE_GP5AFE General Purpose 5P2.4T5A/X1CKTimer 5 Inout A/X1 External 3.3V ClockP2.5T5BTimer 5 Inout BP2.6T4A/T6A/X2CKTimer 4 Inout A/Timer 6 Inout A/X2 External 3.3V ClockP2.7T4B/T6BTimer 4 Inout B/Timer 6 Inout BTDIJTAG Data InputTMSJTAG Mode Select InputTCKJTAG Clock InputXTAL2AAFE Crystal Oscillator Output. Connect XTAL2A to the other side of a parallel resonant crystal and a load
capacitor to ground. Leave XTAL2A unconnected if XTAL1A is driven by an external clock source.XTAL1AAFE Crystal Oscillator Input. Connect XTAL1A to one side of a parallel resonant crystal and a load capacitor to ground. XTAL1A can be conigured to be driven by an external clock source.
51, 52, 55,
57, 60–64P3.0–P3.8
General-Purpose, Digital, I/O Type-C Port*. Port3 functions as both a 9-bit I/O port and as an alternate
interface for the AFE. The default reset condition of Port3 is a weak pullup (input). To drive Port3 as
an output, the port direction register must be programmed to enable outputs or the alternate function module must be conigured to drive the port.
Pin/PortAlternate FunctionAlternate Function DescriptionP3.0AFE_TXENAFE Transmit EnableP3.1AFE_SDOAFE Serial Data OutP3.2AFE_TXCLKAFE Transmit ClockP3.3AFE_RXCLKAFE Receive ClockP3.4AFE_SDIAFE Serial Data InP3.5AFE_RXENAFE Receive EnableP3.6AFE_RSTNAFE ResetP3.7AFE_GP1/RXPINAFE General Purpose 1/RXPINP3.8AFE_GP0/TXPINAFE General Purpose 0/TXPIN
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Pin Description (continued)
Figure 1. UART Timing Diagram for Synchronous Mode (Mode 0)
Figure 2. I2C Timing Diagram
TXD CLOCK
RXD INPUT
RXD OUTPUTBIT X
BIT X
tXHDVtXHDH
tXLXL
tXHXL
BIT X + 1
tQVXHtXHQH
SDA
SCL
tHD, STA
tLOW
tHIGHtF
tSU, DATtSU, STA
tSU, STO
tBUF
tHD, STA
tHD, DAT
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED
START CONDITION
tF,TX
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Timing Figures
Figure 3. SPI Master Timing Diagram
Figure 4. SPI Slave Timing Diagram
SPICS
(SAS = 0)
SCLK
CKPOL/CKPHA
0/1 OR 1/0
SCLK
CKPOL/CKPHA
0/0 OR 1/1
MOSIMSB
MSBMISO
MSB-1
MSB-1
LSB
LSB
SHIFTSAMPLESHIFTSAMPLE
tMCK
tMCH
tMOH
tMIStMIH
tMOVtRFtMLH
tMCL
SPICS
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCHtSCL
MOSI
MISO
tSCK
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSIStSIH
MSBMSB-1
MSB
tSOV
MSB-1LSB
tSSE
LSB
tSLH
tSSH
tSD
tRF
SHIFTSAMPLESHIFTSAMPLE
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
Timing Figures (continued)
Detailed DescriptionThe MAX2990 is an integrated SoC power line modem
that utilizes advance modulation techniques for PLC. The
MAX2990 enables robust data communication using the
existing electrical wires, reducing the need for external
cables for interconnections between nodes in a network.
The MAX2990 features a modem solution based on
OFDM and the high-performance MAXQ microcontroller
core. The MAX2990 encodes data at various carrier
frequencies from 10kHz to 490kHz and uses advanced
OFDM modulation techniques to send multiplexed data
over the power line for overall high data throughput of
100kbps. The MAXQ core is a fully static CMOS, 16-bit
RISC microcontroller with 32kB flash memory, 5.12kB of
ROM, and 8kB of SRAM, of which 4kB can be simultane-
ously accessed by the internal microprocessor and the
PHY. The MAXQ is integrated with modules for serial
communication (SPI, I2C, and UART) and RTC for time
stamping, in addition to standard blocks such as timers
for PWM, GPIO, and external interrupts.
The MAX2990 MAC features 48-bit and 16-bit addressing
and organizes data into packets before transmission. The
MAX2990 uses various registers for precise control over
the PHY layer.
The MAX2990 automatically senses for collisions before
it transmits over the power line. If multiple devices are
connected in a star topology, collisions are not a problem.
However, when multiple devices communicate to each
other, collision avoidance becomes a primary issue. In
peer-to-peer networks, it is possible for concurrent trans-
missions by multiple nodes to result in frame collisions.
The multiple transmissions interfere with each other;
therefore, all data is garbled and receivers are unable to
distinguish the overlapping received signals from each
other (Figure 5).
The MAX2990 features a carrier sense multiple access/
collision avoidance (CSMA/CA) scheme that prevents
collisions. If the channel is not clear, the node waits for
a randomly chosen period of time and then checks again
to see if the channel is clear. The MAX2990 accepts
data from the user at any time, but transmits over the
power line in accordance with CSMA/CA. The automatic
repeat request (ARQ) feature improves data reliability
by requesting packets with errors be retransmitted. The
MAX2990 features a programmable ARQ that auto-
matically detects and resends unsuccessful transmission
packets without any user interface.
Orthogonal Frequency-Division
Multiplexing (OFDM) TechniqueThe power line channel is a hostile environment. Channel
characteristics and parameters vary with frequency, loca-
tion, time, and the type of equipment connected. The
lower frequency regions from 10kHz to 490kHz are espe-
cially susceptible to interference. Furthermore, the power
line is a frequency selective channel. Besides background
noise, it is subject to impulsive noise often occurring at
50/60Hz, narrowband interference, and group delays up
to several hundred microseconds.
OFDM is a modulation technique that can utilize the
allowed bandwidth for CENELEC, ARIB, and FCC bands
very efficiently, allowing the use of advanced channel cod-
ing techniques. This combination enables a very robust
power line communication in the presence of narrowband
interference, impulsive noise, and frequency selective
attenuation.
DEVICE
DEVICEDEVICE
DEVICEDEVICE
DEVICE
HOST
DEVICE
DEVICEDEVICE
DEVICEDEVICE
DEVICE
NETWORK
COORDINATOR
MAX299010kHz to 490kHz OFDM-Based
Power Line Communication Modem
