MAX2769ETI+T ,Universal GPS Receiverapplications, including mobile handsets.♦ Dual-Input Uncommitted LNA for SeparateDesigned on Maxim’ ..
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MAX606EUA ,Low-Profile, 5V/12V or Adjustable, Step-Up DC-DC Converters for Flash Memory/PCMCIA CardsFeaturesThe MAX606/MAX607 are the smallest CMOS, step-up' Lowest-Height Circuit (1.35mm max)DC-DC c ..
MAX2769ETI+-MAX2769ETI+T
Universal GPS Receiver
AVAILABLE
EVALUATION KIT AVAILABLE
General Description
The MAX2769 is the industry’s first global navigation
satellite system (GNSS) receiver covering GPS,
GLONASS, and Galileo navigation satellite systems on a
single chip. This single-conversion, low-IF GNSS receiver
is designed to provide high performance for a wide range
of consumer applications, including mobile handsets.
Designed on Maxim’s advanced, low-power SiGe
BiCMOS process technology, the MAX2769 offers the
highest performance and integration at a low cost.
Incorporated on the chip is the complete receiver
chain, including a dual-input LNA and mixer, followed
by the image-rejected filter, PGA, VCO, fractional-N
frequency synthesizer, crystal oscillator, and a multibit
ADC. The total cascaded noise figure of this receiver is
as low as 1.4dB.
The MAX2769 completely eliminates the need for external
IF filters by implementing on-chip monolithic filters and
requires only a few external components to form a com-
plete low-cost GPS receiver solution.
The MAX2769 is the most flexible receiver on the
market. The integrated delta-sigma fractional-N frequency
synthesizer allows programming of the IF frequency
within a ±40Hz accuracy while operating with any refer-
ence or crystal frequencies that are available in the
host system. The integrated ADC outputs 1 or 2 quan-
tized bits for both I and Q channels, or up to 3 quan-
tized bits for the I channel. Output data is available
either at the CMOS logic or at the limited differential
logic levels.
The MAX2769 is packaged in a compact 5mm x 5mm,
28-pin thin QFN package with an exposed paddle. The
part is also available in die form. Contact the factory for
further information.
Applications
Location-Enabled Mobile Handsets
PNDs (Personal Navigation Devices)
PMPs (Personal Media Players)
PDAs (Personal Digital Assistants)
In-Vehicle Navigation Systems
Telematics (Asset Tracking, Inventory
Management)
Recreational/Marine Navigation/Avionics
Software GPS
Laptops and Ultra-Mobile PCs
Digital Still Cameras and Camcorders
FeaturesGPS/GLONASS/Galileo ReceiversNo External IF SAW or Discrete Filters RequiredProgrammable IF FrequencyFractional-N Synthesizer with Integrated VCO
Supports Wide Range of Reference FrequenciesDual-Input Uncommitted LNA for Separate
Passive and Active Antenna Inputs1.4dB Cascade Noise FigureIntegrated Crystal OscillatorIntegrated Active Antenna Sensor10mA Supply Current in Low-Power Mode2.7V to 3.3V Supply VoltageSmall, 28-Pin, RoHS-Compliant, Thin QFN Lead-
Free Package (5mm x 5mm)
Universal GPS Receiver
LNAOUT
VCCRF
MIXIN
SHDN
ANTFLAGQ0Q1I1CLKOUTXTAL
LNA2
PGM
LNA1
CPOUT
VCCVCO
SCLK
MAX2769
ANTBIAS
VCCADC25
TSENSSDATA828
IDLE
VCCCP1323VCCIFVCCD22171656
N.C.
ADCADC
FILTER
PLL
LNA2
LNA1
VCO
3-WIRE
INTERFACE
Pin Configuration/Block Diagram
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX2769ETI+ -40°C to +85°C 28 Thin QFN-EP*
MAX2769E/W -40°C to +85°C Dice (In Wafer Form)
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.MAX2769
Universal GPS Receiver
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. Typical
values are at VCC= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +4.2V
Other Pins to GND..................-0.3V to +(Operating VCC+ 0.3V)
Maximum RF Input Power..............................................+15dBm
Continuous Power Dissipation (TA= +70°C)
28-Pin Thin QFN (derates 27mW/°C above +70°C)...2500mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (TQFN only, soldering, 10s)..............+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERCONDITIONSMINTYPMAXUNITS
Supply Voltage2.72.853.3V
Default mode, LNA1 is active (Note 2)151822
Default mode, LNA2 is active (Note 2)121519
Idle Mode™, IDLE = low1.5Supply Current
Shutdown mode, SHDN = low20μA
Voltage Drop at ANTBIAS from
VCCRFSourcing 20mA at ANTBIAS0.2Vhor t- C i r cui t P r otecti on C ur r ent
at AN TBIAS AN TBIAS i s shor ted to g r ound 57mA
Acti ve Antenna D etecti on C ur r entTo asser t l og i c- hi g h at AN TFLAG 1.1mA
DIGITAL INPUT AND OUTPUT
Digital Input Logic-HighMeasure at the SHDN pin1.5V
Digital Input Logic-LowMeasure at the SHDN pin0.4V
Idle Mode is a trademark of Maxim Integrated Products, Inc.
CAUTION! ESD SENSITIVE DEVICE
MAX2769
Universal GPS Receiver
PARAMETERCONDITIONSMINTYPMAXUNITS
CASCADED RF PERFORMANCE
RF FrequencyL1 band1575.42MHz
LNA1 input active, default mode (Note 3)1.4
LNA2 input active, default mode (Note 3)2.7Noise Figure
Measured at the mixer input10.3
Out-of-Band 3rd-Order Input
Intercept PointMeasured at the mixer input (Note 4)-7dBm
In-Band Mixer Input Referred
1dB Compression PointMeasured at the mixer input-85dBm
Mixer Input Return Loss10dB
Image Rejection25dB
LO leakage-101Spurs at LNA1 InputReference harmonics leakage-103dBm
Maximum Voltage GainMeasured from the mixer to the baseband analog output9196103dB
Variable Gain Range5559dB
FILTER RESPONSE
Passband Center Frequency4MHz
FBW = 002.5
FBW = 104.2Passband 3dB Bandwidth
FBW = 018
MHz
Lowpass 3dB BandwidthFBW = 119MHz
3r d- or der fi l ter , band wi d th = 2.5M Hz, measur ed at 4M H z offset30Stopband Attenuation5th- or der fi l ter , band wi d th = 2.5M Hz, measur ed at 4M H z offset4149.5dB
LNA
LNA1 INPUT
Power Gain19dB
Noise Figure0.83dB
Input IP3(Note 5)-1.1dBm
Output Return Loss10dB
Intput Return Loss8dB
LNA2 INPUT
Power Gain13dB
Noise Figure1.14dB
Input IP3(Note 5)1dBm
Output Return Loss19dB
Input Return Loss11dB
AC ELECTRICAL CHARACTERISTICS
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
MAX2769
Universal GPS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
FREQUENCY SYNTHESIZER
LO Frequency Range0.4V < VTUNE < 2.4V15501610MHz
LO Tuning Gain57MHz/V
Reference Input Frequency844MHz
Main Divider Ratio3632,767—
Reference Divider Ratio11023—
ICP = 00.5Charge-Pump CurrentICP = 11mA
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER
Reference Input LevelSine wave0.4VP-P
Clock Output Multiply/Divide
Range÷4x2—
ADC
ADC Differential NonlinearityAGC enabled, 3-bit output±0.1LSB
ADC Integral NonlinearityAGC enabled, 3-bit output±0.1LSB
Note 1:MAX2769 is production tested at TA = +25°C. All min/max specifications are guaranteed by design and characterization
from -40°C to +85°C, unless otherwise noted. Default register settings are not production tested or guaranteed. User must
program the registers upon power-up.
Note 2:Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an
active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically
disabled and LNA2 becomes active. PLL is in an integer-N mode with fCOMP= fTCXO / 16 = 1.023MHz and ICP= 0.5mA. The
complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output
data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3:The LNA output connects to the mixer input without a SAW filter between them.
Note 4:Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz
at -60dBm/tone. Passive pole at the mixer output is programmed to be 13MHz.
Note 5:Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the
GPS center frequency of 1575.42MHz at -60dBm per tone.
MAX2769
Universal GPS Receiver
CASCADED RECEIVER GAIN
vs. PGA GAIN CODE
MAX2769 toc01
PGA GAIN CODE (DECIMAL FORMAT)
CASCADED RECEIVER GAIN (dB)555045403530252015105
TA = +25°C
TA = -40°C
TA = +85°C
CASCADED GAIN AND NOISE FIGURE
vs. TEMPERATURE
MAX2769 toc02
TEMPERATURE (°C)
NOISE FIGURE (dB)3510-15
CASCADED GAIN100
AGC GAIN
NOISE FIGURE
LNA1 |S21| AND |S12|
vs. FREQUENCY
MAX2769 toc03
FREQUENCY (GHz)
LNA1 |S21| AND |S12| (dB)
|S21|
|S12|
LNA1 GAIN AND NOISE FIGURE
vs. LNA1 BIAS DIGITAL CODE
MAX2769 toc04
LNA BIAS DIGITAL CODE (DECIMAL)
NOISE FIGURE (dB)
LNA1 GAIN (dB)1323467891011512
GAIN
NOISE FIGURE
LNA1 GAIN AND NOISE FIGURE
vs. TEMPERATURE
MAX2769 toc05
TEMPERATURE (°C)
NOISE FIGURE (dB)3510-15
LNA1 GAIN (dB)
LNA BIAS = 1000
NOISE FIGUREGAIN
Typical Operating Characteristics
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.)
MAX2769
Universal GPS Receiver
LNA2 |S21| AND |S12|
vs. FREQUENCY
MAX2769 toc07
FREQUENCY (GHz)
LNA2 |S21| AND |S12| (dB)
|S21|
|S12|
LNA2 GAIN AND NOISE FIGURE
vs. TEMPERATURE
MAX2769 toc08
TEMPERATURE (°C)
NOISE FIGURE (dB)3510-15
LNA BIAS = 10
NOISE FIGURE
GAIN
LNA INPUT RETURN LOSS
vs. FREQUENCY
MAX2769 toc09
FREQUENCY (GHz)
LNA INPUT RETURN LOSS (dB)
LNA1
LNA2
LNA OUTPUT RETURN LOSS
vs. FREQUENCY
MAX2769 toc10
FREQUENCY (GHz)
LNA OUTPUT RETURN LOSS (dB)
LNA1
LNA2
MIXER INPUT REFERRED IP1dB
vs. OFFSET FREQUENCY
MAX2769 toc11
OFFSET FREQUENCY (MHz)
MIXER INPUT REFERRED IP1dB (dB)
PRF = -100dBm
PGA GAIN = 51dB
PGA GAIN = 32dB
Typical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.)
LNA1 INPUT 1dB COMPRESSION POINT
vs. LNA1 BIAS DIGITAL CODE
MAX2769 toc06
LNA BIAS DIGITAL CODE (DECIMAL)
LNA1 INPUT 1dB COMPRESSION POINT (dBm)1323467891011512
MAX2769
1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY
MAX2769 toc12a
JAMMER FREQUENCY (MHz)
JAMMER POWER (dBm)
MAX2769 toc12b
MIXER INPUT REFERRED NOISE FIGURE
vs. PGA GAIN
MAX2769 toc13
PGA GAIN (dB)
MIXER INPUT REFERRED NOISE FIGURE (dB)45352515
Universal GPS Receiverypical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.)
3RD-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
MAX2769 toc14
BASEBAND FREQUENCY (MHz)
MAGNITUDE (dB)8765432
5TH-ORDER POLYPHASE FILTER MAGNITUDE
RESPONSE vs. BASEBAND FREQUENCY
MAX2769 toc15
BASEBAND FREQUENCY (MHz)
MAGNITUDE (dB)8765432
MIXER INPUT REFERRED GAIN
vs. PGA GAIN CODE
MAX2769 toc16
PGA GAIN CODE (DECIMAL FORMAT)
MIXER INPUT REFERRED GAIN (dB)555045403530252015105
TA = +25°C
TA = -40°C
TA = +85°C
MAX2769
Universal GPS Receiver
2-BIT ADC TRANSFER CURVE
MAX2769 toc17a
DIFFERENTIAL VOLTAGE (V)
CODE (DECIMAL VALUE)
3-BIT ADC TRANSFER CURVE
MAX2769 toc17b
DIFFERENTIAL VOLTAGE (V)
CODE (DECIMAL VALUE)
DIGITAL OUTPUT CMOS LOGIC
MAX2760 toc18
20ns/div
CLK
2V/div
SIGN DATA
2V/div
MAGNITUDE
DATA
2V/div
DIGITAL OUTPUT DIFFERENTIAL LOGIC
MAX2760 toc19
40ns/div
CLK
1V/div
SIGN+
1V/div
SIGN-
1V/div
CRYSTAL OSCILLATOR FREQUENCY
vs. DIGITAL TUNING CODE
MAX2769 toc20
CRYSTAL OSCILLATOR FREQUENCY (kHz)2420161284
16,367.90
16,367.95
16,368.00
16,368.05
16,368.10
16,367.85
TA = +25°C
TA = +85°C
TA = -40°C
CRYSTAL OSCILLATOR FREQUENCY
VARIATION vs. TEMPERATURE
MAX2769 toc21
CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm)3510-15
-4085ypical Operating Characteristics (continued)
(MAX2769 EV kit, VCC= 2.7V to 3.3V, TA= -40°C to +85°C, PGM = GND. Registers are set to the default power-up states. LNA input
is driven from a 50Ωsource. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB
gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kΩ|| 7.5pF on each pin. Typical values
are at VCC= 2.85V and TA= +25°C, unless otherwise noted.)
MAX2769
Universal GPS Receiver
DESIGNATIONQUANTITYDESCRIPTION10.47nF AC-coupling capacitor127pF PLL loop filter capacitor10.47nF PLL loop filter capacitor
C3–C860.1μF supply voltage bypass capacitor
C10, C11210nF AC-coupling capacitor
C1210.47nF AC-coupling capacitor
C1310.1nF supply voltage bypass capacitor120kΩ PLL loop filter resistor
LNAOUT
VCCRF
MIXIN
SHDN
ANTFLAGQ0Q1I1CLKOUTXTAL
LNA2
PGM
LNA1
CPOUT
VCCVCO
SCLK
MAX2769
ANTBIAS
VCCADC25
N.C.SDATA828+
IDLE
VCCCP1323VCCIFVCCD22171656
N.C.
TOP VIEWC13
C12
ACTIVE
ANTENNA BIASC2C11C10
BASEBAND
OUTPUT
BASEBANDCLOCKREFERENCEINPUT
SERIAL
INPUT
ADCADC
FILTER
PLL
LNA2
LNA1
VCO
3-WIRE
INTERFACE
Typical Application Circuit
Table 1. Component List
MAX2769
Universal GPS Receiver
Pin Description
PINNAMEFUNCTIONANTFLAGActive Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the
ANTBIAS pin.LNAOUTLNA Output. The LNA output is internally matched to 50Ω.ANTBIASBuffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.VCCRFRF Section Supply Voltage. Bypass to GND with 100nF and 100pF capacitors in parallel as close as
possible to the pin.MIXINMixer Input. The mixer input is internally matched to 50Ω.LDLock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.SHDNOperation Control Logic Input. A logic-low shuts off the entire device.SDATAData Digital Input of 3-Wire Serial InterfaceSCLKClock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising
edge of the SCLK.CSChip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high
when the loading action is completed.VCCVCOVCO Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.CPOUTCharge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and
C (see the Typical Application Circuit).VCCCPPLL Charge-Pump Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the
pin.VCCDDigital Circuitry Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.XTALXTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.CLKOUTReference Clock OutputQ1Q0
Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.VCCADCADC Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.I0I1
I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or 1-bit limited differential logic
output or analog differential voltage output.N.C.No Connection. Leave this pin unconnected.VCCIFIF Section Supply Voltage. Bypass to GND with a 100nF capacitor as close as possible to the pin.IDLEOperation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active,
and all other blocks are off.LNA2LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50Ω.PGMLogic Input. Connect to GND to use the serial interface. A logic-high allows programming to 8 hard-
coded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3.LNA1LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50Ω (see the
Typical Application Circuit).N.C.No connection. Leave this pin open.
—EPExposed Paddle. Ultra-low-inductance connection to ground. Place several vias to the PCB ground
plane.
MAX2769
Universal GPS Receiver
Detailed Description
Integrated Active Antenna Sensor
The MAX2769 includes a low-dropout switch to bias an
external active antenna. To activate the antenna switch
output, set ANTEN in the Configuration 1 register to
logic 1. This closes the switch that connects the anten-
na bias pin to VCCRF to achieve a low 200mV dropout
for a 20mA load current. A logic-low in ANTEN disables
the antenna bias. The active antenna circuit also fea-
tures short-circuit protection to prevent the output from
being shorted to ground.
Low-Noise Amplifier (LNA)
The MAX2769 integrates two low-noise amplifiers. LNA1
is typically used with a passive antenna. This LNA
requires an AC-coupling capacitor. In the default mode,
the bias current is set to 4mA, the typical noise figure and
IIP3 are approximately 0.8dB and -1.1dBm, respectively.
LNA1 current can be programmed through ILNA in
Configuration 1 register. In the low-current mode of 1mA,
the typical noise figure is degraded to 1.2dB and the IIP3
is lowered to -15dBm. LNA2 is typically used with an
active antenna. The LNA2 is internally matched to 50Ω
and requires a DC-blocking capacitor. Bits LNAMODE in
the Configuration 1 register control the modes of the two
LNAs. See Table 6 for the LNA mode settings and current
selections.
Mixer
The MAX2769 includes a quadrature mixer to output low-
IF or zero IF I and Q signals. The quadrature mixer is
internally matched to 50Ωand requires a low-side LO
injection. The output of the LNA and the input of the mixer
are brought off-chip to facilitate the use of a SAW filter.
Programmable Gain Amplifier (PGA)
The MAX2769 integrates a baseband programmable
gain amplifier that provides 59dB of gain control range.
The PGA gain can be programmed through the serial
interface by setting bits GAININ in the Configuration 3
register. Set bits 12 and 11 (AGCMODE) in the
Configuration 2 register to 10 to control the gain of the
PGA directly from the 3-wire interface.
Automatic Gain Control (AGC)
The MAX2769 provides a control loop that automatically
programs PGA gain to provide the ADC with an input
power that optimally fills the converter and establishes
a desired magnitude bit density at its output. An algo-
rithm operates by counting the number of magnitude
bits over 512 ADC clock cycles and comparing the
magnitude bit count to the reference value provided
through a control word (GAINREF). The desired magni-
tude bit density is expressed as a value of GAINREF in
a decimal format divided by the counter length of 512.
For example, to achieve the magnitude bit density of
33%, which is optimal for a 2-bit converter, program the
GAINREF to 170, so that 170 / 512 = 33%.
Baseband Filter
The baseband filter of the receiver can be programmed to
be a lowpass filter or a complex bandpass filter. The low-
pass filter can be configured as a 3rd-order Butterworth
filter for a reduced group delay by setting bit F3OR5 in the
Configuration 1 register to be 1 or a 5th-order Butterworth
filter for a steeper out-of-band rejection by setting the
same bit to be 0. The two-sided 3dB corner bandwidth
can be selected to be 2.5MHz, 4.2MHz, 8MHz, or 18MHz
(only to be used as a lowpass filter) by programming bits
FBW in the Configuration 1 register. When the complex
filter is enabled by changing bit FCENX in the
Configuration 1 register to 1, the lowpass filter becomes a
bandpass filter and the center frequency can be
programmed by bits FCEN in the Configuration 1 register.
Synthesizer
The MAX2769 integrates a 20-bit sigma-delta fractional-N
synthesizer allowing the device to tune to a required
VCO frequency with an accuracy of approximately
±40Hz. The synthesizer includes a 10-bit reference
divider with a divisor range programmable from 1 to
1023, a 15-bit integer portion main divider with a divisor
range programmable from 36 to 32767, and also a 20-bit
fractional portion main divider. The reference divider is
programmable by bits RDIV in the PLL integer division
ratio register (see Table 10), and can accommodate ref-
erence frequencies from 8MHz to 44MHz. The reference
divider needs to be set so the comparison frequency
falls between 0.05MHz to 32MHz.
CLKOUT
10nF
MAX2769
XTAL
23pF
BASEBAND
CLOCK
Figure1. Schematic of the Crystal Oscillator in the MAX2679
EV Kit
MAX2769
Universal GPS Receiver
The PLL loop filter is the only external block of the syn-
thesizer. A typical PLL filter is a classic C-R-C network
at the charge-pump output. The charge-pump output
sink and source current is 0.5mA by default, and the
LO tuning gain is 57MHz/V. As an example, see the
Typical Application Circuitfor the recommended loop-
filter component values for fCOMP= 1.023MHz and loop
bandwidth = 50kHz.
The desired integer and fractional divider ratios can be
calculated by dividing the LO frequency (fLO) by
fCOMP. fCOMPcan be calculated by dividing the TCXO
frequency (fTCXO) by the reference division ratio
(RDIV). For example, let the TCXO frequency be
20MHz, RDIV be 1, and the nominal LO frequency be
1575.42MHz. The following method can be used when
calculating divider ratios supporting various reference
and comparison frequencies:
Integer Divider= 78(d)= 000 000 0100 1110
(binary)
Fractional Divider= 0.771 x 220= 808452
(decimal) = 1100 0101 0110 0000 0100
In the fractional mode, the synthesizer should not be
operated with integer division ratios greater than 251.
Crystal Oscillator
The MAX2769 includes an on-chip crystal oscillator. A
parallel mode crystal is required when the crystal oscil-
lator is being used. It is recommended that an AC-cou-
pling capacitor be used in series with the crystal and
the XTAL pin to optimize the desired load capacitance
and to center the crystal-oscillator frequency. Take the
parasitic loss of interconnect traces on the PCB into
account when optimizing the load capacitance. For
example, the MAX2769 EV kit utilizes a 16.368MHz
crystal that is designed for a 12pF load capacitance. A
series capacitor of 23pF is used to center the crystal
oscillator frequency, see Figure 1. In addition, the 5-bit
serial-interface word, XTALCAP in the PLL Configuration
register, can be used to vary the crystal-oscillator
frequency electronically. The range of the electronic
adjustment depends on how much the chosen crystal
frequency can be pulled by the varying capacitor. The
frequency of the crystal oscillator used on the MAX2769
EV kit has a range of approximately 200Hz.
The MAX2769 provides a reference clock output. The
frequency of the clock can be adjusted to crystal-oscil-
lator frequency, a quarter of the oscillator frequency, a
half of the oscillator frequency, or twice the oscillator
frequency, by programming bits REFDIV in the PLL
Configuration register.
ADC
The MAX2769 features an on-chip ADC to digitize the
downconverted GPS signal. The maximum sampling
rate of the ADC is approximately 50Msps. The sampled
output is provided in a 2-bit format (1-bit magnitude
and 1-bit sign) by default and also can be configured
as a 1-bit, 1.5-bit, or 2-bit in both I and Q channels, or
1-bit, 1.5-bit, 2-bit, 2.5-bit, or 3-bit in the I channel only.
The ADC supports the digital outputs in three different
formats: the unsigned binary, the sign and magnitude,
or the two’s complement format by setting bits FORMAT
in Configuration register 2. MSB bits are output at I1 or
Q1 pins and LSB bits are output at I0 or Q0 pins, for I or
Q channel, respectively. In the case of 2.5-bit or 3-bit,
output data format is selected in the I channel only, the
ComparisonFrequencyRDIV
MHzMHzTCXO=ƒ==2020LOFrequencyDividerMHzLO
COMP=ƒ=157542
20MMHz=78771.
Table 2. Output Data Format
SIGN/MAGNITUDEUNSIGNED BINARYTWO’S COMPLEMENT BINARYINTEGER
VALUE1b1.5b2b2.5b3b1b1.5b2b2.5b3b1b1.5b2b2.5b3b001010110111101110111100101101011001010010101101110011000101100010001000010011101010010100100100001000000000001111001111000000011000100100001000110101101110011011111110101011010010100101011111111110110111011100010000100111110111101110111111110010000000011110110100
MAX2769
