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MAX2741AETI+ |MAX2741AETIMAXIMN/a9150avaiIntegrated L1-Band GPS Receiver
MAX2741AETI+ |MAX2741AETIMAXN/a2119avaiIntegrated L1-Band GPS Receiver
MAX2741ETI+ |MAX2741ETIMAXIMN/a12avaiIntegrated L1-Band GPS Receiver
MAX2741ETI+TMAXIMN/a2169avaiIntegrated L1-Band GPS Receiver


MAX2741AETI+ ,Integrated L1-Band GPS ReceiverApplications● In-Vehicle Navigation Systems (IVNS)N.C. 2 20 N.C.● Telematics (Vehicle and Asset Tra ..
MAX2741AETI+ ,Integrated L1-Band GPS ReceiverElectrical Characteristics(Operating conditions (unless otherwise specified): V = 2.7V to 3.0V; REF ..
MAX2741ETI+ ,Integrated L1-Band GPS Receiverapplications requiring ● Tolerates -90dBm In-Band Jammer-185dBW for indoor tracking solutions.● To ..
MAX2741ETI+T ,Integrated L1-Band GPS ReceiverElectrical Characteristics(Operating conditions (unless otherwise specified): V = 2.7V to 3.0V for ..
MAX2745ECM ,Single-Chip Global Positioning System Receiver Front-Endfeatures a voltage booster, which can Power Consumption as Low as 41mW at 2.4Vextend the power-sup ..
MAX2745ECM ,Single-Chip Global Positioning System Receiver Front-EndBlock Diagram/In-Vehicle Navigation Systems (IVNSs)Pin ConfigurationLocation-Based Services (PDAs a ..
MAX6043BAUT33#TG16 ,Precision High-Voltage Reference in SOT23ELECTRICAL CHARACTERISTICS—V = +2.5VOUT(V = +5V, I = 0, T = T to T . Typical values are at T = +25° ..
MAX6043BAUT50#TG16 ,Precision High-Voltage Reference in SOT23Features♦ +2.5V, +3.3V, +4.096V, +5.0V, or +10V OutputThe MAX6043 precision voltage reference provi ..
MAX6043CAUT33#TG16 ,Precision High-Voltage Reference in SOT23ELECTRICAL CHARACTERISTICS—V = +2.5VOUT(V = +5V, I = 0, T = T to T . Typical values are at T = +25° ..
MAX6043CAUT50#TG16 ,Precision High-Voltage Reference in SOT23 MAX6043Precision High-Voltage Reference in SOT23
MAX6045AEUR+T ,Precision, Low-Power, Low-Dropout, SOT23-3 Voltage ReferencesElectrical Characteristics—MAX6012(V = +5V, I = 0, T = T to T , unless otherwise noted. Typical val ..
MAX6045BEUR-T ,Precision / Low-Power / Low-Dropout /MAX6012/6021/6025/6030/6041/6045/605019-4777; Rev 2; 10/99Precision, Low-Power, Low-Dropout, SOT23- ..


MAX2741AETI+-MAX2741ETI+-MAX2741ETI+T
Integrated L1-Band GPS Receiver
General Description
The MAX2741 L1-band GPS receiver IC offers a
high-performance, compact solution for mobile hand-
sets and PDA applications. Total voltage gain of
80dB and a 4.7dB cascaded noise figure can pro-
vide receiver sensitivity for applications requiring
-185dBW for indoor tracking solutions.
This dual-conversion receiver downconverts the
1575.42MHz GPS signal to a 37.38MHz first IF, and then
a 3.78MHz second IF. An integrated 2- or 3-bit ADC (1-bit
SIGN, 1- or 2-bit MAG selectable) samples the second IF
and outputs the digitized signals to the baseband processor.
The integrated synthesizer offers the flexibility in fre-
quency planning to allow a single board design to be
employed for reference frequencies from 2MHz to 26MHz.
The integrated reference oscillator allows either TCXO or
crystal operation.
The receiver runs from a 2.7V to 3.0V supply, and draws
only 30mA when active. It is offered in a 28-pin thin QFN
package, and is specified for -40°C to +85°C at 3V.mmx5m8-PINTQF
Applications
●In-Vehicle Navigation Systems (IVNS)●Telematics (Vehicle and Asset Tracking, Inventory
Management)●Emergency Response Systems●Emergency Road-Side Assistance●Location-Based Services/Internet (PDAs)●Digital Cameras/Camcorders●Recreational Handhelds/Walkie-Talkies●Geographical Information Systems (GIS)●Consumer Electronics (Location-Based Games)●Precision Timing
Features
●Supports All Popular Handset Reference Frequencies
Up to 26MHz●4.7dB Cascaded Noise Figure●80dB Cascaded Gain●Tolerates -90dBm In-Band Jammer●Tolerates +13dBm CDMA Out-of-Band Jammer at
Device Input●Integrated Synthesizer and VCO●Integrated 2- or 3-Bit ADC●50dB IF AGC Range●Small 28-Pin Thin QFN Package●SPI Control Interface●Clock Output for Baseband Processor
PARTTEMP RANGEPIN-PACKAGE

MAX2741ETI-40°C to +85°C28 Thin QFN-EP*272625242322
IFOUT+IFOUT-IFIN+IFIN-N.C.N.C.91011121314
FILT
SCLK
SDI
SHDN
XTAL
REFCLK
GPSCLK
GPSIF2
GPSIF1
GPSIF0
VCC5
N.C.
SDO
GND
VCC4
VCC3VCO
3225.6MHz
VCC2
RFIN
N.C.
VCC1∑
LNA
1612.8MHz
33.6MHz
16.8MHz
200kHz0/96
/192
/16128
P.D.
REF
OSC
ADC
SPI INTERFACE
MAX2741

MUX
MAX2741Integrated L1-Band GPS Receiver
Pin Coniguration/Functional Diagram
Ordering Information
EVALUATION KIT AVAILABLE
VCC Pins to GND .................................................-0.3V to +3.3V
VCC Pins to Each Other .......................................-0.3V to +0.3V
FILT to GND .............................................-0.3V to (VCC + 0.3V)
CMOS Inputs to GND (SHDN, SCLK,
CS, SDI) ..............................................+0.3V to (VCC + 0.3V)
CMOS Outputs to GND (CLKOUT,
GPSIF_, SDO) ......................................-0.3V to (VCC + 0.3V)
RFIN to GND ............................................-0.3V to (VCC + 0.3V)
First IF Filter I/O to GND (IFOUT±, IFIN±) .....-0.3V to (VCC + 0.3V)
Crystal Inputs to GND (XTAL, REFCLK) ........-0.3V to (VCC + 0.3V)
Maximum RF Input Power ..................................................0dBm
Continuous Power Dissipation (TA = +85°C)
28-Pin Thin QFN (derate 20.8mW/°C above +70°C) ....1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V; REFCLK driven with 10MHz sinusoid, 1.2VP-P; registers set
according to mode; no RF input signal; digital baseband outputs left open; TA = -40°C to +85°C. Typical values are measured at VCC =
2.75V, TA = +25°C.)
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V for TA = -40°C to +85°C; REFCLK driven at 10MHz sinusoid,
1.2VP-P; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are mea-
sured at VCC = 2.75V, TA = +25°C.)
PARAMETERCONDITIONSMINTYPMAXUNITS

Supply Voltage2.73.0V
Supply Current
Normal operation (TA = +25°C)3042Standby (VSHDN = VIL, SYNTH:D8 = 0)0.7
Input-Logic High ThresholdVCC -
0.1V
Input-Logic Low Threshold0.1V
Input-Logic High/Low Current-10+10µA
Output-Logic HighILOAD = 100µAVCC -
0.3V
Output-Logic LowILOAD = 100µA0.3V
PARAMETERCONDITIONSMINTYPMAXUNITS
1st CONVERSION STAGE (RF TO 1st IF)

RF FrequencyL1-band1575.42MHz
RF Conversion Gain(Note 1)152132dB
Noise FigureMid-gain (CONFIG1:D4–D0 = 10000)4.7dB
Input IP3(Note 2)-30dBm
RF Image Rejection(Notes 3, 4)2035dB
LO Leakage at RFLO to RFIN pin-90dBm
CAUTION! ESD SENSITIVE DEVICE

MAX2741Integrated L1-Band GPS Receiver
Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
AC Electrical Characteristics
(Operating conditions (unless otherwise specified): VCC = 2.7V to 3.0V for TA = -40°C to +85°C; REFCLK driven at 10MHz sinusoid,
1.2VP-P; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are mea-
sured at VCC = 2.75V, TA = +25°C.)
Note 1:
Production tested for +25°C and +85°C, guaranteed by design and characterization for -40°C.
Note 2:
Test tones at 1575.8MHz and 1576.8MHz at -60dBm/tone.
Note 3:
Guaranteed by design and characterization.
Note 4:
Image frequency is 1575.42MHz + 2(fIF) = 1650.18MHz
Note 5:
Test tones at 37.38MHz and 36.88MHz at -50dBm/tone.
PARAMETERCONDITIONSMINTYPMAXUNITS
2nd CONVERSION STAGE (1st IF TO ADC INPUT)

1st IF FrequencyAt IFOUT37.38MHz
Conversion Gain Max gain (CONFIG1:D4–D0 = 11111) (Note 1)486174dB
Min gain (CONFIG1:D4–D0 = 00000) (Note 1)10dB
Input IP31st conversion (Note 5)-36dBm
Noise FigureMax gain (CONFIG1:D4–D0 = 11111)12dB
IF Output Port AdmittanceReal0.40mS
Imaginary1.5pF
IF Input Port AdmittanceReal0.40mS
Imaginary0.15pF
LPF -3dB Corner Frequency(SYNTH:D13–D10 = 1111)2.9MHz(SYNTH:D13–D10 = 0000)7.7
SYNTHESIZER

ICP_OHPLL charge-pump source current 75µA
ICP_OLPLL charge-pump sink current-100µA
Closed-Loop Phase NoiseAt 1kHz offset-55dBc/Hz
Comparison SpursAt ±200kHz offset-44dBc/Hz
Reference Oscillator FrequencySinusoid (Note 1)21026MHz
REF Input Voltage LevelSinusoid (Note 1)0.62.2VP-P
VCO Coarse Tune RangeProgrammable (CONFIG1:D7 to D5 = 000 to 111)
(Note 1)240MHz
DIGITAL I/O

SPI Clock Frequency1MHz
MAX2741Integrated L1-Band GPS Receiver
AC Electrical Characteristics (continued)
PINNAMEFUNCTIONVCC1LNA Supply Connection. External RF bypass capacitor to ground required.
2, 20, 22, 23N.C.Reserved. Make no connections to this pin.RFINLNA Input. Connect to GPS antenna through a bandpass ilter. This input requires an external matching network to match to 50Ω. AC-couple to this pin.VCC2VCO Supply Connection. External RF bypass capacitor to ground required.VCC3CML Supply Connection. External RF bypass capacitor to ground required.VCC4Digital Logic and PLL Supply Connection. External RF bypass capacitor to digital ground required.GNDGround. Connect to PC board digital ground plane.FILTPLL Loop Filter Connection. This is the output of the phase detector’s charge pump. Use the recommended ilter on EV kit for optimal phase noise and lock time.SCLKSPI Clock Input (CMOS)CSSPI Chip-Select Input (CMOS, Active Low)SDISPI Data Input (CMOS)SHDNFull IC Power-Down. This shutdown pin disables the on-chip oscillator and the rest of the IC. To keep
the oscillator running, use the software shutdown (SYNTH:D8); (CMOS, active high).XTALCrystal Oscillator Feedback Capacitor ConnectionREFCLKReference Clock Input for PLL. Drive with 1.2VP-P when using TCXO module.GPSCLKGPS Clock Output to Baseband. This is the clock used by the ADC to sample the GPS data (CMOS).GPSIF2Sampled IF Output, Bit 2 (CMOS). See Table 5.GPSIF1Sampled IF Output, Bit 1 (CMOS). See Table 5.GPSIF0Sampled IF Output, Bit 0 (CMOS). See Table 5.VCC5IF Supply Connection. External RF bypass capacitor to ground required.SDOSPI Data Output (CMOS)IFIN-1st IF Input (Inverting). Connect this 2.5kΩ differentially terminated input to the 1st IF ilter’s (-) output.IFIN+1st IF Input (Noninverting). Connect this 2.5kΩ differentially terminated input to the 1st IF ilter’s (+)
output.IFOUT-1st IF Output (Inverting). Connect this 2.4kΩ differential output to the 1st IF ilter’s (-) input.IFOUT+1st IF Output (Noninverting). Connect this 2.4kΩ differential output to the 1st IF ilter’s (+) input.VCC6RF Image-Reject Mixer Supply. External RF bypass capacitor to ground required.
Exposed
PaddleGNDRF Ground. Ultra-low inductance connection to ground. Place several vias to PC board ground plane.
MAX2741Integrated L1-Band GPS Receiver
Pin Description
Detailed Description
The MAX2741 GPS offers a high-performance superhet-
erodyne receiver solution for low-power mobile devices,
with the benefit of using the system’s existing clock ref-
erence. This receiver is ideal for integration into mobile
phone handsets using common reference frequencies
such as 10.0, 13.0, 14.4, 19.2, 20.0, and 26.0MHz. The
only external components required are the GPS RF
filter, an IF filter (typically designed from inexpensive
discretes), a three-component PLL loop filter, and a few
other resistors and capacitors. The MAX2741 integrates
the reference oscillator core, the VCO and its tank, the
synthesizer, a 1- to 3-bit ADC, and all signal path blocks
except for the 1st IF filter. The typical application area for
the receiver is less than 2cm.
RF/1st Conversion Stage (Front-End)

The MAX2741 RF front-end LNA and mixer are the most
important in the signal path. This stage sets the noise
figure for the receiver, defining the sensitivity, and mixes
the 1575.42MHz L1-band GPS signal down to a 1st IF
of 37.38MHz. The LNA itself has an NF of approximately
1.5dB; the cascaded NF of the front-end (including the
mixer) is approximately 4.7dB, and the cascaded gain is
typically 21dB.
The image-reject mixer is set up for a high-side injected
RFLO (1612.80MHz), and offers typically better than
30dB rejection of the image noise (1650.18MHz). The
-30dBm input 3rd-order intercept (IIP3) of the RF strip, in
conjunction with the GPS IF filter, provides excellent out-
of-band interferer immunity.
The 1st IF outputs (IFOUT±) are internally biased to
approximately 2V, and have a differential source imped-ance of approximately 2.5kΩ. The IF filter can be imple-
mented as a discrete L/C filter, or as a monolithic SAW or
ceramic if one is available.
IF/2nd Conversion Stage

The 2nd conversion stage consists of an active mixer, a
variable-gain amplifier (VGA), and a tunable lowpass filter.
The IF mixer is configured for low-side LO injection for a
2nd IF of 3.78MHz. Total gain in this stage is 62dB, and the
VGA offers 51dB of gain adjustment. The VGA is typically
controlled by the baseband IC through the SPI interface to
optimize the signal swing for digitization by the ADC.
The on-chip lowpass filter has an adjustable cutoff fre-
quency, programmable from 2.9MHz to 7.7MHz in 16
steps. This LPF further reduces out-of-band noise and
band-limits the signal to the ADC, ensuring that the sam-
DC offset compensation at the ADC input is performed
by an on-chip 4-bit DAC. This compensates for any DC
error introduced by transistor mismatch in the differential
stage driving the ADC input, allowing the downconverted
GPS signal’s DC level to be centered within the threshold
voltages of the ADC.
ADC

The on-chip ADC samples the down-converted GPS
signal at the 2nd IF (3.78MHz). Sampled output is pro-
vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit
(2-bit magnitude, 1-bit sign) formats, as determined by
the ADC mode configuration bit (CONFIG1:D15); see
Table 5 for details. The ADC sample clock (system GPS
clock) is derived either directly from the reference clock
(SYNTH:D9 = 1), or from an RFLO divide-by-96 block to
provide a 16.8MHz sample clock (SYNTH:D9 = 0). The
clock is available to the baseband processor at GPSCLK
(pin 15). The sampled ADC data bits are available on
pins 16, 17, and 18 (GPSIF2, GPSIF1, and GPSIF0). The
functionality of the pins is different in each mode (2-bit vs.
3-bit)—see Table 5 in determining the interface connec-
tion for the application circuit.
Synthesizer

The MAX2741 integrates an integer-N synthesizer; all
blocks except the loop filter are on-chip. The reference
can be either a crystal (driven by the internal oscillator),
or a TCXO module. The oscillator provides a 5pF load to
the crystal. A TCXO module should provide a swing in the
0.6VP-P to 2.2VP-P range.
The reference divider (/R) is programmable (SYNTH:
D7–D0), and can accommodate reference frequencies
up to 26MHz. The reference divider needs to be set so
the comparison frequency (fCOMP) at the frequency/
phase detector is 200kHz. The VCO runs at twice the
frequency of the RFLO; the RFLO is therefore generated
from the VCO using a quadrature divide-by-2 block. The
RF LO is fCOMP x 8064 (typically 1612.80MHz), and the
1st IF LO is fCOMP x 168 (typically 33.6MHz); the RF and
IF LO division ratios are not adjustable. This configuration
allows for the use of reference frequencies common to
GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets:
9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72),
19.2MHz (R = 96), 26.0MHz (R = 130), etc.
MAX2741Integrated L1-Band GPS Receiver
The VCO offers a bank of tuning capacitors that can be
latched in/out to adjust the center frequency. Because the
system does not require any RF LO frequency change
(i.e., changing channels), the VCO varactor tuning gain
is very low by design, which means the tuning range of
the VCO is narrow. The coarse-tune capacitors in the
tank circuit allow the system to adjust the VCO center
frequency as needed to guarantee that the synthesizer
can lock. In practice, process and temperature effects on
VCO centering are negligible, and a coarse-tune setting
of 110 (CONFIG:D7 to D5) will center the VCO tuning
range correctly in virtually all cases. To aid in bench and
prototype testing, the PFD offers out-of-lock-high and
out-of-lock-low indicators, available in the SPI STATUS
register (STATUS:D9 to D8). Use these flags to determine
if the VCO tuning range needs to be adjusted higher or
lower in the case where the PLL cannot lock.
The PLL filter is the only external block of the synthe-
sizer. The typical filter is a classic C-R-C two-pole shunt
network on the tune line. Low phase noise is preferred at
the expense of longer PLL settling times, so a low 10kHz
to 20kHz loop bandwidth is used. The recommended
PLL 10kHz filter implementation, with charge pump set to
200µA (CONFIG1:D10 = 1), is shown in Figure 1.
The system/GPS clock is derived either directly from the
reference oscillator, or synthesized from the RFLO (see
the ADC section). This clock is used as the sampling clock
for the on-chip ADC, and is seen at pin 15, GPSCLK.
SPI Bus, Address and Bit Assignments

An SPI-compatible serial interface is used to program the
MAX2741 for configuring the different operating modes. In
addition, data can be read out of the MAX2741 for status
and diagnostic use. The serial interface is controlled by
four signals: SCLK (serial clock), CS (chip-select), SDI
(data input), and SDO (data output).
The control of the PLL, AGC, test, offset management,
and block selection is performed through the SPI bus
from the baseband controller. A 20-bit word, with the MSB
(D15) being sent first, is clocked into a serial shift register
when the chip-select signal is asserted low.
The SPI bus has four control lines: serial clock (SCLK),
chip-select (CS), data in (SDI), and data out (SDO).
Enable SDO functionality by setting the digital test bus
bits: CONFIG1:D9 to D8 = 01. The timing of the interface
signals is shown in Figure 2 and Table 1 along with typical
values for setup and hold time requirements.
For best performance, the SPI bus should be configured
during the startup initialization and then left with the opti-
mum values in the registers. Any changes to the ADC
and VGA bits during GPS signal processing may cause
glitches and corrupt the analog signal path. Reading from
the SPI bus does not interrupt GPS operation.
Figure 1. Recommended 3rd-Order PLL Filter
Figure 2. SPI Timing Diagram
Table 1. SPI Timing Requirements
SYMBOLPARAMETERTYP
VALUEUNITS

tSETUPDData to SCLK setup20ns
tPERIODSCLK period100ns
tHDATAData hold to SCLK20ns
tSETUPSSCS to SCLK disable20ns
tENDFalling SCLK to CS inactive20nsVCC4GND9
FILT
SCLK
MAX2741

22nF
36kΩ
100pF
LSBMSB
SCLK
SDI
tSETUPD
tHDATAtPERIOD
tEND
tSETUPSS
MAX2741Integrated L1-Band GPS Receiver
Table 2. Register Address and Data Bit Assigments (Write)
Table 3. Register Address and Data Bit Assigments (Read)
REGISTER
NAME
DATAADDRESS
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A1A0

SYNTH
Reserved
LPF Autotune
Initiate
LPF T
uning
ord (MSB)
LPF T
uning
ord
LPF T
uning
ord
LPF T
uning
ord (LSB)
Clock
Select
Standby
PLL
Ref Div
Ratio (MSB)PLL
Ref Div
Ratio
PLL
Ref Div
Ratio
PLL
Ref Div
Ratio
PLL
Ref Div
Ratio
PLL
Ref Div
Ratio
PLL
Ref Div
Ratio
PLL
Ref Div
Ratio (LSB)100
CONFIG 1
ADC Mode
ADC Of
fset Control
(LSB)
ADC Of
fset Control
ADC Of
fset Control
(MSB)
ADC Of
fset Control
(SIGN)
Double Charge-
Pump Current
Digital
est
Bus
Mode Select (MSB)
Digital
est
Bus
Mode Select (LSB)
VCO
Coarse T
uning
Range (MSB)
VCO
Coarse T
uning
Range
VCO
Coarse T
uning
Range (LSB)
AGC Gain (MSB)
AGC GainAGC GainAGC Gain
AGC Gain (LSB)101
CONFIG 2
Reset CMOS
Drive VCO Low
Drive VCO
High
ReservedReservedReservedReservedReservedReservedReservedReserved
Analog
est
Mode Select
Analog
est
Mode Select
Analog
est
Mode Select
Analog
est
Mode Select
Analog
est
Mode Select110
REGISTER
NAME
DATAADDRESS
D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0A3A2A1A0

STATUS
ReservedReservedReservedReservedReservedReserved
Out-of-Lock
(High)
Out-of-Lock
(Low)
Clock
Selected
Parity
Reserved
LPF Auto-
calibrate EndLPF Autotune
(MSB)
LPF AutotuneLPF AutotuneLPF Autotune
(LSB)111
MAX2741Integrated L1-Band GPS Receiver
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