MAX2165ETI+T ,Single-Conversion DVB-H Tunerfeatures an I/Q baseband interface.Duty CycleThe MAX2165’s direct-conversion architecture elimi-♦ D ..
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The MAX216 transceiver is designed specifically for com-
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MAX218CAP ,1.8V to 4.25V-Powered, True RS-232 Dual TransceiverELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V = 1.8V to 4.25V, C1 = 0.47µF, C2 = C3 = C4 = 1µF, ..
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MAX527DCWG ,Galibrated Quad 12-Bit Voltage-Output D/A ConvertersGeneral Description
The MAX526/MAX527 contain four 12-bit, voltage-output digi-
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MAX527DCWG+ ,Calibrated, Quad, Voltage-Output, 12-Bit DACELECTRICAL CHARACTERISTICS - MAX526
(VDD = +15V, Vss = -5V, VREF = 10V, AGND = DGND = OV, TA = TNN ..
MAX527DCWG+ ,Calibrated, Quad, Voltage-Output, 12-Bit DACApplications
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MAX528CAG ,Octal, 8-Bit, Serial DACs with Output BufferELECTRICAL CHARACTERISTICS - MAX528
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MAX528CAG ,Octal, 8-Bit, Serial DACs with Output BufferGeneral Description
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' Buffer D ..
MAX2165ETI+T
Single-Conversion DVB-H Tuner
General DescriptionThe MAX2165 direct-conversion tuner IC is designed for
handheld digital video broadcast (DVB-H) applications.
The tuner covers a 470MHz to 780MHz input frequency
range and features an I/Q baseband interface.
The MAX2165’s direct-conversion architecture elimi-
nates the need for an IF-SAW filter, allowing for
reduced bill of materials cost. The design integrates a
variable-gain, low-noise amplifier (LNA); a notch filter;
an RF tracking filter; a quadrature mixer; a power
detector; programmable baseband lowpass channel-
selection filters; baseband variable-gain amplifiers
(VGA); DC offset correction circuitry; and a complete
fractional-N frequency synthesizer. The part is program-
mable through a 2-wire I2C-compatible serial interface.
The MAX2165 integrates a tuneable notch filter. This fil-
ter is designed to notch out interfering signals in the
830MHz to 950MHz frequency range to allow for opera-
tion in the presence of large cellular signals.
Programmable baseband channel-selection filters allow
for operation with 7MHz and 8MHz channels. Digital DC
offset correction circuitry supports time-sliced operation
by minimizing power-up time delay. The fractional-N
synthesizer reduces VCO lock time and minimizes
close-in phase noise, eliminating the need for power-
hungry, phase-noise reduction algorithms.
The MAX2165 is available in a tiny, 5mm x 5mm x
0.8mm, 28-pin thin QFN package with an exposed pad-
dle. It is specified for operation over the -40°C to +85°C
extended temperature range.
ApplicationsDVB-H Handheld Receivers
DVB-T Portable Devices
DMB-T/H Portable Devices
ISDB-T Receivers (13 Segment)
Features93mA (typ) Current Consumption from a Single
+2.85V Supply Voltage21mW (typ) Average Power Consumption at 8%
Duty CycleDirect-Conversion Architecture Eliminates IF-
SAW FilterIntegrated RF Tuneable Notch Filter for Operation
in the Presence of Cellular BlockersIntegrated DC Offset Correction CircuitryIntegrated RF Notch Filter for Operation in the
Presence of Up to -7dBm Cellular BlockersExtended UHF Band Operation5mm x 5mm x 0.8mm, 28-Pin Thin QFN Package
MAX2165
Single-Conversion DVB-H TunerMAX216591011121314272625242322
LDO
VTUNE
BBI+
BBI-
VCC_VCO
BB_AGC
GND_TUNE
N.C.
RFIN
ADDR
VCC_RF
LEXT
SCL
SDA
VCC_BB
BBQ+
OVLD_DET
STBY
RF_AGCVCC_XTALREFOUTMUXVCC_SYNCPXE
BBQ-
SERIAL INTERFACE, CONTROL,
AND SYNTHESIZER
CHARGE
PUMP90°
PWRDET
DAC
CONTROL
BLOCK
SHDN
THIN QFN
5mm x 5mm
Pin Configuration/
Functional Diagram
Ordering Information19-0646; Rev 1; 3/09
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX2165ETI+-40°C to +85°C28 TQFN-EP*
MAX2165
Single-Conversion DVB-H Tuner
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(MAX2165 EV kit, VCC= +2.75V to +3.3V, VRF_AGC= VBB_AGC= 2.3V (maximum gain), no RF input signals at RFIN, default register set-
tings, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +2.85V, TA= +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS(MAX2165 EV kit, VCC= +2.75V to +3.3V, VRF_AGC= VBB_AGC= 2.3V (maximum gain), VOUT= 1VP-P, 75Ωsystem impedance, reg-
isters set according to the specified default register conditions, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +2.85V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
All VCCPins to GND..............................................-0.3V to +3.6V
GND_TUNE to GND..............................................-0.3V to +0.3V
All Other Pins to GND.................................-0.3V to (VCC+ 0.3V)
BBI_, BBQ_ Short Circuit to Ground Duration...............Indefinite
Maximum RF Input Power..............................................+13dBm
Continuous Power Dissipation (TA= +70°C)
28-Pin Thin QFN (derate 34.5mW/°C above +70°C).....2758mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITS
SUPPLY VOLTAGE AND CURRENT Supply Voltage 2.75 3.30 V
LNASW = 1 (RF LNA on) 109 134 Supply Current LNASW = 0 (RF LNA off) 93 116 mA
Shutdown Current 20 μA
Gain-Control Voltage Required to obtain full range of RF and baseband gain 0.4 2.3 V
RF_AGC and BB_AGC Input
Bias Current VAGC at +0.4V and +2.3V -50 +50 μA
SERIAL INTERFACE Input Logic-Level Low 0.3 x
VCCV
Input Logic-Level High 0.7 x
VCC V
Input Hysteresis 0.05 x
VCC V
SDA, SCL Input Current -10 +10 μA
Output Logic-Level Low ISINK = 0.3mA 0.4 V
Output Logic-Level High ISOURCE = 0.3mA VCC -
0.4 V
PARAMETERCONDITIONSMINTYPMAXUNITS
OVERALL PERFORMANCE (RF INPUT TO BASEBAND OUTPUTS)Meets specified performance470783Operating Frequency RangeOperates with derated performance (Note 2)470832MHz
Input Return Loss50Ω system, w or st case acr oss b and , any g ai n- contr ol 7dB
CAUTION! ESD SENSITIVE DEVICE
MAX2165
Single-Conversion DVB-H Tuner
PARAMETERCONDITIONSMINTYPMAXUNITSMaximum gain7482
Voltage GainZSOURCE = 75Ω, ZLOAD >
1kΩMinimum gain on
(LNASW = 1)2329dB
RF Gain-Control Range0.4V ≤ VRF_AGC ≤ 2.3V2934dB
Baseband Gain-Control Range0.4V ≤ VBB_AGC ≤ 2.3V2125dB
LNA Gain StepGain change caused by switching RF LNA on (LNASW =
1) and off (LNASW = 0)13.517dB
LNA Gain Step Phase ChangePhase change caused by switching RF LNA on (LNASW
= 1) and off (LNASW = 0)10degrees
At 470MHz3.86.5Noise Figure (Note 3)At 783MHz4.06.5dB
Maximum gain09Input IP2 (Note 4)23dB gain reduction26dBm
Maximum gain-20-4Input IP3 (Note 5)23dB gain reduction17dBm
In-Band Input P1dBMaximum gain (Note 6)-22dBm
Cellular Tx blocker gain compression1.23Cellular Blocker Desensitization
(Note 7)Cellular Tx blocker noise figure rise3dB
In-Band IM3Two tones (782.8MHz and 782.3MHz) within passband of
baseband filter, 780MHz LO frequency-55-40dBc
170MHz to 960MHz RF input frequency< -60RF Beats Converted to Output960MHz to 1400MHz RF input frequency< -60dBc
RF IsolationDC to 50MHz, RF input to baseband outputs relative to
desired channel-60dBc
I/Q Output SwingZLOAD = 10kΩ || 10pF0.51VP-P
I/Q DC VoltageI+, I-, Q+, Q- outputs to groundVCC / 2V
Phase error2degreesI/Q Quadrature AccuracyAmplitude error-1.5+1.5dB
50MHz to 470MHz-38-33
470MHz to 878MHz-52-35
878MHz to 1732MHz-49-35
dBmV
Spurious Emissions at RF Input
(Note 3)
Spur at four times Rx frequency, tested at fLO = 474MHz,
fSPUR = 1896MHz-58-51dBm
1kHz offset to 10kHz (Note 3)-86-96
1MHz offset (Note 3)-108-126Closed-Loop Phase Noise
> 10MHz offset-140
dBc/Hz
AC ELECTRICAL CHARACTERISTICS (continued)(MAX2165 EV kit, VCC= +2.75V to +3.3V, VRF_AGC= VBB_AGC= 2.3V (maximum gain), VOUT= 1VP-P, 75Ωsystem impedance, reg-
isters set according to the specified default register conditions, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +2.85V, TA= +25°C, unless otherwise noted.) (Note 1)
MAX2165
Single-Conversion DVB-H Tuner
AC ELECTRICAL CHARACTERISTICS (continued)(MAX2165 EV kit, VCC= +2.75V to +3.3V, VRF_AGC= VBB_AGC= 2.3V (maximum gain), VOUT= 1VP-P, 75Ωsystem impedance, reg-
isters set according to the specified default register conditions, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +2.85V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITSPower-Up TimeShutdown to full operation, VCO settled to the Rx
frequency, DC offset calibrated (Note 8)< 120ms
BASEBAND FILTERSLower corner (Note 9)0 or
200Hz
Upper corner at 3.85MHz (UHF mode), TA = +25°C0.95Passband Cutoff Attenuation
Upper corner at 3.35MHz (VHF mode), TA = +25°C2.75dB
Amplitude RippleTA = +25°C0.51.5dBP-P
Group Delay Ripple150µsP-P
Group Delay Matching5ns
4.75MHz (VHF mode) (Note 11)23
5.25MHz (UHF mode) (Note 11)23
14.5MHz (VHF and UHF mode) (Note 12)5975Rejection Ratio (Note 10)
> 16.2MHz84
FRACTIONAL SYNTHESIZERRF N-Divider Ratio7251
RF R-Divider Ratio12
Fractional RatioLength of fractional accumulator (Note 13)20bits
Integer SpursWorst-case spur inside baseband filter bandwidth-60dBc
Settling Time35MHz step, settled to within 100Hz frequency error / 20°
phase error200µs
ICP = 00.6Charge-Pump CurrentICP = 11.2mA
Charge-Pump Leakage-10+10µA
REFERENCE OSCILLATORReference Frequency426MHz
Reference Buffer Output Voltage
Swing10kΩ || 10pF load0.51VP-P
Input ImpedanceWhen used as a passive input for an external reference
oscillator12kΩ
Input VoltageWhen used as a passive input for an external reference
oscillator100600mVRMS
OVERLOAD DETECTORAttack-Point Accuracy±2.5dB
Attack-Point Increment3-bit DAC, change per LSB step2.5dB
Detector on0.1mADetector Output SinkDetector off5µA
MAX2165
Single-Conversion DVB-H Tuner
AC ELECTRICAL CHARACTERISTICS (continued)(MAX2165 EV kit, VCC= +2.75V to +3.3V, VRF_AGC= VBB_AGC= 2.3V (maximum gain), VOUT= 1VP-P, 75Ωsystem impedance, reg-
isters set according to the specified default register conditions, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC= +2.85V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITSDetector Gain150V/V
Detector Response Time5µs
2-WIRE SERIAL INTERFACEClock RateI2C fast mode, slave category400kHz
Note 1:Min and max limits are guaranteed by test at TA= +25°C and are guaranteed by design and characterization at TA=
-40°C and +85°C. The default register settings are not production tested. Load registers no sooner than 100µs after
power-up.
Note 2:Notch filter must be disabled by programming the TF_NTCH[3:0] bits to 1111 to enable operation up to 832MHz. Under
extreme conditions, the part can experience up to 3dB degradation in sensitivity and intermodulation distortion.
Note 3:Guaranteed by design and characterization over the specified operating conditions. Not production tested.
Note 4:UHF tones resulting in f1- f2beat frequency within the baseband output. Two tones at 350MHz and 1133MHz
with IM2 measured at 783MHz.
Note 5:Two tones converted to 5.25MHz and 10.75MHz, IM3 measured at 250kHz.
Note 6:A desired signal at PDESIRED= -78dBm is injected and downconverted to 3.75MHz. A blocker tone is injected at 10MHz
higher in frequency. Specified level is blocker power at which desired output signal compresses by 1dB. TA= +25°C.
Note 7:A single blocker at -7dBm with a bandwidth of less than 4MHz is injected at 880MHz with the receiver tuned to 783MHz
and set to maximum gain.
Note 8:VCO locked to within 100Hz of the Rx frequency. Wake-up initiated by toggling the SHDNpin from low to high and con-
necting the STBYpin to ground.
Note 9:Applies to continuous DC correction operation (DVB-T mode). In DVB-H mode, optional correction hold feature allows
quasi-DC-coupling.
Note 10:Depends on 7MHz/8MHz bandwidth mode.
Note 11:Equivalent to video carrier in upper adjacent channel. TA= +25°C.
Note 12:Equivalent to fNYQUIST- 3.8MHz for 18.3MHz sampling rate baseband DAC.
Note 13:Total frequency resolution is fREF/ 220, or approximately 20Hz with a 20MHz reference frequency.
Typical Operating Characteristics(MAX2165 EV kit, VCC= +2.85V, default register settings, VRF_AGC= VBB_AGC= 2.3V, VIOUT= VQOUT= 500mVP-P, TA= +25°C,
unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGEVCC (V)
(mA)
MAX2165 toc01
TA = -40°C
TA = +85°C
TA = +25°C
VOLTAGE GAIN vs. FREQUENCYFREQUENCY (MHz)
GAIN (dB)
MAX2165 toc02
TA = -40°C
TA = +85°C
TA = +25°C
VOLTAGE GAIN vs. RFAGCMAX2165 toc03
TA = +85°C
TA = -40°C
TA = +25°C
BB_AGC = 2.3V
GAIN (dB)
RF_AGC CONTROL VOLTAGE (V)
MAX2165
Single-Conversion DVB-H Tuner
RF INPUT RETURN LOSS
vs. FREQUENCYFREQUENCY (MHz)
RETURN LOSS (dB)
MAX2165 toc07
ZO = 75Ω
TRACKING FILTER SETTING "7"
TRACKING FILTER SETTING "15"
TRACKING FILTER SETTING "1"
FREQUENCY (MHz)
GAIN (dB)
MAX2165 toc08
NORMALIZED BASEBAND
FREQUENCY RESPONSE
A: +2 ADJUSTMENT FACTOR
B: +1 ADJUSTMENT FACTOR
C: 0 ADJUSTMENT FACTOR
D: -1 ADJUSTMENT FACTOR
E: -2 ADJUSTMENT FACTOR
F: -3 ADJUSTMENT FACTOR
G: -4 ADJUSTMENT FACTOR
H: -5 ADJUSTMENT FACTOR
I: -6 ADJUSTMENT FACTOR
NORMALIZED BASEBAND
FREQUENCY RESPONSEFREQUENCY (MHz)
GAIN (dB)
MAX2165 toc09420
-100.0-6 ADJUSTMENT FACTOR
+0 ADJUSTMENT FACTOR
+2 ADJUSTMENT FACTOR
VOLTAGE GAIN vs. BBAGCBB_AGC CONTROL VOLTAGE (V)
GAIN (dB)
MAX2165 toc040.51.01.52.02.5
RF_AGC = 2.3V
TA = +85°C
TA = -40°C
TA = +25°C
NOISE FIGURE vs. FREQUENCYFREQUENCY (MHz)
NOISE FIGURE (dB)
MAX2165 toc05
TA = +85°CTA = +25°C
TA = -40°C
NOISE FIGURE vs. RF Tx INPUT POWERRF Tx INPUT POWER (dBm)
NOISE FIGURE (dB)
MAX2165 toc06
-7.5-5.0
BLOCKER AT 880MHz
PHASE NOISE vs. RF FREQUENCY
RF FREQUENCY (MHz)
PHASE
NOISE
(dB
MAX2165 toc10
10kHz OFFSET
PHASE NOISE vs. OFFSET FREQUENCYOFFSET FREQUENCY (kHz)
PHASE NOISE (dBm/Hz)
MAX2165 toc11
-5010100100010,000
Typical Operating Characteristics (continued)
(MAX2165 EV kit, VCC= +2.85V, default register settings, VRF_AGC= VBB_AGC= 2.3V, VIOUT= VQOUT= 500mVP-P, TA= +25°C,
unless otherwise noted.)
MAX2165
Single-Conversion DVB-H Tuner40kΩ PULLUP TO 2.85V
PD_TH[2:0] = 000
PD_TH[2:0] = 111
POWER-DETECTOR OUTPUT VOLTAGE
vs. RF INPUT POWERRF INPUT POWER (dBm)
POWER-DETECTOR OUTPUT VOLTAGE (V)
MAX2165 toc12
Typical Operating Characteristics (continued)
(MAX2165 EV kit, VCC= +2.85V, default register settings, VRF_AGC= VBB_AGC= 2.3V, VIOUT= VQOUT= 500mVP-P, TA= +25°C,
unless otherwise noted.)
REFERENCE BUFFER OUTPUT SIGNALMAX2165 toc13
200mV/div
20ns/div
10kΩ || 10pF LOAD
Pin Description
PINNAMEFUNCTIONSDASerial-Data Input/Output. Requires a pullup resistor to VCC.SCLSerial-Clock Input. Requires a pullup resistor to VCC.N.C.No Connection. Connect this pin to ground.RFINRF Input. Internally matched to 75Ω. Requires a DC-blocking capacitor.ADDRAddress-Select Input. Selects the I2C slave address. See Table 20.VCC_RFRF Power-Supply Input. Connect to a low-noise, power-supply voltage. Bypass to the PCB ground
plane with a 2200pF and 100nF capacitor placed as close as possible to the pin.LEXTExternal Inductor Connection. Connect to VCC with a 39nH inductor.RF_AGCRF Gain-Control Voltage Input. Accepts voltages from 0.4V to 2.3V with 2.3V providing maximum RF
gain. This pin can also be controlled by the OVLD_DET output. See the Typical Application Circuit.SHDNShutdown Input. Drive this pin low to disable all internal circuits and to put the device into low-power
shutdown mode. Drive this pin high for normal operation.STBYStandby Input. Controls the power-up sequence of the chip. See the Power-Up Sequence section for
more information on this pin’s operation.OVLD_DET
Overload-Detection Output. This output provides an error signal between the internal power-detector
output voltage and an internal programmable reference voltage. This output can be connected to the
RF_AGC input to implement a closed RF automatic gain-control loop.VCC_BBBaseband Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB
ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.BBQ-Inverting Quadrature Baseband Output
MAX2165
Detailed Description
Register DescriptionsThe MAX2165 includes 15 programmable registers and
three read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all reg-
isters. U labeled under each bit name indicates that the
bit value is user defined to meet specific application
requirements. A 0 or 1 indicates that the bit must be set
to the defined 0 or 1 value for proper operation.
Operation is not tested or guaranteed if these bits are
programmed to other values and is only for
factory/bench evaluation. In typical application, always
program to the operation defined state.
See Tables 2–19 for detailed descriptions of each reg-
ister. All registers must be written 100µs after power-up
and no earlier than 100µs after power-up.
Single-Conversion DVB-H Tuner
Pin Description (continued)
PINNAMEFUNCTIONBBQ+Noninverting Quadrature Baseband OutputBBI-Inverting In-Phase Baseband OutputBBI+Noninverting In-Phase Baseband OutputBB_AGCBaseband Gain-Control Voltage Input. Accepts voltages from 0.4V to 2.3V with 2.3V providing the
maximum baseband gain.VCC_VCOVCO Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB ground
plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.VTUNEVCO Tuning Voltage Input. Connect to the PLL loop filter output.GND_TUNEVCO Tuning Voltage Ground. Connect to the PCB ground plane.LDOVCO Linear-Regulator Noise Bypass. Bypass to the PCB ground plane with a 470nF capacitor placed
as close as possible to the pin.CPCharge-Pump Output. Connect to the PLL loop filter input.VCC_SYNSynthesizer Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the PCB
ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.MUX
Multiplexed Output Line. Output for various test functions, can also be used as a PLL lock-detect
indicator. See Table 9 for more information. When used as a PLL lock detector, logic-high indicates
PLL is not locked and logic-low indicates PLL is locked.REFOUTReference Buffer Output. Provides a buffered crystal-oscillator signal that can be used as a clock
reference for the demodulator. Requires a DC-blocking capacitor.VCC_XTALCrystal-Oscillator Power-Supply Input. Connect to a low-noise power-supply voltage. Bypass to the
PCB ground plane with a 1000pF and 100nF capacitor placed as close as possible to the pin.XBReference Input. Connect to a parallel resonant mode crystal through a load-matching capacitor or to
a reference oscillator.XEReference-Oscillator Feedback Input. Connect to a capacitive feedback network when the on-chip
reference oscillator is used. Leave unconnected when an external reference is used.EPExposed Paddle. Solder evenly to the board’s ground plane to achieve the lowest impedance path.
MAX2165
Single-Conversion DVB-H Tuner
REGISTER SETTINGSMSB LSB
DATA BYTEREGISTER
NAME
REGISTER
ADDRESSOPERATION
DEFINED
DEFAULT
(POR)D7D6D5D4D3D2D1D0N-Divider Integer0x00—H17N7
N-Divider Frac20x01—H18X
FRAC
F19
F18
F17
F16
N-Divider Frac10x02—H00F15
F14
F13
F12
F11
F10
N-Divider Frac00x03—H00F7
Tracking Filter0x04—H72TF_NTCH3
TF_NTCH2
TF_NTCH1
TF_NTCH0
TF_BAL3
TF_BAL2
TF_BAL1
TF_BAL0
LNA0x05—H01X
LNASW
PLL
Configuration0x06—H0ARDIV
ICP
CPS
ADLY0
ADLY0
LFDIV2
LFDIV1
LFDIV0
Test0x07—H08CP_TST2
CP_TST1
CP_TST0
LD_MUX2
LD_MUX1
LD_MUX0
Shutdown0x08—H00X
SHDN_REF
SHDN_SYN
SHDN_RF
SHDN_BB
SHDN_PD
SHDN_BG
VCO Control0x09—H50VCO1
VCO0
BS2
BS1
BS0
VAS
ADL
ADE
Baseband
Control0x0A—HF3BB_BW3
BB_BW2
BB_BW1
BB_BW0
BB_BIA0
PD_TH2
PD_TH1
PD_TH0
DC Offset Control0x0BH79H71XDC_DAC8DC_MO1
DC_MO0
DC_SP1
DC_SP0
DC_TH1
DC_TH0
DC Offset DAC0x0CH00H00DC_DAC7
DC_DAC6
DC_DAC5
DC_DAC4
DC_DAC3
DC_DAC2
DC_DAC1
DC_DAC0
ROM Table
Address0x0D—H00X
FUSE_TH
TFA3
TFA2
TFA1
TFA0
Reserved0x0EH00H00X
ROM Table Data
Readback0x10N/AN/ATRF7TRF6TRF5TRF4TRF3TRF2TRF1TRF0
Chip Status
Readback0x11N/AN/APORVASAVASELDDC_LODC_HIXPD_OVLD
Autotuner
Readback0x12N/AN/AVCO1VCO0BS2BS1BS0ADC2ADC1ADC0
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONN[7:0]7–0Programs the integer value of the PLL N-divider ratio. Default integer divide value is 23.
Table 1. Register Configuration*
Table 2. N-Divider Integer Register (Address: 0x00)*See the Register Descriptions section for more information on recommended settings.
MAX2165
Single-Conversion DVB-H Tuner
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTION7, 6, 5Reserved. Set to 000 for normal operation.
FRAC4
PLL mode select:1 = Fractional mode selected.
0 = Integer mode selected.
F[19:16]3–0Sets the 4 most significant bits of the fractional PLL divider ratio.
Table 3. N-Divider Frac2 Register* (Address: 0x01)
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONF[15:8]7–0Sets bits 15 through 8 of the fractional PLL divider ratio.
Table 4. N-Divider Frac1 Register* (Address: 0x02)*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONF[7:0]7–0Sets the 8 least significant bits of the fractional PLL divider ratio.
Table 5. N-Divider Frac0 Register* (Address: 0x03)*When programming the fractional divider ratio, all three fractional divider registers must be written before the ratio is updated.
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONTF_NTCH[3:0]7–4
Programs the notch frequency of the internal tracking filter. Optimal values for notch
frequencies of 783MHz and 725MHz can be read from the ROM table entries. See the
Reading the ROM Table section.
TF_BAL[3:0]3–0Programs the tracking filter balun. Optimum values over frequency can be interpolated
from the ROM table entries. See the Reading the ROM Table section.
Table 6. Tracking Filter Register (Address: 0x04)
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTION7–1Reserved. Set to all zeros for normal operation.
LNASW0
LNA enable:1 = LNA is enabled.
0 = LNA is disabled.
Table 7. LNA Register (Address: 0x05)
MAX2165
Single-Conversion DVB-H Tuner
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONCP_TST[2:0]7, 6, 5
Charge-pump test modes:000 = Normal operation.
100 = Force charge pump into low-impedance state.
101 = Force charge-pump source current.
110 = Force charge-pump sink current.
111 = Force charge pump into high-impedance state.4, 3Reserved. Set to 01 for normal operation.
LD_MUX[2:0]2, 1, 0
Selects which signal is output to the MUX pin:000 = PLL lock indicator (normal operation).
001 = N-divider output (after divide by 2).
010 = R-divider output (after divide by 2).
011 = Factory use only.
1XX = Factory use only.
Table 9. Test Register (Address: 0x07)
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTIONRDIV7
Selects the PLL reference divider:1 = Divide reference by 2.
0 = Divide reference by 1.
ICP6
Selects the charge-pump current:1 = 1.2mA
0 = 0.6mA
CPS5
Selects how the charge-pump current is programmed:1 = Charge-pump current is automatically programmed to the optimal setting by the VCO
autotuner.
0 = Charge-pump current is set manually by programming the ICP bit.
ADLY[1:0]4, 3
Sets the VCO autoselect wait time:00 = ~200µs
01 = ~400µs
10 = ~800µs
11 = ~1600µs
LF_DIV[2:0]2, 1, 0
Sets the prescaler for internal low-frequency clocks; program these bits so the
crystal frequency divided by the prescaler value is equal to 2MHz:000 = Divide by 8 (for 16MHz crystals).
001 = Divide by 9 (for 18MHz crystals).
010 = Divide by 10 (for 20MHz crystals).
011 = Divide by 11 (for 22MHz crystals).
100 = Divide by 12 (for 24MHz crystals).
101 = Divide by 13 (for 26MHz crystals).
110 = Divide by 14 (for 28MHz crystals).
111 = Divide by 2 (for 4MHz crystals).
Table 8. PLL Configuration Register (Address: 0x06)
MAX2165
Single-Conversion DVB-H Tuner
BIT NAMEBIT LOCATION
(0 = LSB)FUNCTION7Reserved. Set to 0 for normal operation.
SHDN_REF6
Crystal-oscillator buffer shutdown control:1 = Buffered crystal-oscillator output is disabled.
0 = Buffered crystal-oscillator output is enabled.
o t e : The cr ystal osci l l ator i s acti vated b y ei ther the S H D N _S Y N b i t or the S H D N _RE F b i t. If
ei ther b i t i s 0, the cr ystal osci l l ator i s enab l ed . If b oth ar e 1, the cr ystal osci l l ator i s d i sab l ed .5Reserved. Set to 0 for normal operation.
SHDN_SYN4
PLL shutdown control:1 = PLL is disabled.
0 = PLL is enabled.
o t e : The cr ystal osci l l ator i s acti vated b y ei ther the S H D N _S Y N b i t or the S H D N _RE F b i t. If
ei ther b i t i s 0, the cr ystal osci l l ator i s enab l ed . If b oth ar e 1, the cr ystal osci l l ator i s d i sab l ed .
SHDN_RF3
RF front-end shutdown control:1 = RF circuits are disabled.
0 = RF circuits are enabled.
SHDN_BB2
ix e r , b a s e b a n d f ilt e r s , a n d b a s e b a n d va r ia b le - g a i n a m p l if ie r s ( VG A ) s h u t d o w n c o n t r o l: 1 = Mixer, baseband filters, and baseband VGA are disabled.
0 = Mixer, baseband filters, and baseband VGA are enabled.
SHDN_PD1
Baseband power-detector shutdown control:1 = Baseband power detector is disabled.
0 = Baseband power detector is enabled.
SHDN_BG0
Main bias shutdown control:1 = Main bias circuits are disabled.
0 = Main bias circuits are enabled.
o t e : The main bias circuits can and will be shut down once all other blocks are shutdown (all bits in the Shutdown register are set to 1, and the VCO[1:0] bits in the VCO
Control register and the DC_MO[1:0] in the DC Offset Control register are set to 00).
Table 10. Shutdown Register (Address: 0x08)
