MAX19700ETM+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX19700ETM+T ,7.5Msps, Ultra-Low-Power Analog Front-EndFeaturesThe MAX19700 is an ultra-low-power, mixed-signal ana-♦ Dual 10-Bit Rx ADC and Dual 10-Bit T ..
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MAX19700ETM+T
7.5Msps, Ultra-Low-Power Analog Front-End
General Description
The MAX19700 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for TD-SCDMA handsets
and data cards. Optimized for high dynamic perfor-
mance at ultra-low power, the MAX19700 integrates a
dual 10-bit, 7.5Msps receive (Rx) ADC, dual 10-bit,
7.5Msps transmit (Tx) DAC with TD-SCDMA baseband
filters, and three fast-settling 12-bit aux-DAC channels
for ancillary RF front-end control. The typical operating
power in Tx-Rx FAST mode is 36.3mW at a 5.12Msps
clock frequency.
The Rx ADCs feature 54.9dB SINAD and 78dBc SFDR
at a 1.87MHz input frequency with a 7.5Msps sample
frequency. The analog I/Q input amplifiers are fully dif-
ferential and accept 1.024VP-Pfull-scale signals.
Typical I/Q channel matching is ±0.22°phase and
±0.02dB gain.
The Tx DACs with TD-SCDMA lowpass filters feature
-3dB cutoff frequency of 1.27MHz and >55dB stop-
band rejection at fIMAGE= 4.32MHz. The analog I/Q
full-scale output voltage range is selectable at ±410mV
or ±500mV. The output common-mode voltage is selec-
table from 0.9V to 1.4V and the I/Q channel offset is
adjustable. The typical I/Q channel matching is
±0.05dB gain and ±0.16°phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes
and the aux-DAC channels.
The MAX19700 operates on a single +2.7V to +3.3V
analog supply and +1.8V to +3.3V digital I/O supply.
The MAX19700 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package.
Applications
TD-SCDMA Handsets
TD-SCDMA Data Cards
Portable Communication Equipment
FeaturesDual 10-Bit Rx ADC and Dual 10-Bit Tx DACUltra-Low Power
36.3mW at fCLK= 5.12Msps, Fast Mode
19.8mW at fCLK= 5.12Msps, Slow Mode
Low Standby and Shutdown CurrentIntegrated TD-SCDMA Filters with >55dB
Stopband RejectionExcellent Dynamic Performance
SINAD = 54.9dB at fIN= 1.87MHz (Rx ADC)
SFDR = 76.5dBc at fOUT= 620kHz (Tx DAC)Excellent Gain/Phase Match
±0.22°Phase, ±0.02dB Gain (Rx ADC) at
fIN= 1.87MHz at -0.5dBFSThree 12-Bit, 1µs Aux-DACsSingle-Supply OperationMultiplexed Parallel Digital I/OSerial-Interface ControlVersatile Power-Control Circuits
Shutdown, Standby, Idle, Tx-Rx DisableMiniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
19-3549; Rev 0; 2/05
EVALUATION KIT
AVAILABLE
Ordering Information
PART*PIN-PACKAGEPKG CODE
MAX19700ETM48 Thin QFN-EP**T4877-4
MAX19700ETM+48 Thin QFN-EP**T4877-4
*All devices are specified over the -40°C to +85°C operating
range.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram appears at end of data sheet.
DAC3
N.C.
VDD
GND
SCLK
DIN
T/R
SHDN
VDD
N.C.IAP
IAN
GND
CLK
GND
VDD
QAN
GND
EXPOSED PADDLE (GND)QAP
VDD
VDD
REFP1D5
OGNDD9D8D7D3D2D1D0
COMREFINQDPQDNV
GNDIDPIDNV
DAC2DAC1REFN
THIN QFN
MAX19700
TOP VIEW47464544434241403938371415161718192021222324
Pin Configuration
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND, OVDDto OGND..............................-0.3V to +3.4V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, REFP, REFN, REFIN, COM,
DAC1, DAC2, DAC3 to GND.................-0.3V to (VDD+ 0.3V)
D0–D9, DR, T/R, SHDN, SCLK, DIN, CS,
CLK to OGND.....................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above +70°C).......2.1W
Thermal Resistance θJA..................................................38°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP= CREFN= CCOM=
0.33µF. Typical values are at TA= +25°C, unless otherwise noted. CL< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS
Analog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx),
fCLK = 5.12MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx),
fCLK = 5.12MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx),
fCLK = 5.12MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale
Ext2-Rx, Ext3-Rx, and SPI1-Rx modes;
receive ADC operating mode (Rx),
fCLK = 5.12MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale
Ext2-Tx, Ext4-Tx, and SPI4-Tx modes;
transmit DAC operating mode (Tx),
fCLK = 7.5MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale
VDD Supply Current
Ext1-Tx, Ext3-Tx, and SPI2-Tx modes;
transmit DAC operating mode (Tx),
fCLK = 7.5MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale
10.4
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP= CREFN= CCOM=
0.33µF. Typical values are at TA= +25°C, unless otherwise noted. CL< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Ext1-Rx, Ext4-Rx, and SPI3-Rx modes;
receive ADC operating mode (Rx),
fCLK = 7.5MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale
Ext2-Rx, Ext3-Rx, and SPI1-Rx modes;
receive ADC operating mode (Rx),
fCLK = 7.5MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale
Standby mode, CLK = 0 or OVDD;
aux-DACs ON and at midscale2.74
Idle mode, fCLK = 7.5MHz; aux-DACs ON
and at midscale4.76VDD Supply Current
Shutdown mode, CLK = 0 or OVDD0.7µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx modes; receive ADC
operating mode (Rx), fCLK = 7.5MHz,
fIN = 1.87MHz on both channels;
aux-DACs ON and at midscale
1.38mA
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx modes; transmit DAC
operating mode (Tx), fCLK = 7.5MHz, fOUT
= 620kHz; aux-DACs ON and at midscale
Idle mode, fCLK = 7.5MHz; aux-DACs ON
and at midscale10.9
Shutdown mode, CLK = 0 or OVDD0.01
OVDD Supply Current
Standby mode, CLK = 0 or OVDD;
aux-DACs ON and at midscale0.03
Rx ADC DC ACCURACY
Resolution10Bits
Integral NonlinearityINL±0.85LSB
Differential NonlinearityDNL±0.55LSB
Offset ErrorResidual DC offset error±0.5±5%FS
Gain ErrorInclude reference error±1.1±5%FS
DC Gain Matching±0.01±0.25dB
Offset Matching±4.5LSB
Gain Temperature Coefficient±15.7ppm/°C
Offset error (VDD ±5%)±0.2LSBPower-Supply RejectionPSRRGain error (VDD ±5%)±0.04%FS
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP= CREFN= CCOM=
0.33µF. Typical values are at TA= +25°C, unless otherwise noted. CL< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC ANALOG INPUT
Input Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD / 2V
RINSwitched capacitor load720kΩInput ImpedanceCIN5pF
Rx ADC CONVERSION RATE
Maximum Clock FrequencyfCLK(Note 2)7.5MHz
Channel I5Data Latency (Figure 3)Channel Q5.5
Clock
Cycles
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)
fIN = 1.875MHz, fCLK = 7.5MHz53.755Signal-to-Noise RatioSNRfIN = 3.5MHz, fCLK = 7.5MHz54.8dB
fIN = 1.875MHz, fCLK = 7.5MHz53.654.9Signal-to-Noise Plus DistortionSINADfIN = 3.5MHz, fCLK = 7.5MHz54.7dB
fIN = 1.875MHz, fCLK = 7.5MHz6678Spurious-Free Dynamic RangeSFDRfIN = 3.5MHz, fCLK = 7.5MHz70.1dBc
fIN = 1.875MHz, fCLK = 7.5MHz-84Third-Harmonic DistortionHD3fIN = 3.5MHz, fCLK = 7.5MHz-72.1dBc
Intermodulation DistortionIMDf1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-75.6dBc
Third-Order Intermodulation
DistortionIM3f1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-78dBc
fIN = 1.875MHz, fCLK = 7.5MHz-77.9-64Total Harmonic DistortionTHDfIN = 3.5MHz, fCLK = 7.5MHz-71dBc
Aperture Delay3.5ns
Overdrive Recovery Time1.5x full-scale input2ns
Rx ADC INTERCHANNEL CHARACTERISTICS
Crosstalk RejectionfIN X ,Y = 1.875M H z at - 0.5d BFS , fIN X ,Y = 1M H z
at - 0.5d BFS ( N ote 4) -85dB
Amplitude MatchingfIN = 1.875MHz at -0.5dBFS (Note 5)±0.02dB
Phase MatchingfIN = 1.875MHz at -0.5dBFS (Note 5)±0.22D eg r ees
MAX19700
7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), ADC input
amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP= CREFN= CCOM=
0.33µF. Typical values are at TA= +25°C, unless otherwise noted. CL< 5pF on all aux-DAC outputs.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx DAC DC ACCURACY
ResolutionN10Bits
Integral NonlinearityINL±0.45LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 6)±0.26LSB
TA > +25°C-4±1+4
Residual DC OffsetVOS
TA < +25°C-6.5±1+6.5
Full-Scale Gain ErrorIncl ud e r efer ence er r or ( p eak- to- p eak er r or ) -50+50mV
TRANSMIT-PATH DYNAMIC PERFORMANCE
Corner Frequency3dB corner1.11.271.5MHz
Passband RippleDC to 640kHz (Note 6)0.280.5dBP-P
Group Delay Variation in PassbandDC to 640kHz, guaranteed by design50100ns
Error-Vector MagnitudeEVMDC to 700kHz2%
Stopband RejectionfIMAGE = 4.32MHz, fOUT = 800kHz,
fCLK = 5.12MHz55dBc
2MHz20
4MHz46.5
5MHz54.7
10MHz81
Baseband AttenuationSpot relative to
100kHz
20MHz88
DAC Conversion RatefCLK(Note 2)7.5MHz
In-Band Noise DensityNDfOUT = 620kHz, fCLK = 5.12MHz,
offset = 500kHz-121.7dBc/Hz
Third-Order Intermodulation
DistortionIM3f1 = 620kHz, f2 = 640kHz76dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 7.5MHz, fOUT = 620kHz6076.5dBc
Total Harmonic Distortion to
NyquistTHDfCLK = 7.5MHz, fOUT = 620kHz-74.8-59dB
Signal-to-Noise Ratio to NyquistSNRfCLK = 7.5MHz, fOUT = 620kHz57.1dB

Partno	Mfg	Dc	Qty	Available	Descript
MAX19700ETM+T	MAXIM	N/a	74	avai	7.5Msps, Ultra-Low-Power Analog Front-End