MAX195BCPE+ ,16-Bit, 85ksps ADC with 10µA ShutdownFeaturesThe MAX195 is a 16-bit successive-approximation ana- ♦ 16 Bits, No Missing Codeslog-to-digi ..
MAX195BCWE ,16-Bit, 85ksps ADC with 10レA ShutdownGeneral Description ________
MAX195BCWE+ ,16-Bit, 85ksps ADC with 10µA ShutdownMAX19519-0377; Rev 1; 12/9716-Bit, 85ksps ADC w ith 10μA Shutdow n_______________
MAX195BEPE ,16-Bit, 85ksps ADC with 10レA ShutdownFeaturesThe MAX195 is a 16-bit successive-approximation ana- ' 16 Bits, No Missing Codeslog-to-digi ..
MAX195BEPE+ ,16-Bit, 85ksps ADC with 10µA ShutdownApplicationsMAX195BEWE -40°C to +85°C 16 Wide SOPortable InstrumentsMAX195AEDE -40°C to +85°C 16 Ce ..
MAX195BEWE ,16-Bit, 85ksps ADC with 10レA ShutdownMAX19519-0377; Rev 1; 12/9716-Bit, 85ksps ADC with 10µA Shutdown_______________
MAX491CSD ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX148719-0122; Rev 5; 2/96Low-Power, Slew-Rate-LimitedRS-485/RS ..
MAX491CSD ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX491CSD ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversFeaturesThe MAX481, MAX483, MAX485, MAX487–MAX491, and' In µMAX Package: Smallest 8-Pin SOMAX1487 a ..
MAX491CSD+ ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX491CSD+T ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsMAX491, and MAX1487 are not limited, allowing them toMAX3460–MAX3464: +5V, Fail-Safe, 2 ..
MAX491CSD-T ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationscations are obtained using the MAX488–MAX491, whileMAX3080–MAX3089: Fail-Safe, High-Spe ..
MAX195BCPE+-MAX195BCWE+-MAX195BEPE+-MAX195BEWE+
16-Bit, 85ksps ADC with 10µA Shutdown
_______________General DescriptionThe MAX195 is a 16-bit successive-approximation ana-
log-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10μA shutdown mode. Internal calibration circuitry cor-
rects linearity and offset errors to maintain the full rated
performance over the operating temperature range with-
out external adjustments. The capacitive-DAC architec-
ture provides an inherent 85ksps track/hold function.
The MAX195, with an external reference (up to +5V),
offers a unipolar (0V to VREF) or bipolar (-VREFto VREF)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state serial-
data output. The output can be read either during conver-
sion as the bits are determined, or following conversion at
up to 5Mbps using the serial clock (SCLK). The end-of-
conversion (EOC) output can be used to interrupt a
processor, or can be connected directly to the convert
input (CONV) for continuous, full-speed conversions.
The MAX195 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages.
________________________ApplicationsPortable Instruments
Audio
Industrial Controls
Robotics
Multiple Transducer Measurements
Medical Signal Acquisition
Vibrations Analysis
Digital Signal Processing
____________________________Features16 Bits, No Missing Codes90dB SINAD9.4μs Conversion Time10μA (max) Shutdown ModeBuilt-In Track/HoldAC and DC SpecifiedUnipolar (0V to VREF) and Bipolar (-VREFto VREF)
Input RangeThree-State Serial-Data OutputSmall 16-Pin DIP, SO, and Ceramic SB Packages
______________Ordering Information6-Bit, 85ksps ADC with 10μA ShutdownVDDA
VSSA
AGND
AINVDDD
SCLK
CLK
BP/UP/SHDN
TOP VIEW
MAX195
REF
VSSD
RESET
CONVCS
EOC
DGND
DOUT
DIP/Wide SO/Ceramic SBMAX195
AIN
REF
CONV
SCLK
CLK
BP/UP/SHDN
RESET
VSSD
DGND
VDDD
VDDA
AGND
VSSA
DOUT
EOC
SAR
CONTROL LOGIC
COMPARATORCALIBRATION
DACs
THREE-STATE BUFFERMAIN DACΣ
________________Functional Diagram
__________________Pin Configuration19-0377; Rev 1; 12/97
PARTMAX195BCPE
MAX195BCWE
MAX195ACDE0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGEPIN-PACKAGE16 Plastic DIP
16 Wide SO
16 Ceramic SB
MAX195BC/D0°C to +70°CDice*
MAX195BEPE-40°C to +85°C16 Plastic DIP
MAX195BEWE-40°C to +85°C16 Wide SO
MAX195AEDE-40°C to +85°C16 Ceramic SB
MAX195AMDE-55°C to +125°C16 Ceramic SB**
MAX195BMDE-55°C to +125°C16 Ceramic SB**
EVALUATION KIT
AVAILABLEDice are specified at TA= +25°C, DC parameters only.Contact factory for availability and processing to MIL-STD-883.
6-Bit, 85ksps ADC with 10μA ShutdownABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDD to DGND.....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND.........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA..........................................±0.3V
AIN, REF....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C)............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX195_C_E........................................................0°C to +70°C
MAX195_E_E.....................................................-40°C to +85°C
MAX195_MDE..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX195A
16 (tCLK)= +25°C= +25°C
Unipolar
VREF= 4.75V
MAX195A
MAX195B
MAX195A, VREF= 4.75V
VSSA = -5.25V to -4.75V, VREF= 4.75V
MAX195B, VREF= 4.75V
VDDA = 4.75V to 5.25V, VREF= 4.75V
CONDITIONSMHz1.7fCLKClock Frequency
(Notes 3, 4)9.4tCONVConversion Time-90Peak Spurious Noise (Note 2)-97-90THDTotal Harmonic Distortion (up to
the 5th harmonic) (Note 2)0VREFInput Range65
Power-Supply Rejection
Ratio (VDDA and VSSA only)
Bits16RESResolution
ppm/°C0.1Full-Scale Tempco
%FSRUnipolar Full-Scale Error±0.0075
Unipolar/Bipolar Offset Tempcoppm/°C0.4
±0.003%FSR±0.004INLIntegral NonlinearityLSB±4Unipolar/Bipolar Offset Error
UNITSMINTYPMAXSYMBOLPARAMETERUnipolarpF250Input Capacitance= +25°CdB8790SINADSignal-to-Noise plus Distortion
Ratio (Note 2)
MHz5fSCLKSerial Clock Frequency
Bipolar
Bipolar125
-VREFVREF
VREF= 4.75V%FSRBipolar Full-Scale Error±0.018
MAX195BLSB±2DNL
ACCURACY (Note 1)
ANALOG INPUT
DYNAMIC PERFORMANCE (fs= 85kHz, bipolar range AIN = -5V to +5V, 1kHz) (Note 1)
Differential Nonlinearity
6-Bit, 85ksps ADC with 10μA ShutdownELECTRICAL CHARACTERISTICS (continued)(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
BP/UP/SHDN= open
VDDD = 5.25V
BP/UP/SHDN= open
BP/UP/SHDN= 0V
BP/UP/SHDN= VDDD
Digital inputs = 0 or 5V
VDDD = 4.75V
CONDITIONS-100+100BP/UP/SHDNMax Allowed
Leakage, Mid Input2.75VFLTBP/UP/SHDNVoltage,
Floating1.5VDDD - 1.5VIMBP/UP/SHDN
Mid Input Voltage-4.0IILBP/UP/SHDN
Input Current, Low4.0IIHBP/UP/SHDN
Input Current, High0.5VILBP/UP/SHDN
Input Low Voltage2.4VIHCLK, CS, CONV, RESET, SCLK
Input High VoltageVDDD - 0.5VIHBP/UP/SHDN
Input High Voltage±10CLK, CS, CONV, RESET, SCLK
Input Current0.8VILCLK, CS, CONV, RESET, SCLK
Input Low Voltage10CLK, CS, CONV, RESET, SCLK
Input Capacitance (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETEROutput Low VoltageVOLVDDD = 4.75V, ISINK= 1.6mA0.4V
Output High VoltageVOHVDDD = 4.75V, ISOURCE= 1mAVDDD - 0.5V
DOUT Leakage CurrentILKGDOUT = 0 or 5V±10μA
Output Capacitance (Note 2)10pF
VDDD4.755.25V
VSSD-5.25-4.75V
VDDABy supply-rejection test4.755.25V
VSSABy supply-rejection test-5.25-4.75V
VDDD Supply CurrentIDDDVDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V2.54mA
VSSD Supply CurrentISSDVDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V0.92mA
VDDA Supply CurrentIDDAVDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V3.85mA
VSSA Supply CurrentISSAVDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V3.85mA
DIGITAL INPUTS (CLK, CS, CONV, RESET, SCLK, BP/UP/SHDN)
DIGITAL OUTPUTS (DOUT, EOC)
POWER REQUIREMENTS
6-Bit, 85ksps ADC with 10μA ShutdownVDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN= 0V
VDDD = VDDA = 5.25V, VSSD = VSSA = -5.25V,
BP/UP/SHDN= 0V
CONDITIONS80Power Dissipation0.15ISSAVSSA Shutdown Supply Current0.15IDDAVDDA Shutdown Supply Current1.65IDDDVDDD Shutdown Supply Current
(Note 5)0.15ISSDVSSD Shutdown Supply Current
UNITSMINTYPMAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
TIMING CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
Note 1:Accuracy and dynamic performance tests performed after calibration.
Note 2:Guaranteed by design, not tested.
Note 3:Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 4:See External Clocksection.
Note 5:Measured in shutdown mode with CLK and SCLK low.
POWER REQUIREMENTS (cont.)
PARAMETERSYMBOLCONDITIONSTA= +25°C
TYP= 0°C to
+70°C
MINMAX= -40°C to
+85°C
MINMAX= -55°C to
+125°C
MINMAX
UNITSCONVPulse WidthtCW203035ns
CONVto CLK Falling
Synchronization (Note 2)tCC1101010ns
CONVto CLK Rising
Synchronization (Note 2)tCC24040ns
Data Access TimetDVCL= 50pF8080
Bus Relinquish TimetDHCL= 10pF404040ns
CLK to EOCHightCEHCL= 50pF300300350ns
CLK to EOCLowtCELCL= 50pF300300350ns
CLK to DOUT ValidtCDCL= 50pF100350100375100400ns
SCLK to DOUT ValidtSDCL= 50pF201402016020160nsto SCLK Setup TimetCSS757575nsto SCLK Hold TimetCSH-10-10-10ns
Acquisition TimetAQ2.42.42.4μs
Calibration TimetCAL14,000 x tCLK8.28.28.2ms
RESETto CLK Setup TimetRCS-40-40-40ns
RESETto CLK Hold TimetRCH120120120
Start-Up Time (Note 6)tSUExiting
shutdown50
Note 6:Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
_______________Detailed DescriptionThe MAX195 uses a successive-approximation register
(SAR) to convert an analog input to a 16-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK at the SCLK rate (up to 5Mbps).
The MAX195 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (μPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX195 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
The DAC consists of an array of 16 capacitors with
binary weighted values plus one “dummy LSB” capaci-
tor (Figure 1). During input acquisition in unipolar
mode, the array’s common terminal is connected to
AGND and all free terminals are connected to the input
signal (AIN). After acquisition, the common terminal is
disconnected from AGND and the free terminals are
disconnected from AIN, trapping a charge proportional
to the input voltage on the capacitor array.
The free terminal of the MSB (largest) capacitor is con-
nected to the reference (REF), which pulls the common
terminal (connected to the comparator) positive.
Simultaneously, the free terminals of all other capaci-
tors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
near VREF, connecting the MSB’s free terminal to REF
only pulls the comparator input slightly positive.
However, connecting the remaining capacitor’s free ter-
minals to ground drives the comparator input well
below ground, so the comparator input is negative, the
comparator output is low, and the MSB is set high. If
the analog input is near ground, the comparator output
is high and the MSB is low.
Following this, the next largest capacitor is disconnect-
ed from AGND and connected to REF, and the com-
parator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of VREFto -VREF.
6-Bit, 85ksps ADC with 10μA Shutdown
______________________________________________________________Pin Description
PINNAMEFUNCTIONBP/UP/SHDNBipolar/Unipolar/Shutdown Input. Three-state input selects bipolar or unipolar input range, or shutdown.
0V = shutdown, +5V = unipolar, floating = bipolar.CLKConversion Clock InputSCLKSerial Clock Input is used to shift data out between conversions. May be asynchronous to CLK.VDDD+5V Digital Power SupplyDOUTSerial Data Output, MSB firstDGNDDigital GroundEOCEnd-of-Conversion/Calibration Output—normally low. Rises one clock cycle after the beginning of conversion
or calibration and falls one clock cycle after the end of either. May be used as an output framing signal.CSChip-Select Input—active low. Enables the serial interface and the three-state data output (DOUT).CONVConvert-Start Input—active low. Conversion begins on the falling edge after CONVgoes low if the input
signal has been acquired; otherwise, on the falling clock edge after acquisition.RESETReset Input. Pulling RESETlow places the ADC in an inactive state. Rising edge resets control logic and
begins calibration.VSSD-5V Digital Power SupplyREFReference Input, 0 to 5VAINAnalog Input, 0 to VREFunipolar or ±VREFbipolar rangeAGNDAnalog GroundVSSA-5V Analog Power SupplyVDDA+5V Analog Power Supply
CalibrationIn an ideal DAC, each of the capacitors associated with
the data bits would be exactly twice the value of the
next smaller capacitor. In practice, this results in a
range of values too wide to be realized in an economi-
cally feasible size. The capacitor array actually consists
of two arrays, which are capacitively coupled to reduce
the LSB array’s effective value. The capacitors in the
MSB array are production trimmed to reduce errors.
Small variations in the LSB capacitors contribute
insignificant errors to the 16-bit result.
Unfortunately, trimming alone does not yield 16-bit per-
formance or compensate for changes in performance
due to changes in temperature, supply voltage, and
other parameters. For this reason, the MAX195 includes
a calibration DAC for each capacitor in the MSB array.
These DACs are capacitively coupled to the main DAC
output and offset the main DAC’s output according to
the value on their digital inputs. During calibration, the
correct digital code to compensate for the error in each
MSB capacitor is determined and stored. Thereafter,
the stored code is input to the appropriate calibration
DAC whenever the corresponding bit in the main DAC
is high, compensating for errors in the associated
capacitor.
The MAX195 calibrates automatically on power-up. To
reduce the effects of noise, each calibration experiment
is performed many times and the results are averaged.
Calibration requires about 14,000 clock cycles, or
8.2ms at the highest clock (CLK) speed (1.7MHz). In
addition to the power-up calibration, bringing RESET
low halts MAX195 operation, and bringing it high again
initiates a calibration (Figure 2).
6-Bit, 85ksps ADC with 10μA ShutdownMSB
AIN
REF
AGND
DUMMYLSB
32,768C16,384C4C 2CCC
EOC
CLK
RESET
CALIBRATION
BEGINS
CALIBRATION
ENDS
MAX195
OPERATION HALTS
tCAL
tRCS
tRCH
Figure 1. Capacitor DAC Functional Diagram
Figure 2. Initiating Calibration
If the power supplies do not settle within the MAX195’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrat-
ed. If so, recalibrate the converter (pulse RESETlow)
before use. For best DC accuracy, calibrate the
MAX195 any time there is a significant change in sup-
ply voltages, temperature, reference voltage, or clock
characteristics (see External Clocksection) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parame-
ters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to main-
tain accuracy or to recalibrate if the MAX195 has been
held in shutdown for long periods. However, recalibra-
tion is recommended if it is likely that ambient tempera-
ture or supply voltages have significantly changed
since the previous calibration.
Digital InterfaceThe digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDNis a three-level input. Leave it floating to
configure the MAX195’s analog input in bipolar mode
(AIN = -VREFto VREF) or connect it high for a unipolar
input (AIN = 0V to VREF). Bringing BP/UP/SHDNlow
places the MAX195 in its 10μA shutdown mode.
A logic low on RESEThalts MAX195 operation. The ris-
ing edge of RESETinitiates calibration as described in
the Calibrationsection above.
Begin a conversion by bringing CONVlow. After con-
version begins, additional convert start pulses are
ignored. The convert signal must be synchronized with
CLK. The falling edge of CONVmust occur during the
period shown in Figures 3 and 4. When CLK is not
directly controlled by your processor, two methods of
ensuring synchronization are to drive CONVfrom EOC
(continuous conversions) or to gate the conversion-start
signal with the conversion clock so that CONVcan go
low only while CLK is low (Figure 5). Ensure that the
maximum propagation delay through the gate is less
than 40ns.
The MAX195 automatically ensures four CLK periods
for track/hold acquisition. If, when CONVis asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOCwill go high on the
following falling CLK edge (Figure 3). If, when convert
is asserted, less than three clock cycles have passed,
a conversion will begin on the fourth falling clock edge
6-Bit, 85ksps ADC with 10μA ShutdownTRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
tAQ THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
tCEL
tCW
tCEH
tCC2
tCC1
EOC
CONV
Figure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
after the end of the previous conversion and EOCwill
go high on the following CLK falling edge (Figure 4).
External ClockThe conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the min-
imum high and low times exceed 150ns. The minimum
clock rate for accurate conversion is 125Hz for temper-
atures up to +70°C or 1kHz at +125°C due to leakage
of the sampling capacitor array. In addition, CLK
should not remain high longer than 50ms at tempera-
tures up to +70°C or 500μs at +125°C. If CLK is held
high longer than this, RESETmust be pulsed low to initi-
ate a recalibration because it is possible that state
information stored in internal dynamic memory may be
lost. The MAX195’s clock can be stopped indefinitely if
it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output DataThe conversion result, clocked out MSB first, is avail-
able on DOUT only when CSis held low. Otherwise,
DOUT is in a high-impedance state. There are two ways
to read the data on DOUT. To read the data bits as they
are determined (at the CLK clock rate), hold CSlow
during the conversion. To read results between conver-
sions, hold CSlow and clock SCLK at up to 5MHz.
If you read the serial data bits as they are determined,
EOC frames the data bits (Figure 6). Conversion begins
with the first falling CLK edge, after CONVgoes low
and the input signal has been acquired. Data bits are
shifted out of DOUT on subsequent falling CLK edges.
Clock data in on CLK’s rising edge or, if the clock
speed is greater than 1MHz, on the following falling
edge of CLK to meet the maximum CLK-to-DOUT tim-
ing specification. See the Operating Modes and
SPI™/QSPI™ Interfacessection for additional informa-
tion. Reading the serial data during the conversion
results in the maximum conversion throughput,
because a new conversion can begin immediately after
the input acquisition period following the previous con-
version.
6-Bit, 85ksps ADC with 10μA ShutdownTRACK/HOLD
CLK
CONVERSION
BEGINS
CONVERSION
ENDS
tAQ
* THE FALLING EDGE OF CONV MUST OCCUR IN THIS REGION
tCEL
tCW
tCEH
tCC2
tCC1
EOC
CONV
Figure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
If you read the data bits between conversions, you can:
1) count CLK cycles until the end of the conversion, or
2) poll EOCto determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSBconversion result appears at DOUT
after CSgoes low, but beforethe first SCLK pulse.
Each subsequent SCLK pulse shifts out the next con-
version bit. The 15th SCLK pulse shifts out the LSB.
Additional clock pulses shift out zeros.
6-Bit, 85ksps ADC with 10μA ShutdownCLK
START
CONV
MAX195
CONV
START
CLK
SEE DIGITAL INTERFACE SECTION
CONV
CLK
(CASE 1)
CLK
(CASE 2)
EOC
tDVtCD
tCW
tCEH
CASE 1: CLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: CLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
NOTE: ARROWS ON CLK TRANSITIONS INDICATE LATCHING EDGE
tCEL
DOUT
tDH
B15
CONVERSION
BEGINSCONVERSION
ENDS
MSBLSB
B14B13B12B2B1B0B15B15 FROM PREVIOUS
CONVERSION
Figure 5. Gating CONVto Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
Data is clocked out on SCLK’s falling edge. Clock
data in on SCLK’s rising edge or, for clock speeds
above 2.5MHz, on the following falling edge to meet
the maximum SCLK-to-DOUT timing specification
(Figure 7). The maximum SCLK speed is 5MHz. See
the Operating Modes and SPI/QSPI Interfacessection
for additional information. When the conversion clock
is near its maximum (1.7MHz), reading the data after
each conversion (during the acquisition time) results
in lower throughput (about 70ksps max) than reading
the data during conversions, because it takes longer
than the minimum input acquisition time (four cycles
at 1.7MHz) to clock 16 data bits at 5Mbps. After the
data has been clocked in, leave some time (about
1μs) for any coupled noise on AIN to settle before
beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX195 in its simplest
operational configuration.
6-Bit, 85ksps ADC with 10μA ShutdownEOC
SCLK
(CASE 1)
SCLK
(CASE 2)
CASE 1: SCLK IDLES LOW, DATA LATCHED ON RISING EDGE (CPOL = 0, CPHA = 0)
CASE 2: SCLK IDLES LOW, DATA LATCHED ON FALLING EDGE (CPOL = 0, CPHA = 1)
CASE 3: SCLK IDLES HIGH, DATA LATCHED ON FALLING EDGE (CPOL = 1, CPHA = 0)
NOTE: ARROWS ON SCLK TRANSITIONS INDICATE LATCHING EDGE
DOUT
SCLK
(CASE 3)
tCONV
tDHtSDtDV
MSBLSB
B15B14B13B12B3B2B1B0B11
tCSS
tCSH
MAX195
10μF
BP/UP/
SHDN
CLK
SCLK
VDDD
DOUT
DGND
REFERENCE
(0V TO VDDA)
ANALOG
INPUT
-5V
EOC
VDDA
VSSA
AGND
AIN
CONVERSION
CLOCK
+5V
REF
VSSD
RESET
CONV
0.1μF10μF0.1μF
Figure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
Figure 8. MAX195 in the Simplest Operating Configuration
6-Bit, 85ksps ADC with 10μA ShutdownBRIDGE
INSTRUMENTATION
AMPLIFIER
+5V
AINMAX195
VDDA
AGND
47μF
LOW ESR
0.1μF
CERAMIC
REF
COMPANYCAPACITORFACTORY FAX [COUNTRY CODE]USA TELEPHONESprague595D series,
592D series1-603-224-1430603-224-1961
AVXTPS series1-207-283-1941800-282-4975
SanyoOS-CON series,
MVGX series81-7-2070-1174619-661-6835
NichiconPL series1-708-843-2798708-843-7500
Figure 9. Ratiometric Measurement Without an Accurate Reference
Table 1. Low-ESR Capacitor Suppliers
__________Applications Information
ReferenceThe MAX195 reference voltage range is 0V to VDDA.
When choosing the reference voltage, the MAX195’s
equivalent input noise (40μVRMSin unipolar mode,
80μVRMSin bipolar mode) should be considered. Also, if
VREFexceeds VDDA, errors will occur due to the internal
protection diodes that will begin to conduct, so use cau-
tion when using a reference near VDDA (unless VREF
and VDDA are virtually identical). VREFmust never
exceed its absolute maximum rating (VDDA + 0.3V).
The MAX195 needs a good reference to achieve its
rated performance. The most important requirement is
that the reference must present a low impedance to the
REF input. This is often achieved by buffering the refer-
ence through an op amp and bypassing the REF input
with a large (1μF to 47μF), low-ESR capacitor in parallel
with a 0.1μF ceramic capacitor. Low-ESR capacitors
are available from the manufacturers listed in Table 1.
The reference must drive the main conversion DAC
capacitors as well as the capacitors in the calibration
DACs, all of which may be switching between GND and
REF at the conversion clock frequency. The total
capacitive load presented can exceed 1000pF and,
unlike the analog input (AIN), REF is sampled continu-
ously throughout the conversion.
The first step in choosing a reference circuit is to
decide what kind of performance is required. This often
suggests compromises made in the interests of cost
and size. It is possible that a system may not require an
accurate reference at all. If a system makes a ratiomet-
ric measurement such as Figure 9’s bridge circuit, any
relatively noise-free voltage that presents a low imped-
ance at the REF input will serve as a reference. The
+5V analog supply suffices if you use a large, low-
impedance bypass capacitor to keep REF stable dur-
ing switching of the capacitor arrays. Do not place a
resistance between the +5V supply and the bypass
capacitor, because it will cause linearity errors due to
the dynamic REF input current, which typically ranges
from 300μA to 400μA.
Figure 10 shows a more typical scheme that provides
good AC accuracy. The MAX874’s initial accuracy can
be improved by trimming, but the drift is too great to
provide good stability over temperature. The MAX427
buffer provides the necessary drive current to stabilize
the REF input quickly after capacitance changes.
The reference inaccuracies contribute additional full-
scale error. A reference with less than 1⁄216total error
(15 parts per million) over the operating temperature
range is required to limit the additional error to less
than 1LSB. The MAX6241 achieves a drift specification
of 1ppm/°C (typ). This allows reasonable temperaturehanges with less than 1LSB error. While the
MAX6241’s initial-accuracy specification (0.02%)
results in an offset error of about ±14LSB, the reference
voltage can be trimmed or the offset can be corrected
in software if absolute DC accuracy is essential. Figure
11’s circuit provides outstanding temperature stability
and also provides excellent DC accuracy if the initial
error is corrected.
6-Bit, 85ksps ADC with 10μA ShutdownMAX195
MAX427
AGNDVSSA
VDDA
MAX874
GND
VIN
COMP
VOUT
4.096V
+15V
-15V
47μF
LOW ESR0.1μF
0.1μF
0.1μF
0.1μF
1000pF
0.1μF
0.1μF
10Ω
REF
1N914
1N914
10Ω
-5V
+5V1214
2.2μF
VIN ≥ 8V
1μF
10k2.2μF0.1μF
MAX6241
OUTREF
TRIMNR
GNDAGND
MAX195
Figure 10. Typical Reference Circuit for AC Accuracy
Figure 11. High-Accuracy Reference
6-Bit, 85ksps ADC with 10μA ShutdownINPUT
SIGNAL1N914
DIODE
CLAMPS
+5V
AIN
MAX195
-5V
VSSA
VDDA+15V
-15V
10Ω
Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
REF and AIN Input ProtectionThe REF and AIN signals should not exceed the
MAX195 supply rails. If this can occur, diode clamp the
signal to the supply rails. Use silicon diodes and a 10Ω
current-limiting resistor (Figures 10 and 12) or Schottky
diodes without the resistor.
When using the current-limiting resistor, place the resis-
tor between the appropriate input (AIN or REF) and any
bypass capacitor. While this results in AC transients at
the input due to dynamic input currents, the transients
settle quickly and do not affect conversion results.
Improperly placing the bypass capacitor directly at the
input forms an RC lowpass filter with the current-limiting
resistor, which averages the dynamic input current and
causes linearity errors.
Analog InputThe MAX195 uses a capacitive DAC that provides an
inherent track/hold function. The input impedance is
typically 30Ωin series with 250pF in unipolar mode and
50Ωin series with 125pF in bipolar mode.
Input RangeThe analog input range can be either unipolar (0V to
VREF) or bipolar (-VREFto VREF), depending on the
state of the BP/UP/SHDNpin (see Digital Interfacesec-
tion). The reference range is 0V to VDDA. When choos-
ing the reference voltage, the equivalent MAX195 input
noise (40μVRMSin unipolar mode, 80μVRMSin bipolar
mode) should be considered.
Input Acquisition and SettlingFour conversion-clock periods are allocated for acquir-
ing the input signal. At the highest conversion rate, four
clock periods is 2.4μs. If more than three clock cycles
have occurred since the end of the previous conver-
sion, conversion begins on the next falling clock edge
after CONVgoes low. Otherwise, bringing CONVlow
begins a conversion on the fourth falling clock edge
after the previous conversion. This scheme ensures the
minimum input acquisition time is four clock periods.
Most applications require an input buffer amplifier. If
the input signal is multiplexed, the input channel should
be switched near the beginning of a conversion, rather
than near the end of or after a conversion (Figure 13).
This allows time for the input buffer amplifier to respond
to a large step change in input signal. The input amplifi-
er must have a high enough slew rate to complete the
required output voltage change beforethe beginning of
the acquisition time.
At the beginning of acquisition, the capacitive DAC is
connected to the amplifier output, causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits before the end of the
acquisition time. If the frequency of interest is low, AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage (Figure 14). However, for AC use, AIN must be
driven by a wideband buffer (at least 10MHz), which
must be stable with the DAC’s capacitive load (in paral-
lel with any AIN bypass capacitor used) and also must
settle quickly (Figure 15 or 16).
6-Bit, 85ksps ADC with 10μA ShutdownMAX400IN
+15V
-15V
1.0μF0.1μF
0.1μF1000pF
100Ω
AIN
1N914
1N914
+5V
-5V
10Ω
Figure 14. MAX400 Drives AIN for Low-Frequency Use
EOC
CLK
CHANGE MUX INPUT HERE
CONVERSION
IN1A0A1
IN2
IN3
IN4OUT
ACQUISITION
MAX1954-TO-1
MUX
EOC
AIN
Figure 13. Change multiplexer input near beginning of conversion to allow time for slewing and settling.
