MAX19507ETM+ ,Dual-Channel, 8-Bit, 130Msps ADCapplications. The♦ Selectable Data Bus (Dual CMOS or Singletypical signal-to-noise ratio (SNR) perf ..
MAX19507ETM+ ,Dual-Channel, 8-Bit, 130Msps ADCApplications*EP = Exposed pad.IF and Baseband Communications, IncludingCellular Base Stations and P ..
MAX19517ETM+ ,Dual-Channel, 10-Bit, 130Msps ADCApplications*EP = Exposed pad.IF and Baseband Communications, IncludingCellular Base Stations and P ..
MAX19517ETM+ ,Dual-Channel, 10-Bit, 130Msps ADCapplications. The♦ Selectable Data Bus (Dual CMOS or Singletypical signal-to-noise ratio (SNR) perf ..
MAX1951ESA ,PLASTIC ENCAPSULATED DEVICESTable of Contents I. ........Device Description V. ........Quality Assurance Information II ..
MAX1951ESA+ ,1MHz, All-Ceramic, 2.6V to 5.5V Input, 2A PWM Step-Down DC-to-DC Regulatorsapplications. The MAX1951total output error is less than 1% over load, line, and ♦ 1% Output Accura ..
MAX490ECSA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversGeneral Description ________
MAX490ECSA+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 Transceiversapplications that are not ESD sensitive see the pin-and function-compatible MAX481, MAX483, MAX485, ..
MAX490ECSA+T ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplicationsMAX481EESA -40°C to +85°C 8 SOIndustrial-Control Local Area Networks MAX483ECPA 0°C to ..
MAX490EEPA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversMAX481E/MAX483E/MAX485E/MAX487E–MAX491E/MAX1487E19-0410; Rev 3; 7/96±15kV ESD-Protected, Slew-Rate- ..
MAX490EEPA+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX490EESA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX19507ETM+
Dual-Channel, 8-Bit, 130Msps ADC
General DescriptionThe MAX19507 dual-channel, analog-to-digital converter
(ADC) provides 8-bit resolution and a maximum sample
rate of 130Msps.
The MAX19507 analog input accepts a wide 0.4V to
1.4V input common-mode voltage range, allowing DC-
coupled inputs for a wide range of RF, IF, and base-
band front-end components. The MAX19507 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and high-
intermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
49.8dBFS and typical spurious-free dynamic range
(SFDR) is 69dBc at fIN= 70MHz and fCLK= 130MHz.
The MAX19507 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regula-
tor allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 74mW per chan-
nel at VAVDD= 1.8V. In addition to low operating
power, the MAX19507 consumes only 1mW in power-
down mode and 21mW in standby mode.
Various adjustments and feature selections are avail-
able through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three inputs available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible out-
put data bus that can also be configured as a single
multiplexed parallel CMOS bus.
The MAX19507 is available in a small 7mm x 7mm, 48-
pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.
Refer to the MAX19515, MAX19516, and MAX19517
data sheets for pin- and feature-compatible 10-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19505 and MAX19506 data sheets for
pin- and feature-compatible 8-bit, 65Msps and 100Msps
versions, respectively.
ApplicationsIF and Baseband Communications, IncludingCellular Base Stations and Point-to-Point
Microwave Receivers
Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data
Acquisition
FeaturesVery-Low-Power Operation (74mW/Channel at
130Msps)1.8V or 2.5V to 3.3V Analog SupplyExcellent Dynamic Performance
49.8dBFS SNR at 70MHz
69dBc SFDR at 70MHzUser-Programmable Adjustments and Feature
Selection through an SPI™InterfaceSelectable Data Bus (Dual CMOS or Single
Multiplexed CMOS)DCLK Output and Programmable Data Output
Timing Simplifies High-Speed Digital InterfaceVery Wide Input Common-Mode Voltage Range
(0.4V to 1.4V)Very High Analog Input Bandwidth (> 850MHz)Single-Ended or Differential Analog InputsSingle-Ended or Differential Clock InputDivide-by-One (DIV1), Divide-by-Two (DIV2), and
Divide-by-Four (DIV4) Clock ModesTwo’s Complement, Gray Code, and Offset Binary
Output Data FormatOut-of-Range Indicator (DOR)CMOS Output Internal Termination Options
(Programmable)Reversible Bit Order (Programmable)Data Output Test PatternsSmall 7mm x 7mm, 48-Pin Thin QFN Package with
Exposed Pad
Dual-Channel, 8-Bit, 130Msps ADC
Ordering Information19-4311; Rev 1; 9/10
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX19507ETM+-40°C to +85°C48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN
to GND..........-0.3V to the lower of (VAVDD+ 0.3V) and +3.6V
DCLKA, DCLKB, D7A–D0A, D7B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (VOVDD+ 0.3V) and +3.6V
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C
above +70°C).............................................................3200mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution8Bits
Integral NonlinearityINLfIN = 3MHz-0.3±0.1+0.3LSB
Differential NonlinearityDNLfIN = 3MHz-0.3±0.1+0.3LSB
Offset ErrorOEInternal reference-0.4±0.1+0.4%FS
Gain ErrorGEExternal reference = 1.25V-1.5±0.3+1.5%FS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)Differential Input-Voltage RangeVDIFFDifferential or single-ended inputs1.5VP-P
Common-Mode Input-Voltage
RangeVCM(Note 2)0.41.4V
Fixed resistance, common mode, and
differential mode> 100
Input ResistanceRIN
Differential input resistance, common mode
connected to inputs4
Input CurrentIINSwitched capacitance common-mode input
current, each input74µA
CPARFixed capacitance to ground, each input0.7Input CapacitanceCSAMPLESwitched capacitance, each input1.2pF
CONVERSION RATEMaximum Clock FrequencyfCLK130MHz
Minimum Clock FrequencyfCLK65MHz
Data LatencyFigures 9, 109Cycles
Dual-Channel, 8-Bit, 130Msps ADC
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC PERFORMANCESmall-Signal Noise FloorSSNFfIN = 70MHz, < -35dBFS-49.8dBFS
fIN = 3MHz49.8
fIN = 70MHz49.049.8Signal-to-Noise RatioSNR
fIN = 175MHz49.8
dBFS
fIN = 3MHz49.3
fIN = 70MHz48.549.3Signal-to-Noise Plus Distortion
RatioSINAD
fIN = 175MHz49.3
fIN = 3MHz77.0
fIN = 70MHz65.077.0Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)SFDR1
fIN = 175MHz77.0
dBc
fIN = 3MHz69.0
fIN = 70MHz64.069.0Spurious-Free Dynamic Range
(4th and Higher Harmonics)SFDR2
fIN = 175MHz69.0
dBc
fIN = 3MHz-78.0
fIN = 70MHz-78.0-65.0Second HarmonicHD2
fIN = 175MHz-78.0
dBc
fIN = 3MHz-82.0
fIN = 70MHz-82.0-65.0Third HarmonicHD3
fIN = 175MHz-80.0
dBc
fIN = 3MHz-72.0
fIN = 70MHz-72.0-63.0Total Harmonic DistortionTHD
fIN = 175MHz-72.0
dBc
fIN = 70MHz ±1.5MHz, -7dBFS-80Third-Order IntermodulationIM3fIN = 175MHz ±2.5MHz, -7dBFS-75dBc
Full-Power BandwidthFPBWRSOURCE = 50Ω differential, -3dB rolloff850MHz
Aperture DelaytAD850ps
Aperture JittertAJ0.3psRMS
Overdrive Recovery Time±10% beyond full scale1Cycles
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERCHANNEL CHARACTERISTICSfINA or fINB = 70MHz at -1dBFS95CrosstalkfINA or fINB = 175MHz at -1dBFS85dBc
Gain MatchfIN = 70MHz±0.05dB
Offset MatchfIN = 70MHz±0.2%FSR
Phase MatchfIN = 70MHz±0.5D eg r ees
ANALOG OUTPUTS (CMA, CMB)CMA, CMB Output VoltageVCOMDefault programmable setting0.850.90.95V
INTERNAL REFERENCEREFIO Output VoltageVREFOUT1.231.251.27V
REFIO Temperature CoefficientTCREF< ±60ppm/°C
EXTERNAL REFERENCEREFIO Input-Voltage RangeVREFIN1.25 +5/
-10%V
REFIO Input ResistanceRREFIN10
±20%kΩ
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODEDifferential Clock Input Voltage0.4 to 2.0VP-P
Self-biased1.2Differential Input Common-Mode
VoltageDC-coupled clock signal1.0 to 1.4V
Differential, default10kΩ
Differential, programmable internal
termination selected100ΩInput ResistanceRCLK
Common mode9kΩ
Input CapacitanceCCLKTo ground, each input3pF
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (VCLK- < 0.1V)Single-Ended Mode Selection
Threshold (VCLK-)0.1V
Allowable Logic Swing (VCLK+)0 - VAVDDV
Single-Ended Clock Input High
Threshold (VCLK+)1.5V
Single-Ended Clock Input Low
Threshold (VCLK+)0.3V
VCLK+ = VAVDD = 1.8V or 3.3V+0.5Input Leakage (CLK+)VCLK+ = 0V-0.5µA
Input Leakage (CLK-)VCLK- = 0V-150-50µA
Input Capacitance (CLK+)3pF
Dual-Channel, 8-Bit, 130Msps ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CLOCK INPUT (SYNC)Allowable Logic Swing0 - VAVDDV
Sync Clock Input High Threshold1.5V
Sync Clock Input Low Threshold0.3V
VSYNC = VAVDD = 1.8V or 3.3V+0.5Input LeakageVSYNC = 0V-0.5µA
Input Capacitance4.5pF
DIGITAL INPUTS (SHDN, SPEN)Allowable Logic Swing0 - VAVDDV
Input High Threshold1.5V
Input Low Threshold0.3V
VSHDN/VSPEN = VAVDD = 1.8V or 3.3V+0.5Input LeakageVSHDN/VSPEN = 0V-0.5µA
Input CapacitanceCDIN3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODEAllowable Logic Swing0 - VAVDDV
Input High Threshold1.5V
Input Low Threshold0.3V
VSCLK/VSDIN/VCS = VAVDD = 1.8V or 3.3V+0.5Input LeakageVSCLK/VSDIN/VCS = 0V-0.5µA
Input CapacitanceCDIN3pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = VAVDD)—PARALLEL CONTROL MODE (Figure 5)VSCLK/VSDIN/VCS = VAVDD = 1.8V71217Input Pullup Current
VSCLK/VSDIN/VCS = VAVDD = 3.3V162126
VSCLK/VSDIN/VCS = 0V, VAVDD = 1.8V-65-50-35Input Pulldown CurrentVSCLK/VSDIN/VCS = 0V, VAVDD = 3.3V-105-90-75µA
VAVDD = 1.8V1.351.451.55Open-Circuit VoltageVOCVAVDD = 3.3V2.582.682.78V
DIGITAL OUTPUTS (CMOS MODE 75Ω, D0–D7 (A and B Channel), DCLKA, DCLKB, DORA, DORB)Output-Voltage LowVOLISINK = 200µA0.2V
Output-Voltage HighVOHISOURCE = 200µAVOVDD
- 0.2V
VOVDD applied+0.5Three-State Leakage CurrentILEAKGND applied-0.5µA
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER-MANAGEMENT CHARACTERISTICSWake-Up Time from ShutdowntWAKEInternal reference, CREFIO = 0.1µF (10τ)5ms
Wake-Up Time from StandbytWAKEInternal reference15µs
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)SCLK PeriodtSCLK50ns
SCLK to CS Setup TimetCSS10ns
SCLK to CS Hold TimetCSH10ns
SDIN to SCLK Setup TimetSDSSerial-data write10ns
SDIN to SCLK Hold TimetSDHSerial-data write0ns
SCLK to SDIN Output Data DelaytSDDSerial-data read10ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9), (Default Timing see Table 5)Clock Pulse-Width HightCH3.85ns
Clock Pulse-Width LowtCL3.85ns
Clock Duty CycletCH/tCLK30 to 70%
CL = 10pF, VOVDD = 1.8V (Note 2)10.312.614.9Data Delay After Rising Edge of
CLK+tDDCL = 10pF, VOVDD = 3.3V11.4ns
Data to DCLK Setup TimetSETUPCL = 10pF, VOVDD = 1.8V (Note 2)6.06.7ns
Data to DCLK Hold TimetHOLDCL = 10pF, VOVDD = 1.8V (Note 2)0.41.0ns
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10), (Default Timing see Table 5)Clock Pulse-Width HightCH3.85ns
Clock Pulse-Width LowtCL3.85ns
Clock Duty CycletCH/tCLK30 to 70%
CL = 10pF, VOVDD = 1.8V (Note 2)6.99.211.5Data Delay After Rising Edge of
CLK+tDD
CL = 10pF, VOVDD = 3.3V8.5
Data to DCLK Setup TimetSETUPCL = 10pF, VOVDD = 1.8V (Note 2)1.32.3ns
Data to DCLK Hold TimetHOLDCL = 10pF, VOVDD = 1.8V (Note 2)0.71.5ns
DCLK Duty CycletDCH/tCLKCL = 10pF, VOVDD = 1.8V (Note 2)385064%
MUX Data Duty CycletCHA/tCLKCL = 10pF, VOVDD = 1.8V (Note 2)385062%
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)Setup Time for Valid Clock EdgetSUVEdge mode (Note 2)0.7ns
Hold-Off Time for Invalid Clock
EdgetHOEdge mode (Note 2)0.5ns
Minimum Synchronization Pulse
WidthRelative to input clock period2Cycles
Dual-Channel, 8-Bit, 130Msps ADC
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSLow-level VAVDD1.71.9
Analog Supply VoltageVAVDDHigh-level VAVDD (regulator mode, invoked
automatically)2.33.5V
Digital Output Supply VoltageVOVDD1.73.5V
Dual channel8295
Single channel active48
Standby mode11.515
Power-down mode0.650.9
Analog Supply CurrentIAVDD
Power-down mode, VAVDD = 3.3V1.6
Dual channel148171
Dual channel, VAVDD = 3.3V271
Single channel active86
Standby mode2127
Power-down mode1.21.6
Analog Power DissipationPDA
Power-down mode, VAVDD = 3.3V2.9
Dual-channel mode, CL = 10pF22Digital Output Supply CurrentIOVDDPower-down mode< 0.1mA
Note 1:Specifications TA≥+25°C guaranteed by production test, specifications TA< +25°C guaranteed by design and
characterization.
Note 2:Guaranteed by design and characterization.
175MHz TWO-TONE IMD PLOTMAX19507 toc06
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fIN1 = 172.50053MHz
fIN2 = 177.48741MHz
70MHz TWO-TONE FFT PLOTMAX19507 toc05
FREQUENCY (MHz)
AMPLITUDE (dBFS)204060
fIN1 = 71.49905MHz
fIN2 = 68.502129MHz
175MHz INPUT FFT PLOTMAX19507 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fIN = 175.105057MHz
AIN = -0.508dBFS
SNR = 49.225dB
SINAD = 49.204dB
THD = -72.411dBc
SFDR1 = 80.172dBc
SFDR2 = 69.998dBc
70MHz INPUT FFT PLOTMAX19507 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)204060
fIN = 70.1088714MHz
AIN = -0.531dBFS
SNR = 49.187dB
SINAD = 49.172dB
THD = -73.779dBc
SFDR1 = 76.498dBc
SFDR2 = 71.834dBc
3MHz SINGLE-ENDED INPUT FFT PLOTMAX19507 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fIN = 3.05381775MHz
AIN = -0.496dBFS
SNR = 49.281dB
SINAD = 49.232dB
THD = -68.700dBc
SFDR1 = 69.821dBc
SFDR2 = 68.781dBc
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
Typical Operating Characteristics(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= +25°C, unless otherwise noted.)
3MHz INPUT FFT PLOTFREQUENCY (MHz)
AMPLITUDE (dBFS)
MAX19507 toc01
fIN = 2.99827576MHz
AIN = -0.543dBFS
SNR = 49.135dB
SINAD = 49.120dB
THD = -73.810dBc
SFDR1 = 79.951dBc
SFDR2 = 68.821dBc
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEINL (LSB)
MAX19507 toc0764128192256
MAX19507 toc08
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODEDNL (LSB)64128192256
PERFORMANCE
vs. INPUT FREQUENCY
MAX19507 toc09
PERFORMANCE (dBFS)
SFDR1
SFDR2
-THD
SINADSNR
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX19507 toc18
ANALOG SUPPLY CURRENT (mA)
PERFORMANCE
vs. ANALOG INPUT AMPLITUDE
MAX19507 toc11
ANALOG INPUT AMPLITUDE (dBFS)
PERFORMANCE (dBFS)
SFDR2
SFDR1
-THD
SINAD
SNR55
SINGLE-ENDED PERFORMANCE
vs. INPUT FREQUENCYMAX19507 toc10
INPUT FREQUENCY (MHz)20400
SFDR2SFDR1
-THD
SINADSNR
SINGLE-ENDED PERFORMANCE (dBFS)
Typical Operating Characteristics (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= +25°C, unless otherwise noted.)
Dual-Channel, 8-Bit, 130Msps ADC
PERFORMANCE
vs. SAMPLING FREQUENCYSAMPLING FREQUENCY (Msps)
PERFORMANCE (dBFS)
SFDR2
SFDR1
-THD
SINADSNR55
PERFORMANCE
vs. COMMON-MODE VOLTAGEMAX19507 toc13
COMMON-MODE VOLTAGE (V)
PERFORMANCE (dBFS)
SFDR2
SFDR1-THD
SINADSNR55
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGEMAX19517 toc14
ANALOG SUPPLY VOLTAGE (V)
PERFORMANCE (dBFS)
SFDR2
SFDR1
-THD
SINADSNR55
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGEMAX19507 toc15
ANALOG SUPPLY VOLTAGE (V)
PERFORMANCE (dBFS)
SFDR2
SFDR1
-THD
SINADSNR
ANALOG SUPPLY CURRENT
vs. SAMPLING FREQUENCYMAX19507 toc16
ANALOG SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX19507 toc17
ANALOG SUPPLY CURRENT (mA)6040200-20
-40
Typical Operating Characteristics (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX19507 toc19
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT (mA)
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
MAX19507 toc20
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT (mA)
VOVDD = 1.8V
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCYMAX19507 toc21
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT (mA)
VOVDD = 3.6V
DIGITAL SUPPLY CURRENT
vs. TEMPERATUREMAAX19507 toc22
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)10
VOVDD = 3.6V
VOVDD = 1.8V
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX19507 toc23
DUAL BUS
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGESUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX19507 toc24
MULTIPLEXED BUS
PERFORMANCE
vs. CLOCK DUTY CYCLEMAX19507 toc25
PERFORMANCE (dBFS)4050
SFDR2
SFDR1-THD
SINAD
SNR
PERFORMANCE
vs. TEMPERATUREMAX19507 toc26
PERFORMANCE (dBFS)10-40
SFDR2
SFDR1
-THD
SINAD
SNR
GAIN ERROR
vs. TEMPERATUREMAX19517 toc27
GAIN ERROR (%)10
-40
Typical Operating Characteristics (continued)(VAVDD= VOVDD= 1.8V, internal reference, differential clock, VCLK= 1.5VP-P, fCLK= 130MHz, AIN= -0.5dBFS, data output termina-
tion = 50Ω, TA= +25°C, unless otherwise noted.)
COMMON-MODE VOLTAGE
vs. TEMPERATURETEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)10
VCM = 1.35V
VCM = 1.2V
VCM = 1.05V
VCM = 0.9V
VCM = 0.75V
VCM = 0.6V
VCM = 0.45V
OFFSET ERROR
vs. TEMPERATUREMAX19507 toc28
TEMPERATURE (°C)
OFFSET ERROR (mV)10
Dual-Channel, 8-Bit, 130Msps ADC
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX19507 toc29
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)10
GAIN ERROR vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
GAIN ERROR (%)
MAX19507 toc31
REGULATOR MODE
INPUT CURRENT
vs. COMMON-MODE VOLTAGECOMMON-MODE VOLTAGE (V)
INPUT CURRENT (
MAX19507 toc32
110
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
Pin Description
PINNAMEFUNCTION1, 12, 13, 48AVDDAnalog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF.CMAChannel A Common-Mode Input-Voltage ReferenceINA+Channel A Positive Analog InputINA-Channel A Negative Analog InputSPENActive-Low SPI Enable. Drive high to enable parallel programming mode.REFIOReference Input/Output. To use internal reference, bypass to GND with a > 0.1µF capacitor. See
the Reference Input/Output (REFIO) section for external reference adjustment.
7SHDNActive-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated
on the falling edge of SHDN.I.C.Internally Connected. Leave unconnected.INB+Channel B Positive Analog InputINB-Channel B Negative Analog InputCMBChannel B Common-Mode Input-Voltage ReferenceSYNCClock-Divider Mode Synchronization InputCLK+Clock Positive InputCLK-Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock
input. Otherwise, CLK+/CLK- are self-biased differential clock inputs.
17, 18GNDGround. Connect all ground inputs and EP (exposed pad) together.DORBChannel B Data Over RangeDCLKBChannel B Data Clock
21, 22I.C.Internally Connected. Leave unconnected.D0BChannel B Three-State Digital Output, Bit 0 (LSB)D1BChannel B Three-State Digital Output, Bit 1
25, 36OVDDDigital Supply Voltage. Bypass each OVDD input to GND with a 0.1µF capacitor.D2BChannel B Three-State Digital Output, Bit 2D3BChannel B Three-State Digital Output, Bit 3D4BChannel B Three-State Digital Output, Bit 4D5BChannel B Three-State Digital Output, Bit 5D6BChannel B Three-State Digital Output, Bit 6D7BChannel B Three-State Digital Output, Bit 7 (MSB)
32, 33I.C.Internally Connected. Leave unconnected.D0AChannel A Three-State Digital Output, Bit 0 (LSB)D1AChannel A Three-State Digital Output, Bit 1D2AChannel A Three-State Digital Output, Bit 2D3AChannel A Three-State Digital Output, Bit 3D4AChannel A Three-State Digital Output, Bit 4
Dual-Channel, 8-Bit, 130Msps ADC
Detailed DescriptionThe MAX19507 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 9 clock cycles.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed on to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX19507 functional diagram.
Analog Inputs and Common-Mode
ReferenceApply the analog input signal to the analog inputs
(INA+/INA- or INB+/INB-), which are connected to the
input sampling switch (Figure 3). When the input sam-
pling switch is closed, the input signal is applied to the
sampling capacitors through the input switch resistance.
The input signal is sampled at the instant the input
switch opens. The pipeline ADC processes the sampled
voltage and the digital output result is available 9 clock
cycles later. Before the input switch is closed to begin
the next sampling cycle, the sampling capacitors are
reset to the input common-mode potential.
Common-mode bias can be provided externally or
internally through 2kΩresistors. In DC-coupled applica-
tions, the signal source provides the external bias and
the bias current. In AC-coupled applications, the input
current is supplied by the common-mode input voltage.
For example, the input current can be supplied through
the center tap of a transformer secondary winding.
Alternatively, program the appropriate internal register
through the serial-port interface to supply the input DC
current through internal 2kΩresistors (Figure 3). When
the input current is supplied through the internal resis-
tors, the input common-mode potential is reduced by
the voltage drop across the resistors. The common-
mode input reference voltage can be adjusted through
programmable register settings from 0.45V to 1.35V in
0.15V increments. The default setting is 0.90V. Use this
feature to provide a common-mode output reference to
a DC-coupled driving circuit.
Pin Description (continued)
PINNAMEFUNCTIOND5AChannel A Three-State Digital Output, Bit 5D6AChannel A Three-State Digital Output, Bit 6D7AChannel A Three-State Digital Output, Bit 7 (MSB)DORAChannel A Data Over RangeDCLKAChannel A Data ClockSDIN/FORMATSPI Data Input/Format. Serial-data input when SPEN is low. Output data format when SPEN is high.SCLK/DIVSerial Clock/Clock Divider. Serial clock when SPEN is low. Clock divider when SPEN is high.CS/OUTSELSerial-Port Select/Data Output Mode. Serial-port select when SPEN is low. Data output mode
selection when SPEN is high.
—EPExposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance.
MAX19507Σ+
DIGITAL ERROR CORRECTION
FLASH
ADC
DAC
STAGE 2
IN_+
IN_-
STAGE 1STAGE 9STAGE 10
END OF PIPELINE
D0_ THROUGH D7_
Figure 1. Pipeline Architecture—Stage Blocks
MAX19507
Dual-Channel, 8-Bit, 130Msps ADCT/H
INA+
CMA
REFIO
CMB
INA-
OUTPUT
DRIVERS
DATA
AND
OUTPUT
FORMAT
PIPELINE
ADC
PIPELINE
ADC
CLOCK
CLOCK
DIGITAL
ERROR
CORRECTION
INTERNAL
REFERENCE
GENERATOR
REFERENCE
AND BIAS
SYSTEM
DIGITAL
ERROR
CORRECTION
DUTY-
CYCLE
EQUALIZER
CLOCK
DIVIDER
D0A–D7A
DCLKB
SHDN
GND
DORB
D0B–D7B
OVDD
(1.8V TO 3.3V)
AVDD
(1.8V OR
2.5V TO 3.3V)
DCLKA
DORA
T/H
INB+
INB-
CLK+
CLK-
SYNC
SCLK
SDIN
SERIAL PORT
AND
CONTROL REGISTERS
INTERNAL CONTROL
1.8V INTERNAL
REGULATOR
AND
POWER CONTROL
SPEN
MAX19507
MAX19507
CPAR
0.7pF
INA+
*VCOM
*VCOM PROGRAMMABLE FROM 0.45V TO 1.35V. SEE COMMON-MODE REGISTER (08h)
AVDD
CMA
2kΩ
2kΩ
CSAMPLE
1.2pF
CSAMPLE
1.2pF
CPAR
0.7pF
INA-
AVDD
SAMPLING CLOCK
RSWITCH
120Ω
RSWITCH
120Ω
Figure 2. Functional Diagram
Dual-Channel, 8-Bit, 130Msps ADC
Reference Input/Output (REFIO)REFIO adjusts the reference potential, which, in turn,
adjusts the full-scale range of the ADC. Figure 4 shows
a simplified schematic of the reference system. An
internal bandgap voltage generator provides an internal
reference voltage. The bandgap potential is buffered
and applied to REFIO through a 10kΩresistor. Bypass
REFIO with a 0.1µF capacitor to GND. The bandgap
voltage is applied to a scaling and level-shift circuit,
which creates internal reference potentials that estab-
lish the full-scale range of the ADC. Apply an external
voltage on REFIO to trim the ADC full scale. The allow-
able adjustment range is +5/-15%. The REFIO-to-ADC
gain transfer function is:
VFS= 1.5 x [VREFIO/1.25] Volts
Programming and InterfaceThere are two ways to control the MAX19507 operating
modes. Full feature selection is available using the SPI
interface, while the parallel interface offers a limited set
of commonly used features. The programming mode is
selected using the SPENinput. Drive SPENlow for SPI
interface; drive SPENhigh for parallel interface.
Parallel InterfaceThe parallel interface offers a pin-programmable inter-
face with a limited feature set. Connect SPENto AVDD
to enable the parallel interface. See Table 1 for pin
functionality; see Figure 5 for a simplified parallel-inter-
face input schematic.
BANDGAP
REFERENCEBUFFER
1.250V
REFIO
INTERNAL GAIN—BYPASS REFIO
EXTERNAL GAIN CONTROL—DRIVE REFIO
SCALE AND
LEVEL SHIFTINTERNAL REFERENCE
(CONTROLS ADC GAIN)
10kΩ
0.1μF
EXTERNAL BYPASS
Figure 4. Simplified Reference Schematic
36kΩ
156kΩ
SCLK
SDIN
AVDD
29/32 AVDDDECODER
CONTROL
LOGIC
23/32 AVDD
3/32 AVDD
Figure 5. Simplified Parallel-Interface Input Schematic
SPEN
SDIN/FORMATSCLK/DIVCS/OUTSEL
DESCRIPTIONSDINSCLKCSSPI interface active. Features are programmed through the
serial port (see the Serial Programming Interface section).0XXTwo’s complementAVDDXXOffset binaryUnconnectedXXGray codeX0XClock divide-by-1XAVDDXClock divide-by-2XUnconnectedXClock divide-by-4XX0CMOS (dual bus)XXAVDDMUX CMOS (channel A data bus)XXUnconnectedMUX CMOS (channel B data bus)
Table1. Parallel-Interface Pin FunctionalityX = Don’t care.
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
Serial Programming InterfaceA serial interface programs the MAX19507 control reg-
isters through the CS, SDIN, and SCLK inputs. Serial
data is shifted into SDIN on the rising edge of SCLK
when CSis low. The MAX19507 ignores the data pre-
sented at SDIN and SCLK when CSis high. CCSS
must
transition high after each read/write operation. SDINalso serves as the serial-data output for reading control
registers. The serial interface supports two-byte transfer
in a communication cycle. The first byte is a control
byte, containing the address and read/write instruction,
written to the MAX19507. The second byte is a data
byte and can be written to or read from the MAX19507.
Figure 6 shows a serial-interface communication cycle.
The first SDIN bit clocked in establishes the communi-
cation cycle as either a write or read transaction (0 for
write operation and 1 for read operation). The following
7 bits specify the address of the register to be written or
read. The final 8 SDIN bits are the register data. All
address and data bits are clocked in or out MSB first.
During a read operation, the MAX19507 serial port dri-
ves read data (D7) into SDIN after the falling edge of
SCLK following the 8th rising edge of SCLK. Since the
minimum hold time on SDIN input is zero, the master
can stop driving SDIN any time after the 8th rising edge
of SCLK. Subsequent data bits are driven into SDIN on
the falling edge of SCLK. Output data in a read opera-
tion is latched on the rising edge of SCLK. Figure 7
shows the detailed serial-interface timing diagram.
R/WA6A4A5A2A3A0A1D7D6D4D5D2D3D0D1
R/W
0 = WRITE
1 = READ
SCLK
SDIN
ADDRESSDATA
WRITE OR READ
tCSStCSH
tSDDtSDStSDH
tSCLK
SCLK
SDIN
WRITEREAD
Figure 6. Serial-Interface Communication Cycle
Figure 7. Serial-Interface Timing Diagram
Dual-Channel, 8-Bit, 130Msps ADC
BIT NO.VALUEDESCRIPTION0Reserved0Reserved0 or 11 = ROM read in progress0 or 11 = ROM read completed and register data is valid (checksum is OK)0Reserved1Reserved0 or 1Reserved0 or 11 = Duty-cycle equalizer DLL is locked
Table 2. Register 0Ah Status Byte
ADDRESSPOR DEFAULTFUNCTION00h00000011Power management
01h00000000Output format
02h00000000Digital output power management
03h01101101Data/DCLK timing
04h00000000C H A d ata outp ut ter m i nati on contr ol
05h00000000C H B d ata outp ut ter m i nati on contr ol
06h00000000C l ock d i vi d e/d ata for m at/test p atter n
07hReservedReserved—do not use
08h00000000Common mode
0Ah—Software reset
Table 3. User-Programmable RegistersRegister address 0Ah is a special-function register.
Writing data 5Ah to register 0Ah initiates a register
reset. When this operation is executed, all control regis-
ters are reset to default values. A read operation of reg-
ister 0Ah returns a status byte with information
described in Table 2.
The SHDN input (pin 7) toggles between any two
power-management states. The Power Management
register defines each power-management state. In the
default state, SHDN = 1 shuts down the MAX19507 and
SHDN = 0 returns to full power.
User-Programmable Registers
Power Management (00h)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0HPS_SHDN1STBY_SHDN1C H B_ON _S H D N 1C H A_O N _S H D N 1HPS_SHDN0STBY_SHDN0CHB_ON_SHDN0C H A_O N _S H D N 0
MAX19507
Dual-Channel, 8-Bit, 130Msps ADC
HPS_SHDN0STBY_SHDN0CHA_ON_SHDN0CHB_ON_SHDN0SHDN INPUT = 0*
HPS_SHDN1STBY_SHDN1CHA_ON_SHDN1CHB_ON_SHDN1SHDN INPUT = 1**000Complete power-down001Channel B active, channel A full power-down010Channel A active, channel B full power-downX11Channels A and B active100Channels A and B in standby mode101Channel B active, channel A standby110Channel A active, channel B standby100Channels A and B in standby modeX1XChannels A and B active, output is averagedXX1Channels A and B active, output is averaged
Control Bits:
Output Format (01h)In addition to power management, the HPS_SHDN1
and HPS_SHDN0 activate an A+B adder mode. In this
mode, the results from both channels are averaged.
The MUX_CH bit selects which bus the (A+B)/2 data is
presented.
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 000BIT_ORDER_BBIT_ORDER_AMUX_CHMUX0
*HPS_SHDN0, STBY_SHDN0, CHA_ON_SHDN0, and CHB_ON_SHDN0 are active when SHDN = 0.
**HPS_SHDN1, STBY_SHDN1, CHA_ON_SHDN1, and CHB_ON_SHDN1 are active when SHDN = 1.
X = Don’t care.
Note:When HPS_SHDN_ = 1 (A+B adder mode), CHA_ON_SHDN_ and CHB_ON_SHDN_must BOTHequal 0 for power-down or
standby.
Bit 7, 6, 5Set to 0 for proper operation
Bit 4BIT_ORDER_B: Reverse CHB output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 3BIT_ORDER_A: Reverse CHA output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 2MUX_CH: Multiplexed data bus selection
0 = Multiplexed data output on CHA (CHA data presented first, followed by CHB data) (default)
1 = Multiplexed data output on CHB (CHB data presented first, followed by CHA data)
Bit 1MUX: Digital output mode
0 = Dual data bus output mode (default)
1 = Single multiplexed data bus output mode
MUX_CH selects the output bus
Bit 0Set to 0 for proper operation
