MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterApplicationsTFT Active Matrix LCD DisplaysTOP VIEWPassive Matrix LCD DisplaysRDY 1 16 TGNDPDAsFB 2 ..
MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterFeaturesThe MAX1748 triple-output DC-DC converter in a low- Three Integrated DC-DC Convertersprofi ..
MAX1748EUE ,Triple-Output TFT LCD DC-DC ConverterELECTRICAL CHARACTERISTICS(V = +3.0V, SHDN = IN, V = V = 10V, TGND = PGND = GND, C = 0.22µF, C = 47 ..
MAX1748EUE+ ,Triple-Output TFT-LCD DC-DC ConvertersELECTRICAL CHARACTERISTICS(V = +3.0V, SHDN = IN, V = V = 10V, TGND = PGND = GND, C = 0.22µF, C = 47 ..
MAX1748EUE+ ,Triple-Output TFT-LCD DC-DC ConvertersMAX1748/MAX872619-3430; Rev 0; 10/04Triple-Output TFT-LCD DC-DC Converters
MAX1748EUE+T ,Triple-Output TFT-LCD DC-DC ConvertersFeaturesThe MAX1748/MAX8726 triple-output DC-DC converters♦ Three Integrated DC-DC Convertersin a l ..
MAX4581EEE ,Low-Voltage, CMOS Analog Multiplexers/SwitchesMAX4581/MAX4582/MAX458319-1328; Rev 1; 10/99Low-Voltage, CMOS AnalogMultiplexers/Switches__________ ..
MAX4581EEE ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4581EEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4581EEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesApplications♦ Low Distortion: < 0.02% (600) ΩBattery-Operated Equipment♦ Low Crosstalk: < -96dB (50 ..
MAX4581EPE ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4581ESE ,Low-Voltage, CMOS Analog Multiplexers/SwitchesApplications♦ +2V to +12V Single-Supply OperationBattery-Operated Equipment±2V to ±6V Dual-Supply O ..
MAX17480GTL+-MAX17480GTL+T
AMD 2-/3-Output Mobile Serial VID Controller
General DescriptionThe MAX17480 is a triple-output, step-down, fixed-
frequency controller for AMD’s serial VID interface (SVI)
CPU and northbridge (NB) core supplies. The MAX17480
consists of two high-current SMPSs for the CPU cores
and one 4A internal switch SMPS for the NB core. The
two CPU core SMPSs run 180°out-of-phase for true
interleaved operation, minimizing input capacitance.
The 4A internal switch SMPS runs at twice the switching
frequency of the core SMPS, reducing the size of the
external components.
The MAX17480 is fully AMD SVI compliant. Output volt-
ages are dynamically changed through a 2-wire SVI,
allowing the SMPSs to be individually programmed to
different voltages. A slew-rate controller allows con-
trolled transitions between VID codes and controlled
soft-start. SVI also allows each SMPS to be individually
set into a low-power pulse-skipping state.
Transient phase repeat improves the response of the
fixed-frequency architecture, reducing the total output
capacitance for the CPU core. A thermistor-based tem-
perature sensor provides a programmable thermal-fault
output (VRHOT).
The MAX17480 includes output overvoltage protection
(OVP), undervoltage protection (UVP), and thermal pro-
tection. When any of these protection features detect a
fault, the controller shuts down. True differential current
sensing improves current limit and load-line accuracy.
The MAX17480 has an adjustable switching frequency,
allowing 100kHz to 600kHz operation per core SMPS,
and twice that for the NB SMPS.
ApplicationsMobile AMD SVI Core Supplies
Multiphase CPU Core Supplies
Voltage-Positioned, Step-Down Converters
Notebook/Desktop Computers
FeaturesDual-Output Fixed-Frequency Core Supply
Controller
Split or Combinable Outputs Detected at
Power-Up
Dynamic Phase Selection Optimizes
Active/Sleep Efficiency
Transient Phase Repeat Reduces Output
Capacitance
True Out-of-Phase Operation Reduces Input
Capacitance
Programmable AC and DC Droop
Accurate Current Balance and Current Limit
Integrated Drivers for Large Synchronous-
Rectifier MOSFETs
Programmable 100kHz to 600kHz Switching
Frequency
4V to 26V Battery Input Voltage Range4A Internal Switch Northbridge SMPS
2.7V to 5.5V Input Voltage Range
2x Programmable Switching Frequency
75mΩ/40mΩPower Switches±0.5% VOUTAccuracy over Line, Load, and
TemperatureAMD SVI-Compliant Serial Interface with
Switchable Address7-Bit On-Board DAC: 0 to +1.550V Output Adjust
RangeIntegrated Boost SwitchesAdjustable Slew-Rate ControlPower-Good (PWRGD) and Thermal-Fault
(VRHOT) OutputsSystem Power-OK (PGD_IN) InputOvervoltage, Undervoltage, and Thermal-Fault
ProtectionVoltage Soft-Startup and Passive Shutdown< 1µA Typical Shutdown Current
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Ordering Information19-4443; Rev 0; 2/09
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX17480GTL+ -40°C to +105°C 40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ELECTRICAL CHARACTERISTICS
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD,VIN3,VCC, VDDIOto AGND..............................-0.3V to +6V
PWRGD to AGND.....................................................-0.3V to +6V
SHDNto AGND........................................................-0.3V to +6V
GNDS1, GNDS2, THRM, VRHOTto AGND..............-0.3V to +6V
CSP_, CSN_, ILIM12 to AGND.................................-0.3V to +6V
SVC, SVD, PGD_IN to AGND...................................-0.3V to +6V
FBDC_, FBAC_, OUT3 to AGND..............................-0.3V to +6V
OSC, TIME, OPTION, ILIM3 to AGND........-0.3V to (VCC+ 0.3V)
BST1, BST2 to AGND.............................................-0.3V to +36V
BST1, BST2 to VDD.................................................-0.3V to +30V
BST3 to AGND...................................(VDD- 0.3V) to (VLX3+ 6V)
LX1 to BST1..............................................................-6V to +0.3V
LX3 RMS Current (Note 2).....................................................±4A
LX2 to BST2..............................................................-6V to +0.3V
LX3 to PGND (Note 2)..............................................-0.6V to +6V
DH1 to LX1..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2..............................................-0.3V to (VBST2 + 0.3V)
DL1 to PGND..............................................-0.3V to (VDD + 0.3V)
DL2 to PGND..............................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 22.2mW/°C above +70°C).......1778mW
Operating Temperature Range.........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INPUT SUPPLIES
VIN Drain of external high-side MOSFET 4 26
VBIAS VCC, VDD 4.5 5.5
VIN3 2.7 5.5 Input Voltage Range
VDDIO 1.0 2.7
VCC Undervoltage-Lockout
Threshold VUVLOVCC rising, 50mV typical hysteresis,
latched, UV fault 4.10 4.25 4.45 V
VCC Power-On Reset Threshold
Falling edge, typical hysteresis = 1.1V,
faults cleared and DL_ forced high when
VCC falls below this level
1.8 V
VDDIO Undervoltage-Lockout
Threshold
VDDIO rising, 100mV typical hysteresis,
latched, UV fault 0.7 0.8 0.9 V
VIN3 Undervoltage-Lockout
Threshold VIN3 rising, 100mV typical hysteresis 2.5 2.6 2.7 V
Quiescent Supply Current (VCC) ICC Skip mode, FBDC_ and OUT3 forced
above their regulation points 5 10 mA
Quiescent Supply Currents (VDD) IDD Skip mode, FBDC_ and OUT3 forced
above their regulation points, TA = +25°C 0.01 1 µA
Quiescent Supply Current (VDDIO) IDDIO 10 25 µA
Quiescent Supply Current (IN3) IIN3 Skip mode, OUT3 forced above its
regulation point 50 200 µA
Shutdown Supply Current (VCC)SHDN = GND, TA = +25°C 0.01 1 µA
Note 1:Absolute Maximum Ratings measured with 20MHz scope bandwidth.
Note 2:LX3 has clamp diodes to PGND and IN3. If continuous current is applied through these diodes, thermal limits must be observed.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Shutdown Supply Currents (VDD)SHDN = GND, TA = +25°C 0.01 1 µA
Shutdown Supply Current (VDDIO)SHDN = GND, TA = +25°C 0.01 1 µA
Shutdown Supply Current (IN3) SHDN = GND, TA = +25°C 0.01 1 µA
INTERNAL DACs, SLEW RATE, PHASE SHIFT
DAC codes from
0.8375V to 1.5500V -0.5 +0.5 %
DAC codes from
0.5000V to 0.8250V -5 +5 DC Output Voltage Accuracy
(Note 1) VOUT
Measured at FBDC_
for the core SMPSs;
measured at OUT3
for the NB SMPS;
30% duty cycle, no
load, ILIM3 = VCC,
VOUT3 = VDAC3 +
12.5mV (Note 3)
DAC codes from
12.5mV to 0.4875V -10 +10
mV
OUT3 Offset 12.5 mV
50 % SMPS1 to SMPS2 Phase Shift SMPS2 starts after SMPS1 180 Degrees
SMPS3 to SMPS1 and SMPS2
Phase Shift SMPS3 starts after SMPS1 or SMPS2 25 %
RTIME = 143k, SR = 6.25mV/µs -10 +10
During
transition RTIME = 35.7k to 357k,
SR = 25mV/µs to 2.5mV/µs -15 +15 %Slew-Rate Accuracy
Startup 1 mV/µs
FBAC_ Input Bias Current IFBAC_CSP_ = CSN_, TA = +25°C -3 +3 µA
FBDC_ Input Bias Current IFBDC_TA = +25°C -250 +250 nA
ROSC = 143k (fOSC1 = fOSC2 = 300kHz
nominal, fOSC3 = 600kHz nominal) -7 +7
Switching Frequency Accuracy
fOSC1,
fOSC2,
fOSC3
ROSC = 71.4k (fOSC1 = fOSC2 = 600kHz
nominal, fOSC3 = 1.2MHz nominal) to
432k (fOSC1 = fOSC2 = 99kHz nominal,
fOSC3 = 199kHz nominal)
-9 +9
SMPS1 AND SMPS2 CONTROLLERS
DC Load Regulation Either SMPS, PWM mode, droop disabled;
zero to full load -0.1 %
Line Regulation Error Either SMPS, 4V < VIN < 26V 0.03 %/V
GNDS_ Input Range VGNDS_ Separate mode -200 +200 mV
GNDS_ Gain AGNDS_
Separate:VOUT_/VGNDS_,-200mV VGNDS_
+200mV; combined: VOUT/VGNDS_,
-200mV VGNDS_ +200mV
0.95 1.00 1.05 V/V
GNDS_ Input Bias Current IGNDS_TA = +25°C -2 +2 µA
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Combined-Mode Detection
Threshold
GNDS1, GNDS2, detection after REFOK,
latched, cleared by cycling SHDN0.7 0.8 0.9 V
Maximum Duty Factor DMAX 90 92 %
Minimum On-Time tONMIN 150 ns
SMPS1 AND SMPS2 CURRENT LIMIT
Current-Limit Threshold
ToleranceVLIMITVCSP_ - VCSN_ = 0.052 x (VREF - VILIM),
(VREF - VILM) = 0.2V to 1.0V -3 +3 mV
Zero-Crossing Threshold VZX VGND_ - VLX_, skip mode 1 mV
Idle Mode™ Threshold VIMIN VCSP_ - VCSN_, skip mode, 0.15 x VLIMIT -2 +2 mV
CS_ Input Leakage Current CSP_ and CSN_, TA = +25°C -0.2 +0.2 µA
CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V
SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE
AC Droop and Current Balance
Amplifier Transconductance Gm(FBAC_)IFBAC_/(VCS_), VFBAC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = 0 to +40mV 1.94 2.00 2.06 mS
AC Droop and Current Balance
Amplifier Offset IFBAC_/Gm(FBAC_) -1.5 +1.5 mV
No-Load Positive Offset OPTION = 2V or GND +12.5 mV
Transient Detection Threshold
Measured at FBDC_ with respect to
steady-state FBDC_ regulation voltage,
10mV hysteresis (typ)
-47 -41 -33 mV
SMPS3 INTERNAL 4A STEP-DOWN CONVERTER
OUT3 Load Regulation RDROOP3 4 5.5 7 mV/A
OUT3 Line Regulation 0 to 100% duty cycle 5 mV
OUT3 Input Current IOUT3 TA = +25°C -100 -5 +100 nA
LX3 Leakage Current ILX3SHDN = GND, VLX3 = GND or 5.5V,
VIN3 = 5.5V, TA = +25°C -20 +20 µA
RON(NH3) High-side n-channel 75 150 Internal MOSFET On-Resistance RON(NL3) Low-side n-channel 40 75 m
ILIM3 = VCC 4.75 5.25 6 LX3 Peak Current Limit ILX3PK
ILIM3 = GND 3.75 4.25 5
LX3 Idle-Mode Trip Level ILX3MIN Percentage of ILX3PK 25 %
LX3 Zero-Crossing Trip Level IZX3 Skip mode 20 mA
Maximum Duty Factor DMAX 84 87 %
Minimum On-Time tONMIN 150 ns
Idle Mode is a trademark of Maxim Integrated Products, Inc.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
FAULT DETECTION
PWM mode 250 300 350 mV
Skip mode and output
has not reached the
regulation voltage
1.80 1.85 1.90 Output Overvoltage Trip
Threshold
(SMPS1 and SMPS2 Only)
VOVP_
Measured at
FBDC_, rising
edge
Minimum OVP
threshold 0.8
Output Overvoltage Fault
Propagation Delay (SMPS1 and
SMPS2 Only)
tOVP FBDC_ forced 25mV above trip threshold 10 µs
Output Undervoltage Protection
Trip Threshold VUVP Measured at FBDC_ or OUT3 with respect
to unloaded output voltage -450 -400 -350 mV
Output Undervoltage Fault
Propagation Delay tUVP FBDC_ forced 25mV below trip threshold 10 µs
Lower threshold,
falling edge
(undervoltage)
-350 -300 -250
PWRGD Threshold
Measured at
FBDC_ or OUT3
with respect to
unloaded output
voltage,15mV
hysteresis (typ)
Upper threshold,
rising edge
(overvoltage)
+150 +200 +250
mV
PWRGD Propagation Delay tPWRGD FBDC_ or OUT3 forced 25mV outside the
PWRGD trip thresholds 10 µs
PWRGD, Output Low Voltage ISINK = 4mA 0.4 V
PWRGD Leakage Current IPWRGD High state, PWRGD forced to 5.5V,
TA = +25°C 1 µA
PWRGD Startup Delay and
Transition Blanking Time tBLANK Measured from the time when FBDC_ and
OUT3 reach the target voltage 20 µs
VRHOT Trip Threshold Measured at THRM, with respect to VCC,
falling edge, 115mV hysteresis (typ) 29.5 30 30.5 %
VRHOT Delay tVRHOTTHRM forced 25mV below the VRHOT trip
threshold, falling edge 10 µS
VRHOT, Output Low Voltage ISINK = 4mA 0.4 V
VRHOT Leakage Current High state, VRHOT forced to 5V, TA = +25°C 1 µA
THRM Input Leakage TA = +25°C -100 +100 nA
Thermal-Shutdown Threshold TSHDNHysteresis = 15°C +160 °C
GATE DRIVERS
High state (pullup) 0.9 2.5 DH_ Gate-Driver On-Resistance RON(DH_)BST_ - LX_ forced
to 5V (Note 4) Low state (pulldown) 0.7 2.5
DL_, high state 0.7 2.0 DL_ Gate-Driver On-Resistance RON(DL_)DL_, low state 0.25 0.6
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= 0°C to +85°C, unless otherwise noted.
Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DH_ Gate-Driver Source/Sink
Current IDH_DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.2 A
DL_ Gate-Driver Source Current IDL_DL_ forced to 2.5V 2.7 A
DL_ Gate-Driver Sink Current IDL_ (SINK) DL_ forced to 2.5V 8 A
tDH_DL DH_ low to DL_ high 9 20 35 Dead Time
tDL_DH DL_ low to DH_ high 9 20 35
ns
Internal BST1, BST2 Switch RONBST1, BST2 to VDD, IBST1 = IBST2 = 10mA 10 20
Internal BST3 Switch RONBST3 to VDD, IBST3 = 10mA 10 20
2-WIRE I2C BUS LOGIC INTERFACE
SVI Logic-Input Current SVC, SVD, TA = +25°C -1 +1 µA
SVI Logic-Input Threshold SVC, SVD, rising edge, hysteresis 0.14 x
VDDIO (V)
0.3 x
VDDIO
0.7 x
VDDIOV
SVC Clock Frequency fSVC 3.4 MHz
START Condition Hold Time tHD;STA 160 ns
Repeated START Condition
Setup Time tSU;STA 160 ns
STOP Condition Setup Time tSU;STO 160 ns
Data Hold tHD;DAT
A master device must internally provide a
hold time of at least 300ns for the SVD
signal (referred to the VIHMIN of SVC signal)
to bridge the undefined region of SVC’s
falling edge 70 ns
Data Setup Time tSU;DAT 10 ns
SVC Low Period tLOW 160 ns
SVC High Period tHIGH Measured from 10% to 90% of VDDIO 60 ns
SVC/SVD Rise and Fall Time tR, tFInput filters on SVD and SVC suppress
noise spike less than 50ns 40 ns
Pulse Width of Spike Suppression 20 ns
INPUTS AND OUTPUTS
SHDN, PGD_IN, TA = +25°C -1 +1 µA Logic-Input Current ILIM3, OPTION, TA = +25°C -200 +200 nA
Logic-Input Levels SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V
High, OPTION, ILIM3 VCC -
0.4
3.3V, OPTION 2.75 3.85
2V, OPTION 1.65 2.35
Input Logic Levels
Low, OPTION, ILIM3 0.4
PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV 0.3 x
VDDIO
0.7 x
VDDIOV
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INPUT SUPPLIES
VIN Drain of external high-side MOSFET 4 26
VBIAS VCC, VDD 4.5 5.5
VIN3 2.7 5.5 Input Voltage Range
VDDIO 1.0 2.7
VCC Undervoltage-Lockout
Threshold VUVLOVCC rising, 50mV typical hysteresis,
latched, UV fault 4.10 4.45 V
VDDIO Undervoltage-Lockout
Threshold
VDDIO rising, 100mV typical hysteresis,
latched, UV fault 0.7 0.9 V
VIN3 Undervoltage-Lockout
Threshold VIN3 rising, 100mV typical hysteresis 2.5 2.7 V
Quiescent Supply Current (VCC) ICC Skip mode, FBDC_ and OUT3 forced
above their regulation points 10 mA
Quiescent Supply Current IDDIO 25 µA
Quiescent Supply Current (IN3) IIN3 Skip mode, OUT3 forced above its
regulation point 200 µA
INTERNAL DACs, SLEW RATE, PHASE SHIFT
DAC codes from
0.8375V to 1.5500V -0.7 +0.7 %
DAC codes from
0.5000V to 0.8250V -7.5 +7.5 DC Output Voltage Accuracy VOUT
Measured at FBDC_
for the core SMPSs;
measured at OUT3
for the NB SMPS;
30% duty cycle,
no load, ILIM3 =
VCC, VOUT3 = VDAC3
+ 12.5mV (Note 3)
DAC codes from
12.5mV to 0.4875V -15 +15
mV
RTIME = 143k,
SR = 6.25mV/µs -10 +10
Slew-Rate Accuracy During transition RTIME = 35.7k to
357k, SR =
25mV/µs to 2.5mV/µs
-15 +15
ROSC = 143k (fOSC1 = fOSC2 = 300kHz
nominal, fOSC3 = 600kHz nominal) -9 +9
Switching Frequency Accuracy
fOSC1,
fOSC2,
fOSC3
ROSC = 71.4k (fOSC1 = fOSC2 = 600kHz
nominal, fOSC3 = 1.2MHz nominal) to
432k (fOSC1 = fOSC2 = 99kHz nominal,
fOSC3 = 199kHz nominal)
-12 +12
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SMPS1 AND SMPS2 CONTROLLERS
GNDS_ Input Range VGNDS_ Separate mode -200 +200 mV
GNDS_ Gain AGNDS_
Separate: VOUT_/VGNDS_,-200mV
VGNDS_ +200mV; combined;
VOUT/VGNDS_, -200mVVGNDS_ +200mV
0.95 1.05 V/V
Combined-Mode Detection
Threshold
GNDS1, GNDS2, detection after REFOK,
latched, cleared by cycling SHDN0.7 0.9 V
Maximum Duty Factor DMAX 90 %
Minimum On-Time tONMIN 150 ns
SMPS1 AND SMPS2 CURRENT LIMIT
Current-Limit Threshold
ToleranceVLIMITVCSP_ - VCSN_ = 0.052 x (VREF - VILIM),
(VREF - VILM) = 0.2V to 1.0V -3 +3 mV
Idle-Mode Threshold Tolerance VIMIN VCSP_ - VCSN_, skip mode, 0.15 x VLIMIT -2 +2 mV
CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V
SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE
AC Droop and Current Balance
Amplifier Transconductance Gm(FBAC_)IFBAC_/(VCS_), VFBAC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = 0 to +40mV 1.94 2.06 mS
AC Droop and Current Balance
Amplifier Offset IFBAC_/Gm(FBAC_) -1.5 +2.0 mV
Transient Detection Threshold
Measured at FBDC_ with respect to
steady-state FBDC_ regulation voltage,
10mV hysteresis (typ)
-47 -33 mV
SMPS3 INTERNAL 4A STEP-DOWN CONVERTER
OUT3 Load Regulation RDROOP3 4 7 mV/A
RON(NH3) High-side n-channel 150 Internal MOSFET On-Resistance RON(NL3) Low-side n-channel 75 m
LX3 Peak Current Limit ILX3PK ILIM3 = VCC, skip mode 4.75 6 A
Maximum Duty Factor DMAX 84 %
Minimum On-Time tONMIN 150 ns
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
FAULT DETECTION
PWM mode 250 350 mV
Output Overvoltage Trip
Threshold
(SMPS1 and SMPS2 Only)
VOVP_Measured at
FBDC_, rising edge
Skip mode and
output have not
reached the
regulation voltage
1.80 1.90 V
Output Undervoltage Protection
Trip Threshold VUVP Measured at FBDC_ or OUT3 with respect
to unloaded output voltage -450 -350 mV
Lower threshold,
falling edge
(undervoltage)
-350 -250
PWRGD Threshold
Measured at FBDC_
or OUT3 with respect
to unloaded output
voltage, 15mV
hysteresis (typ)
Upper threshold,
rising edge
(overvoltage)
+150 +250
mV
PWRGD, Output Low Voltage ISINK = 4mA 0.4 V
VRHOT Trip Threshold Measured at THRM, with respect to VCC,
falling edge, 115mV hysteresis (typ) 29.5 30.5 %
VRHOT, Output Low Voltage ISINK = 4mA 0.4 V
GATE DRIVERS
High state (pullup) 2.5 DH_ Gate-Driver On-Resistance RON(DH_)BST_ - LX_ forced to
5V (Note 4) Low state (pulldown) 2.5
DL_, high state 2.0 DL_ Gate-Driver On-Resistance RON(DL_)DL_, low state 0.6
tDH_DL DH_ low to DL_ high 9 35 Dead Time tDL_DH DL_ low to DH_ high 9 35 ns
Internal BST1, BST2 Switch RONBST1, BST2 to VDD, IBST1 = IBST2 = 10mA 20
Internal BST3 Switch RONBST3 to VDD, IBST3 = 10mA 20
2-WIRE I2C BUS LOGIC INTERFACE
SVI Logic-Input Threshold SVC, SVD, rising edge, hysteresis = 0.14 x
VDDIO(V)
0.3 x
VDDIO
0.7 x
VDDIOV
SVC Clock Frequency fSVC 3.4 MHz
START Condition Hold Time tSU;STA 160 ns
Repeated START Condition
Setup Time tSU;STA 160 ns
STOP Condition Setup Time tSU;STO 160 ns
Data Hold tHD;DAT
A master device must internally provide a
hold time of at least 300ns for the SVD signal
(referred to the VIHMIN of SVC signal) to bridge
the undefined region of SVC’s falling edge 70 ns
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure2, VIN = 12V, VCC = VDD = VIN3 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA= -40°C to +105°C, unless otherwise
noted. Typical values are at TA= +25°C.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Setup Time tSU;DAT 10 ns
SVC Low Period tLOW 160 ns
SVC High Period tHIGH Measured from 10% to 90% of VDDIO 60 ns
SVC/SVD Rise and Fall Time tR, tFInput filters on SVD and SVC suppress
noise spike less than 50ns 40 ns
INPUTS AND OUTPUTS
Logic-Input Levels SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V
High, OPTION, ILIM3 VCC -
0.4
3.3V, OPTION 2.75 3.85
2V, OPTION 1.65 2.35
Input Logic Levels
Low, OPTION, ILIM3 0.4
PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV 0.3 x
VDDIO
0.7 x
VDDIOV
Note 3:When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the
error-comparator threshold by 50% of the ripple. The core SMPSs have an integrator that corrects for this error. The NB
SMPS has an offset determined by the ILIM3 pin, and a -6.5mV/A load line.
Note 4:Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the TQFN
package.
Note 5: Specifications to TA= -40°C to +105°C are guaranteed by design, not production tested.
SVC
tHD;STA
tHD;DATtSU;DATtSU;STOtBUF
tLOW
tHIGH
VIH
VIL
SVD
Figure 1. Timing Definitions Used in the Electrical Characteristics
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Typical Operating Characteristics
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
CORE SMPS 1-PHASE EFFICIENCY
vs. LOAD CURRENT (VOUT = 1.2V)
MAX17480 toc01
LOAD CURRENT (A)
EFFICIENCY (%)1
SKIP MODE
PWM MODE
12V
20V
CORE SMPS 2-PHASE EFFICIENCY
vs. LOAD CURRENT (VOUT = 1.2V)
MAX17480 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
12V
20V
PWM MODE
CORE SMPS OUTPUT VOLTAGE
vs. LOAD CURRENT (VOUT = 1.2V)
MAX17480 toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)105
SKIP MODE AND PWM MODE
VIN = 12V
CORE SMPS 1-PHASE EFFICIENCY
vs. LOAD CURRENT (VOUT = 0.8V)
MAX17480 toc04
LOAD CURRENT (A)
EFFICIENCY (%)1
SKIP MODE
PWM MODE
12V7V
20V
CORE SMPS OUTPUT VOLTAGE
vs. LOAD CURRENT (VOUT = 0.8V)
MAX17480 toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)105
SKIP MODE AND PWM MODE
VIN = 12V
NB SMPS EFFICIENCY
vs. LOAD CURRENT (1V)
MAX17480 toc06
LOAD CURRENT (A)
EFFICIENCY (%)
SKIP MODE
PWM MODE
3.3V
NB SMPS 1V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17480 toc07
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)1
SKIP MODE
PWM MODE
VIN = 3.3V
VIN = 5V
CORE SMPS 1-PHASE SWITCHING
FREQUENCY vs. LOAD CURRENT
MAX17480 toc08
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)1
VIN = 20V SKIP
VIN = 20V PWM
VIN = 12V SKIP
VIN = 12V PWM
VIN = 7V SKIP
VIN = 7V PWM
VOUT = 1.2V
NB SMPS SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX17480 toc09
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
VIN = 3.3V SKIP
VIN = 5V PWM
VIN = 3.3V SKIP
VIN = 5V PWM
VOUT = 1V
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
MAXIMUM INDUCTOR CURRENT
vs. INPUT VOLTAGE
MAX17480 toc10
INPUT VOLTAGE (V)
INDUCTOR CURRENT (A)
VOUT = 1.2V
PEAK CURRENT
DC CURRENT
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX17480 toc11
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)2118151296
SKIP MODE
PWM MODE
IIN
IIN
ICC + IDD
ICC + IDD
VOUT = 1.2V
CORE SMPS VID = 1.2V
OUTPUT VOLTAGE DISTRIBUTION
MAX17480 toc12
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
TA = +85°C
TA = +25°C
SAMPLE SIZE = 100
NB SMPS VID = 1.2V
OUTPUT VOLTAGE DISTRIBUTION
MAX17480 toc13
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 100TA = +85°C
TA = +25°C
Gm(FBAC) TRANSCONDUCTANCE
DISTRIBUTION
MAX17480 toc14
TRANSCONDUCTANCE (μS)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 100+85°C
+25°C
NB SMPS PEAK
CURRENT-LIMIT DISTRIBUTION
MAX17480 toc15
PEAK CURRENT LIMIT (A)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 100
ILIM3 = VCC
TA = +85°C
TA = +25°C
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
STARTUP WAVEFORMS
MAX17480 toc16
200μs/div
SHDN, 5V/div
VOUT1, 0.5V/div
VOUT2, 0.5V/div
VOUT3, 0.5V/div
PWRGD, 5V/div
ILX, 5A/div
ILX3, 1A/div
VIN = 12V
VBOOT = 1V
ILOAD1 = 3A
ILOAD2 = 3A
ILOAD3 = 0.5A
STARTUP SEQUENCE
MAX17480 toc17
400μs/div
SHDN, 5V/div
VOUT1, 0.5V/div
VOUT2, 0.5V/div
VOUT3, 0.5V/div
PWRGD, 5V/div
PGD_IN, 2.5V/div
SVC, 2.5V/div
SVD, 2.5V/div
VIN = 12V
VBOOT = 1V
VSVID = 1.2V
SHUTDOWN WAVEFORMS
MAX17480 toc18
100μs/div
3.3V
1.2V
1.2V
1.2V
SHDN, 5V/div
VOUT1, 0.5V/div
VOUT2, 0.5V/div
VOUT3, 0.5V/div
DL1, 10V/div
DL2, 10V/div
LX3, 10V/div
PWRGD, 10V/div
VIN = 12VILOAD1 = 3A
VSVID = 1.2VILOAD2 = 3A
ILOAD3 = 0.5A
CORE SMPS 1-PHASE LOAD-TRANSIENT
RESPONSE
MAX17480 toc19
20μs/div
1.2V
1.5A
13.5A
12V
VOUT1, 50mV/div
ILX1, 10A/div
LX1, 10V/div
VIN = 12VILOAD1 = 1.5A TO 13.5A TO 1.5A
VOUT1 = 1.2VPWM MODE
CORE SMPS 1-PHASE TRANSIENT
PHASE REPEAT
MAX17480 toc20
2μs/div
1.2V
1.5A
13.5A
12V
VOUT1
50mV/div
ILX1
10A/div
LX1
10V/div
VIN = 12VILOAD1 = 1.5A TO 13.5A TO 1.5A
VOUT1 = 1.2VPWM MODE
CORE SMPS 2-PHASE LOAD-TRANSIENT
RESPONSE
MAX17480 toc21
20μs/div
1.2V
1.5A
13.5A
13.5V
1.5A
VOUT
50mV/div
ILX1
10A/div
ILX2
10A/div
VIN = 12VILOAD = 3A TO 27A TO 3A
VOUT1 = 1.2VPWM MODE
CORE SMPS 2-PHASE TRANSIENT
PHASE REPEAT
MAX17480 toc22
2μs/div
1.2V
1.5A
13.5A
13.5A
1.5A
VOUT
50mV/div
ILX1
10A/div
ILX2
10A/div
VIN = 12VILOAD = 3A TO 27A TO 3A
VOUT1 = 1.2VPWM MODE
NB SMPS LOAD-TRANSIENT
RESPONSE
MAX17480 toc23
20μs/div
0.4A
3.6A
VOUT3
50mV/div
ILX3
2A/div
LX3
5V/div
VIN3 = 5V ILOAD3 = 0.4A TO 3.6A TO 0.4A
VOUT3 = 1V PWM MODE
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
CORE SMPS OUTPUT OVERLOAD
WAVEFORM (SEPARATE MODE)
MAX17480 toc24
100μs/div
1.2V
1.2V
1.2V
VIN = 12VILOAD1 = 3A TO 40A
VSVID = 1.2VILOAD2 = 3A
ILOAD3 = 0.5A
SHDN, 5V/div
VOUT1, 1V/div
DL1, 10V/div
VOUT2, 1V/div
VOUT3, 1V/div
DL2, 10V/div
LX3, 10V/div
CORE SMPS OUTPUT OVERVOLTAGE
WAVEFORM (SEPARATE MODE)
MAX17480 toc25
100μs/div
1.2V
1.2V
1.2V
VIN = 12VILOAD1 = NO LOAD
VSVID = 1.2VILOAD2 = 3A
ILOAD3 = 0.5A
SHDN, 5V/div
VOUT1, 1V/div
DL1, 10V/div
VOUT2, 1V/div
VOUT3, 1V/div
DL2, 10V/div
LX3, 10V/div
DYNAMIC OUTPUT-VOLTAGE
TRANSITIONS (LIGHT LOAD)
MAX17480 toc26
100μs/div
0.6V
0.6V
0.6V
1.3V
1.3V
2.5V
2.5V
1.3V
VIN = 12V
VSVID = 1.3V TO 0.6V TO 1.3V
VOUT1, 0.5V/div
VOUT2, 0.5V/div
VOUT3, 0.5V/div
SVC, 2.5V/div
SVD, 2.5V/div
PGD_IN TRANSITION (LIGHT LOAD)
MAX17480 toc27
10µs/div
0.8V
1.1V
1.1V
1.2V
0.9V
VIN = 12V
VBOOT = 1.1V
VOUT1 = 0.8V
VOUT2 = 1.2V
VOUT3 = 0.9V
VOUT, 200mV/div,
VOUT2, 200mV/div
LX1, 20V/div
LX2, 20V/div
LX3, 5V/div
VOUT3, 200mV/div
PWRGD, 5V/div
PGD_IN, 5V/div
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description
PINNAMEFUNCTION
1 ILIM12
SMPS1 and SMPS2 Current-Limit Adjust Input. The positive current-limit threshold voltage is 0.052
times the voltage between TIME and ILIM over a 0.2V to 1.0V range of V(TIME, ILIM). The IMIN12
minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding
positive current-limit threshold voltage.
2 ILIM3
SMPS3 Current-Limit Adjust Input. Two-level current-limit setting for SMPS3. The ILX3MIN minimum
current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit
threshold.
ILIM3ILX3PK (A)
VCC 5.25
GND 4.25
3, 4 IN3 Internal High-Side MOSFET Drain Connection for SMPS3. Bypass to PGND with a 10µF or greater
ceramic capacitor close to the IC.
5, 6 LX3 Inductor Connection for SMPS3. Connect LX3 to the switched side of the inductor.
7 BST3 Boost Flying Capacitor Connection for SMPS3. An internal switch between VDD and BST3 charges
the flying capacitor during the time the low-side FET is on. SHDN
Active-Low Shutdown Control Input. This input cannot withstand the battery voltage. Connect to
VCC for normal operation. Connect to ground to put the IC into its 1µA max shutdown state. During
startup, the output voltage is ramped up to the voltage set by the SVC and SVD inputs at a slew rate
of 1mV/µs. In shutdown, the outputs are discharged using a 20 switch through the CSN_ pins for
the core SMPSs and through the OUT3 pin for the northbridge SMPS.
The MAX17480 powers up to the voltage set by the two SVI bits.
SVCSVDBOOT VOLTAGE
VOUT (V)
0 0 1.1
0 1 1.0
1 0 0.9
1 1 0.8
The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared
by a rising SHDN signal.
9 OUT3 Feedback Input for SMPS3. A 20 discharge FET is enabled from OUT3 to PGND when SMPS3 is
shut down.
10 AGND Analog Ground
11 SVD Serial VID Data
12 SVC Serial VID Clock
13 VDDIO CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at VDDIO.
14 GNDS2
SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2
internally connects to a transconductance amplifier that fine tunes the output voltage—
compensating for voltage drops from the SMPS ground to the load ground.
Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS2 is
pulled above 0.9V, GNDS1 is used as the remote ground-sense input.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PINNAMEFUNCTION
15 FBAC2
Output of the Voltage-Positioning Transconductance Amplifier for SMPS2. The RC network between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
where RDROOP_AC2 is the transient (AC) voltage-positioning slope that provides an acceptable
trade-off between stability and load-transient response, Gm(FBAC2) = 2mS (typ), and RSENSE2 is the
value of the current-sense element that is used to provide the (CSP2, CSN2) current-sense voltage,
ZCFB2 is the impedance of CFB2, and FBAC2 is high impedance in shutdown.
16 FBDC2
Feedback-Sense Input for SMPS2. Connect a resistor RFBDC2 between FBDC2 and the positive side
of the feedback remote sense, and a capacitor from FBAC2 to couple the AC ripple from FBAC2 to
FBDC2. An integrator on FBDC2 corrects for output ripple and ground-sense offset.
To enable a DC load-line less than the AC load-line, add a resistor from FBAC2 to FBDC2.
To enable a DC load-line equal to the AC load-line, short FBAC2 to FBDC2. See the Core Steady-
State Voltage Positioning (DC Droop) section.
FBDC2 is high impedance in shutdown.
17 CSN2
Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current
sensing.
A 20 discharge FET is enabled from CSN2 to PGND when the SMPS2 is shut down.
18 CSP2
Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current
sensing.
19 PGD_IN
System Power-Good Input
PGD_IN is low when SHDN first goes high. The MAX17480 decodes the two SVI bits to determine
the boot voltage. The SVI bits can be changed dynamically during this time while PGD_IN remains
low and PWRGD is still low.
PGD_IN goes high after the MAX17480 reaches the boot voltage. This indicates that the SVI block
is active, and the MAX17480 starts to respond to the SVI commands. The MAX17480 stores the
boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN.
After PGD_IN has gone high, if at any time PGD_IN goes low, the MAX17480 regulates to the
previously stored boot VID. The slew rate during this transition is set by the resistor between the
TIME and GND pins. PWRGD follows the blanking for normal VID transition.
The subsequent rising edge of PGD_IN does not change the stored VID. RRRDROOPACFBACFBDC
FBACFBDCFB_2222=×+ZZRG
CFB
SENSEmFBAC××()
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PINNAMEFUNCTION
20 PWRGD
Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all threeSMPS
outputs.
PWRGD is forced high impedance whenever the slew-rate controller is active (output voltage
transitions).
During startup, PWRGD is held low for an additional 20µs after the MAX17480 reaches the startup
boot voltage set by the SVC and SVD pins. The MAX17480 stores the boot VID when PWRGD first
goes high. The stored boot VID is cleared by rising SHDN.
PWRGD is forced low in shutdown.
When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective
SMPS is blanked during a downward VID transition. The upper PWRGD threshold comparator is re-
enabled once the output is in regulation (Figure 6).
21 DH2 SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.
22 LX2 SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to SMPS2’s zero-crossing comparator.
23 BST2 Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between
VDD and BST2 charges the flying capacitor during the time the low-side FET is on.
24 DL2
SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD. DL2 is forced low in shutdown.
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip
mode after an inductor current zero crossing (GND2 - LX2) is detected.
25 VDD
Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge
the BST_ flying capacitors during the off-time. Connect VDD to the 4.5V to 5.5V system supply
voltage. Bypass VDD to GND with a 2.2µF or greater ceramic capacitor.
26 DL1
SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to VDD. DL1 is forced low in shutdown.
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip
mode after an inductor current zero crossing (GND1 - LX1) is detected.
27 BST1 Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between
VDD and BST1 charges the flying capacitor during the time the low-side FET is on.
28 LX1 SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to SMPS1’s zero-crossing comparator.
29 DH1 SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. VRHOTActive-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at
THRM goes below 1.5V (30% of VCC). VRHOT is high impedance in shutdown.
31 THRM
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC
and GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC)
at the desired high temperature.
32 VCC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1µF minimum
capacitor. A VCC UVLO event that occurs while the IC is functioning is latched, and can only be
cleared by cycling VCC power or by toggling SHDN.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PINNAMEFUNCTION
33 CSP1 Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
34 CSN1
Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
A 20 discharge FET is enabled from CSN1 to PGND when the SMPS1 is shut down.
35 FBDC1
Feedback Sense Input for SMPS1. Connect a resistor RFBDC1 between FBDC1 and the positive side
of the feedback remote sense, and a capacitor from FBAC1 to couple the AC ripple from FBAC1 to
FBDC1. An integrator on FBDC1 corrects for output ripple and ground-sense offset.
To enable a DC load-line less than the AC load-line, add a resistor from FBAC1 to FBDC1.
To enable a DC load-line equal to the AC load-line, short FBAC1 to FBDC1. See the Core Steady-
State Voltage Positioning (DC Droop) section.
FBDC1 is high impedance in shutdown.
36 FBAC1
Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The RC network between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
where RDROOP_AC1 is the transient (AC) voltage-positioning slope that provides an acceptable
trade-off between stability and load-transient response, Gm(FBAC1) = 2mS (typ), RSENSE1 is the
value of the current-sense element that is used to provide the (CSP1, CSN1) current-sense voltage,
ZCFB1 is the impedance of CFB1, and FBAC1 is high impedance in shutdown.
37 GNDS1
SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1
internally connects to a transconductance amplifier that fine tunes the output voltage—
compensating for voltage drops from the SMPS ground to the load ground.
Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS1 is
pulled above 0.9V, GNDS2 is used as the remote ground-sense input.
38 OPTION
Four-Level Input to Enable Offset and Change Core SMPS Address
When OFFSET is enabled, the MAX17480 enables a fixed +12.5mV offset on SMPS1 and SMPS2
VID codes after PGD_IN goes high. This configuration is intended for applications that implement a
load line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting
the PSI_L bit to 0 through the serial interface.
Additionally, the OPTION level also allows core SMPS1 and SMPS2 to take on either the VDD0 or
VDD1 addresses. VDD0 refers to CORE0, and VDD1 refers to CORE1 for the AMD CPU.
The NB SMPS is not affected by the OPTION setting.
OPTIONOFFSET
ENABLED
SMPS1
ADDRESS
SMPS2
ADDRESS
VCC 0 BIT 1 (VDD0) BIT 2 (VDD1)
3.3V 0 BIT 2 (VDD1) BIT 1 (VDD0)
2V 1 BIT 1 (VDD0) BIT 2 (VDD1)
GND 1 BIT 2 (VDD1) BIT 1 (VDD0) RRRDROOPACFBACFBDC
FBACFBDCFB_1111=×+ZZRG
CFB
SENSEmFBAC××()
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PINNAMEFUNCTION
39 OSC
Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching
frequency (per phase):
fOSC = 300kHz x 143k/ROSC
A 71.4k to 432k resistor corresponds to switching frequencies of 600kHz to 100kHz,
respectively, for SMPS1 and SMPS2. SMPS3 runs at twice the programmed switching frequency.
Switching frequency selection is limited by the minimum on-time. See the Core Switching
Frequency description in the SMPS Design Procedure section.
40 TIME
Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate:
PWM slew rate = (6.25mV/µs) x (143k/RTIME)
where RTIME is between 35.7k and 357k.
This slew rate applies to both upward and downward VID transitions, and to the transition from boot
mode to VID mode. Downward VID transition slew rate in skip mode can appear slower because the
output transition is not forced by the SMPS.
The slew rate for startup is fixed at 1mV/µs.
EP PGND Exposed Pad. Power ground connection and source connection of the internal low-side MOSFET.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
COMPONENT
VIN = 7V TO 24V,
VOUT1 = VOUT2 = 1.0V TO
1.3V, 18A PER PHASE
VIN3 = 5V,
VOUT3 = 1.0V TO 1.3V,
VIN = 4.5V TO 14V,
VOUT1 = VOUT2 = 1.0V TO
1.3V, 18A PER PHASE
VIN3 = 3.3V,
VOUT3 = 1.0V TO 1.3V,
Mode Separate, 2-phase mobile
(GNDS1 = GNDS2 = low) —Separate, 2-phase mobile
(GNDS1 = GNDS2 = low) —
Switching
Frequency 300kHz 600kHz 500kHz 1MHz
CIN_ Input
Capacitor
(2) 10µF, 25V
Taiyo Yuden
TMK432BJ106KM
(1) 10µF, 6.3V
TDK C2012X5R0J106M
Taiyo Yuden
JMK212BJ106M
(2) 10µF, 16V
Taiyo Yuden
TMK432BJ106KM
(1) 10µF, 6.3V
TDK C2012X5R0J106M
Taiyo Yuden
JMK212BJ106M
COUT_ Output
Capacitor
(2) 330µF, 2V, 6m,
low-ESR capacitor
Panasonic EEFSX0D331XE
SANYO 2TPE330M6
(1) 220µF, 2V, 6m,
low-ESR capacitor
Panasonic EEFSD0D221R
SANYO 2TPE220M6
(2) 220µF, 2V, 6m,
low-ESR capacitor
Panasonic EEFSD0D221R
SANYO 2TPE220M6
(1) 47µF, ceramic
capacitor
NH_ High-Side
MOSFET
(1) Vishay/Siliconix
SI7634DP None (1) International Rectifier
IRF7811W None
NL_ Low-Side
MOSFET
(2) Vishay/Siliconix
SI7336ADP None (2) Vishay/Siliconix
SI7336ADP None
DL_ Schottky
Rectifier
(if needed)
3A, 40V Schottky diode
Central Semiconductor
CMSH3-40
None
3A, 40V Schottky diode
Central Semiconductor
CMSH3-40
None
L_ Inductor
0.45µH, 21A, 1.1m
power inductor
Panasonic
ETQP4LR45WFC
1.5µH, 5A, 21m
power inductor
NEC/Tokin
MPLCH0525LIR5
Toko FDV0530-1R5M
0.36µH, 21A, 1.1m
power inductor
Panasonic
ETQP4LR36WFC
0.6µH, 4.95A, 16m
power inductor
Sumida CDR6D23MN
Table 1. Component Selection for Standard Applications
Note:Mobile applications should be designed for separate mode operation. Component selection is dependent on AMD CPU AC
and DC specifications.
MANUFACTURERWEBSITE
AVX Corporation www.avxcorp.com
BI Technologies www.bitechnologies.com
Central Semiconductor Corp. www.centralsemi.com
Fairchild Semiconductor www.fairchildsemi.com
International Rectifier www.irf.com
KEMET Corp. www.kemet.com
NEC TOKIN America, Inc. www.nec-tokinamerica.com
Panasonic Corp. www.panasonic.com
MANUFACTURERWEBSITE
Pulse Engineering www.pulseeng.com
Renesas Technology Corp. www.renesas.com
SANYO Electric Co., Ltd. www.sanyodevice.com
Siliconix (Vishay) www.vishay.com
Sumida Corp. www.sumida.com
Taiyo Yuden www.t-yuden.com
TDK Corp. www.component.tdk.com
TOKO America, Inc. www.tokoam.com
Table 2. Component Suppliers
Standard Application Circuit
The MAX17480 standard application circuit (Figure 2)
generates two independent 18A outputs and one 4A
output for AMD mobile CPU applications. See Table 1
for component selections. Table 2 lists the component
manufacturers.
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
MAX17480
NL1DL1
NH1OSCVDDIOSVCSVDTIMEBST1DH1LX1DL1
VCC
VDD
CLX1
CDCR1
CSP1
RILIM2
ROSCILIM12
RVCC
10Ω
RCSP1
CSP1
+5V
CSN1
RCSN1
2x 100kΩ
RNTC
RILIM1
RLX1RDCR1
CVCC
2.2μF
CBST1
0.22μFCSP1CSN1
CCS1
CVDD
1μF
CCSN1
AGND
CIN1
COUT1
2x 330μF
6mΩ
PWR
VIN
4V TO 26V
0.45μH
0.45μH
PWR
PWR
PWR
CSN1
VOUT1/18ATDC
RFBAC1
2kΩ
RFBDC1
2kΩFBAC1FBDC1
CFB1
2200pF
NL2DL2
NH2BST2DH2LX2DL2
CLX2
CDCR2
CSP2
RLX2RDCR2
CBST2
0.22μFCIN2
COUT2
2x 330μF
6mΩ
PWR
VIN
4V TO 26V
PWR
PWR
PWR
PWR
PWR
PWR
CSN2
VOUT2/18ATDC
RCSP2
CSP2
CSN2
CORE0 SENSE_H
RCSN2CSP2CSN2
CCS2
CCSN2
AGND
AGND
1.5V OR 1.8VPGD_INSYSTEM POWER-GOOD
3, 4IN3
5, 6LX3BST3
VIN_NB
2.7V TO 5.5VILIM3VCC
+3.3V
VCC
VOUT3/4ASHDNPWRGDVRHOTTHRM
AGNDOPTION
SERIAL INPUT
CORE0 SENSE_L
100Ω37GNDS1
4700pF
AGND
4700pF
AGND
CORE0
18A
REGULATOR
CORE1
18A
REGULATOR
100Ω
RFBAC2
2kΩ
RFBDC2
2kΩFBAC2FBDC2
CFB2
2200pF
CORE1 SENSE_HPOWER GROUND
ANALOG GROUND
CORE1 SENSE_L
100Ω14GNDS2
4700pF
AGND
4700pF
AGND
100Ω
EP = PGND
ON OFF
OFFSETOPTION
BIT1 (VDD0)
BIT2 (VDD1)
BIT1 (VDD0)
BIT2 (VDD1)
VCC
3.3V
GND
BIT2 (VDD1)
BIT1 (VDD0)
BIT2 (VDD1)
BIT1 (VDD0)
SMPS1
ADDR
SMPS2
ADDR
ILX3_PK (A)ILIM3
+12.5
+12.5
4-LEVEL
ILIM35.25
VCC
GND
SMPS3
OFFSET (mV)
RTHRM
NB SENSE_H9OUT3AGND
CIN_NB
4700pF
CBST3
0.1μF
COUT3
220μF
6mΩ
1.5μH
AGND
AGND
INTERNAL
4A NB
REGULATOR
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
MAX17480
NL1DL1
NH1OSCVDDIOSVCSVDTIMEBST1DH1LX1DL1
VCC
VDD
CLX1
CDCR1
CSP1
RILIM2
ROSCILIM12
RVCC
10Ω
RCSP1
CSP1
+5V
CSN1
RCSN1
2x 100kΩ
RNTC
RILIM1
RLX1RDCR1
CVCC
2.2µF
CBST1
0.22µFCSP1CSN1
CCS1
CVDD
1µF
CCSN1
AGND
CIN1
COUT
3x330µF
6mΩ
PWR
VIN
4V TO 26V
0.45µH
0.45µH
PWR
PWR
PWR
CSN1
VCORE/36ATDC
RFBAC1
2kΩ
RFBDC1
2kΩFBAC1FBDC1
CFB1
2200pF
NL2DL2
NH2BST2DH2LX2DL2
CLX2
CDCR2
CSP2
RLX2RDCR2
CBST2
0.22µF
CIN2
PWR
VIN
4.5V TO 28V
PWR
PWR
PWR
PWR
PWR
CSN2
RCSP2
CSP2
CSN2
CORE0 SENSE_H
RCSN2CSP2CSN2
CCS2
CCSN2
AGND
AGND
1.5V OR 1.8VPGD_INSYSTEM POWER-GOOD
3, 4IN3
5, 6LX3BST3
VIN_NB
2.7V TO 5.5VILIM3VCC
+3.3V
VCC
VOUT3/4ASHDNPWRGDVRHOTTHRM
AGNDOPTION
SERIAL INPUT
CORE0 SENSE_L
100Ω37GNDS1
4700pF
AGND
4700pF
AGND
36A
CORE
REGULATOR
100Ω
RFBAC2
2kΩ
RFBDC2
2kΩFBAC2FBDC2
CFB2
2200pF
VCOREPOWER GROUND
ANALOG GROUND
VDDIO14GNDS2
4700pF
AGND
100Ω
EP = PGND
ON OFF
OFFSETOPTION
BIT1 (VDD0)
BIT2 (VDD1)
BIT1 (VDD0)
BIT2 (VDD1)
VCC
OPEN
REF
GND
BIT2 (VDD1)
BIT1 (VDD0)
BIT2 (VDD1)
BIT1 (VDD0)
SMPS1
ADDR
SMPS2
ADDR
ILX3_PK (A)ILIM3
+12.50
+12.50
4-LEVEL
ILIM35.25
VCC
GND
SMPS3
OFFSET (mV)
RTHRM
NB SENSE_H9OUT3AGND
100Ω
CIN_NB
4700pF
CBST3
0.1µF
COUT3
220µF
6mΩ
1.5µH
AGND
AGND
INTERNAL
4A NB
REGULATOR
CONNECT GNDS2 TO VDDIO
FOR UNIFIED CORE OPERATION
MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
DAC1
UVLO
REFOK
RUN
AGND
REF
(2.0V)
ADDR
SVC
SVD
SVI INTERFACE
PGD_IN
SHDN
VDDIO
DAC2
DAC3
FAULT2
FAULT1
DACOUT1
DACOUT2
VDDIOVCC
OFS_EN
OPTION4-LEVEL
DECODEADDR
OFS_EN
ILIM12CURRENT
LIMIT
IMAX_
IMIN_
CSA_
REF
SKIP_
GNDS1
BLANK1
TARGET1
GNDS2
BLANK2
TARGET2
BLANK3
TARGET3
DACOUT3
OSC
TIME
GNDS2
GNDS1
SMPS1 FAULT
BLOCK
SMPS2 FAULT
BLOCK
SMPS3 FAULT
BLOCK
PGD1
FAULT1FBDC1
TARGET1
BLANK1
PGD2
FAULT2
FBDC2
TARGET2
BLANK2
PGD3
FAULT3
OUT3
TARGET3
BLANK3
IN3
LX3
PGND
BST3
ILIM3
PWR
TARGET3
OUT3
SMPS3 DRIVER
BLOCK
SKIP3
COMBINE
DETECTCOMBINE
CLOCK2
CLOCK1
ISLOPE1
ISLOPE2
CLOCK3
ISLOPE3
CSP_
CSN_
FBDC_SMPS1 AND
SMPS2 PWM
BLOCK
SMPS1 AND
SMPS2 DRIVER
BLOCK
FBAC_
PWM_
CLOCK_
TARGET_
IMIN_
IMAX_
SKIP_
ISLOPE_
CSA_
COMBINE
PWM_
BST_
VDD
DH_
LX_
PGND
DL_
SKIP_
VRHOT
THRM
0.3 x VCC
GNDS MUX
PWRGD
CSP3
CSN3
FAULT3
SMPS1 TARGET
AND SLEW
RATE BLOCK
SMPS2 TARGET
AND SLEW
RATE BLOCK
SMPS3 TARGET
AND SLEW
RATE BLOCK
PWR
MAX17480
7-BIT VID
SKIP1
7-BIT VID
SKIP2
7-BIT VID
SKIP3
OSCILLATOR
Figure 4. Functional Diagram
