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MAX1718BEEI+ |MAX1718BEEIMAXN/a22avaiNotebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)
MAX1718BEEI-T |MAX1718BEEITMAXIMN/a35000avaiNotebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)
MAX1718EEI+ |MAX1718EEIMAXN/a24avaiNotebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)
MAX1718EEI+T |MAX1718EEITMAXN/a2502avaiNotebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)
MAX1718EEI-C71059 |MAX1718EEIC71059MAXIMN/a1000avaiNotebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)


MAX1718BEEI-T ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)Features♦ Quick-PWM Architecture The MAX1718 step-down controller is intended for coreCPU DC-DC co ..
MAX1718EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIFeatures Quick-PWM Architecture The MAX1718 step-down controller is intended for coreCPU DC-DC co ..
MAX1718EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIApplicationsresponse to load transients while maintaining a relativelyconstant switching frequency. ..
MAX1718EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIMAX171819-1960; Rev 3; 8/02Notebook CPU Step-Down Controller for Intel-Mobile Voltage Positioning ( ..
MAX1718EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, V = V = SKP/SDN = 5V, V = 1.25V, T = 0°C ..
MAX1718EEI ,Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-IIMAX171819-1960; Rev 3; 8/02Notebook CPU Step-Down Controller for Intel-Mobile Voltage Positioning ( ..
MAX4545EAP ,Quad/Dual, Low-Voltage, Bidirectional RF/Video SwitchesApplications______________Ordering InformationRF SwitchingVideo Signal RoutingPART TEMP. RANGE PIN- ..
MAX4545EAP+ ,Quad/Dual, Low-Voltage, Bidirectional RF Video SwitchesFeaturesThe MAX4545/MAX4546/MAX4547 are low-voltage ♦ Low 50Ω Insertion Loss: -1dB at 100MHzT-switc ..
MAX4545EAP+ ,Quad/Dual, Low-Voltage, Bidirectional RF Video SwitchesApplications______________Ordering InformationRF SwitchingVideo Signal RoutingPART TEMP. RANGE PIN- ..
MAX4545EWP ,Quad/Dual, Low-Voltage, Bidirectional RF/Video SwitchesFeaturesThe MAX4545/MAX4546/MAX4547 are low-voltage ' Low 50Ω Insertion Loss: -1dB at 100MHzT-switc ..
MAX4546CEE ,Quad/Dual, Low-Voltage, Bidirectional RF/Video SwitchesGeneral Description ________
MAX4546CEE+ ,Quad/Dual, Low-Voltage, Bidirectional RF Video SwitchesGeneral Description ________


MAX1718BEEI+-MAX1718BEEI-T-MAX1718EEI+-MAX1718EEI+T-MAX1718EEI-C71059
Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning (IMVP-II)
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

19-1960; Rev 4; 8/05
Ordering Information

†P.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
IMVP-II is a trademark of Intel Corp.
VCC
VCC
5V INPUT
BATT 2V TO 28V
POWER-GOOD
OUTPUT
SKP/SDN
ILIM
OUTPUT
0.6V TO 1.75V
SHUTDOWN
BST
GND
NEG
POS
VGATE
OVP
VDD
SUSMUX CONTROL
SUSPEND
INPUT
DECODER
ZMODE
TIME
REF
TON
DUAL MODE VID
MUX INPUTS
MAX1718
Minimal Operating Circuit
General Description

The MAX1718 step-down controller is intended for core
CPU DC-DC converters in notebook computers. It fea-
tures a dynamically adjustable output, ultra-fast transient
response, high DC accuracy, and high efficiency need-
ed for leading-edge CPU core power supplies. Maxim’s
proprietary Quick-PWM™ quick-response, constant-on-
time PWM control scheme handles wide input/output
voltage ratios with ease and provides 100ns “instant-on”
response to load transients while maintaining a relatively
constant switching frequency.
The output voltage can be dynamically adjusted through
the 5-bit digital-to-analog converter (DAC) over a 0.6V to
1.75V range. The MAX1718 has an internal multiplexer
that accepts three unique 5-bit VID DAC codes corre-
sponding to Performance, Battery, and Suspend modes.
Precision slew-rate control†provides “just-in-time” arrival
at the new DAC setting, minimizing surge currents to
and from the battery.
The internal DAC of the MAX1718B is synchronized to
the slew-rate clock for improved operation under
aggressive power management of newer chipsets and
operating systems that can make incomplete mode tran-
sitions.
A pair of complementary offset control inputs allows
easy compensation for IR drops in PC board traces or
creation of a voltage-positioned power supply. Voltage-
positioning modifies the load-transient response to
reduce output capacitor requirements and total system
power dissipation.
Single-stage buck conversion allows these devices to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, two-stage conversion
(stepping down the 5V system supply instead of the bat-
tery) at a higher switching frequency allows the mini-
mum possible physical size.
The MAX1718 is available in a 28-pin QSOP package.
Applications

IMVP-II™ Notebook Computers
2-Cell to 4-Cell Li+ Battery to CPU Core Supply
Converters
5V to CPU Core Supply Converters
Features
Quick-PWM Architecture ±1% VOUTAccuracy Over Line and Load5-Bit On-Board DAC with Input MuxesPrecision-Adjustable VOUTSlew Control 0.6V to 1.75V Output Adjust RangePrecision Offset ControlSupports Voltage-Positioned Applications2V to 28V Battery Input Range Requires a Separate 5V Bias Supply200/300/550/1000kHz Switching FrequencyOver/Undervoltage ProtectionDrives Large Synchronous-Rectifier FETs700µA (typ) ICCSupply Current2µA (typ) Shutdown Supply Current2V ±1% Reference Output VGATE Blanking During Transition Small 28-Pin QSOP Package
Pin Configuration appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1718EEI-40°C to +85°C28 QSOP
MAX1718BEEI+-40°C to +85°C28 QSOP
MAX1718BEEI-40°C to +85°C28 QSOP
MAX1718BEEIB+-40°C to +85°C28 QSOP
+Denotes lead-free package.
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= 0°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +30V
VCC, VDDto GND.....................................................-0.3V to +6V
D0–D4, ZMODE,VGATE, OVP, SUS, to GND .........-0.3V to +6V
SKP/SDNto GND...................................................-0.3V to +16V
ILIM, CC, REF, POS, NEG, S1, S0,
TON, TIME to GND.................................-0.3V to (VCC+ 0.3V)
DL to GND..................................................-0.3V to (VDD+ 0.3V)
BST to GND............................................................-0.3V to +36V
DH to LX.....................................................-0.3V to (BST + 0.3V)
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND...........................................Continuous
Continuous Power Dissipation
28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITS
228
Battery voltage, V+
VCC, VDDInput Voltage Range
DC Output Voltage Accuracy
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from 0.9V to 1.75V
DAC codes from 0.6V to 0.875V+1
-1.5+1.5
Line Regulation ErrorVCC= 4.5V to 5.5V, VBATT= 4.5V to 28V5mV
Input Bias CurrentFB, POS, NEG-0.2+0.2µA0.42.5POS, NEG Common-Mode Range
TIME Frequency Accuracy
150kHz nominal, RTIME= 120kΩ
380kHz nominal, RTIME= 47kΩ
38kHz nominal, RTIME= 470kΩ
V+ = 5V, FB = 1.2V, TON = GND (1000kHz) +8
-12+12
-12+12
TON = REF (550kHz)
TON = open (300kHz)
TON = VCC(200kHz)
V+ = 12V, FB = 1.2VOn-Time (Note 1)
Minimum Off-Time (Note 1)TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz)
TON = GND (1000kHz)
300375ns7001200Measured at VCC, FB forced above the regulation pointQuiescent Supply Current (VCC)
Quiescent Supply Current (VDD)Measured at VDD, FB forced above the regulation point<15µA2540Quiescent Battery Supply
Current (V+)
Shutdown Supply Current (VCC)
Shutdown Supply Current (VDD)
SKP/SDN= GND
SKP/SDN= GND5<15SKP/SDN= GND, VCC= VDD= 0V or 5VShutdown Battery Supply
Current (V+)
Reference VoltageVCC= 4.5V to 5.5V, no REF load1.9822.02V-80+80POS - NEGPOS, NEG Differential Range
V/V0.810.860.91∆VFB / (POS - NEG); POS - NEG = 50mVPOS, NEG Offset Gain
PWM CONTROLLER
BIAS AND REFERENCE
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

Current-Limit Threshold Voltage
(Zero Crossing)4mVGND - LX
DH Gate Driver On-Resistance1.03.5ΩBST - LX forced to 5V
Current-Limit Default
Switchover Threshold3VCC-1VCC-0.4V= 0°C to +85°C85115= +25°C to +85°C
ILIM = REF (2V)
ILIM = 0.5V
PARAMETERMINTYPMAXUNITS

Output Undervoltage Fault
Blanking Time256clks
Output Undervoltage Fault
Propagation Delay10µs
Output Undervoltage Fault
Protection Threshold657075%
Overvoltage Fault Propagation
Delay10µs
Current-Limit Threshold Voltage
(Positive, Default)100110
Current-Limit Threshold Voltage
(Positive, Adjustable)5065mV165200230
REF Sink Current
Reference Load Regulation0.01VµA
Overvoltage Trip Threshold1.952.002.05V
Current-Limit Threshold Voltage
(Negative)-140-117-95mV
Thermal Shutdown Threshold150°C
VCCUndervoltage Lockout
Threshold4.14.4V
1.03.5DL Gate Driver On-Resistance 0.41.0Ω
DH Gate-Driver Source/Sink
Current 1.6A
DL Gate-Driver Sink Current4A
CONDITIONS

LX - GND, ILIM = VCC
From SKP/SDNsignal going high, clock speed set by RTIME
Hysteresis = 10°C
FB forced 2% below trip threshold
With respect to unloaded output voltage
FB forced 2% above trip threshold
GND - LX, ILIM = VCC
Rising edge, hysteresis = 20mV, PWM disabled below
this level
GND - LX
DL, high state (pullup)
DL, low state (pulldown)
DH forced to 2.5V, BST - LX forced to 5V
IREF= 0µA to 50µA
DL forced to 2.5V
REF in regulation
Measured at FB
VGATE Lower Trip Threshold-12-10-8%Measured at FB with respect to unloaded output voltage
VGATE Upper Trip Threshold+8+10+12%Measured at FB with respect to unloaded output voltage
VGATE Propagation Delay10µsFB forced 2% outside VGATE trip threshold
VGATE Output Low Voltage0.4VISINK= 1mA
VGATE Leakage Current1µAHigh state, forced to 5.5V
ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= 0°C to +85°C, unless otherwise noted.)
FAULT PROTECTION
GATE DRIVERS
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= 0°C to +85°C, unless otherwise noted.)+8
-2.0+2.0
-1.5+1.5
MINTYPMAX

-12+12
-12+12
465565TON = VCC(200kHz)
TON = open (300kHz)
TON = REF (550kHz)
V+ = 12V, FB = 1.2VOn-Time (Note 1)
V+ = 5V, FB = 1.2V, TON = GND (1000kHz)
38kHz nominal, RTIME= 470kΩ
380kHz nominal, RTIME= 47kΩ
150kHz nominal, RTIME= 120kΩ
TIME Frequency Accuracy
DAC codes from 0.6V to 0.875V
DAC codes from 0.9V to 1.75VV+ = 4.5V to 28V,
includes load
regulation error
CONDITIONS

DC Output Voltage Accuracy
PARAMETERUNITS

PWM CONTROLLER
SKP/SDNFloat LevelISKP/SDN= 0µA1.82.2
PARAMETERCONDITIONSMINTYPMAXUNITS
1.6DL forced to 2.5VDL Gate-Driver Source Current
D0–D4 Pullup/PulldownEntering impedance modePullup
PulldownkΩ-1+1+1
D0–D4, ZMODE = GND
ZMODE, SUS, OVPLogic Input Current
4 Level Input Logic Levels
(TON, S0, S1)
For high
For open
For REF
For low
VCC- 0.4
0.5-3+3SKP/SDN, S0, S1, TON forced to GND or VCCSKP/SDN,S0, S1, and TON Input
Current
SKP/SDNInput Levels
SKP/SDN= logic high (SKIP mode)
SKP/SDN= open (PWM mode)
SKP/SDN= logic low (shutdown mode)
To enable no-fault mode15
2.8695D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
ZMODE = VCC
DAC B-Mode Programming
Resistor, High 1.05D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
ZMODE = VCC
DAC B-Mode Programming
Resistor, Low 0.8D0–D4, ZMODE, SUS, OVPLogic Input Low Voltage2.4D0–D4, ZMODE, SUS, OVPLogic Input High VoltageDH risingns35DL risingDead Time
LOGIC AND I/O
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
Measured at VDD, FB forced above the regulation pointµA5Quiescent Supply Current (VDD)40Quiescent Battery Supply
Current (V+)
SKP/SDN= 0
SKP/SDN= 05Shutdown Supply Current (VDD)5Shutdown Supply Current (VCC)
VCC= 4.5V to 5.5V, no REF load
SKP/SDN= 0, VCC= VDD= 0 or 5V
CONDITIONS
1.982.02Reference Voltage5Shutdown Battery Supply
Current (V+)
UNITSMINTYPMAXPARAMETER

Measured at FB
DL, low state (pulldown)
DL, high state (pullup)
GND - LX
Rising edge, hysteresis = 20mV, PWM disabled below this
level
GND - LX, ILIM = VCC
With respect to unloaded output voltage
LX - GND, ILIM = VCC1.0
3.5DL Gate Driver On-Resistance 4.14.4VCCUndervoltage Lockout
Threshold-145-90Current-Limit Threshold Voltage
(Negative)1.952.05Overvoltage Trip Threshold
160240mV3365Current-Limit Threshold Voltage
(Positive, Adjustable)80115Current-Limit Threshold Voltage
(Positive, Default)6575Output Undervoltage Protection
Threshold
ILIM = 0.5V
ILIM = REF (2V)
Measured at VCC, FB forced above the regulation pointµA1300Quiescent Supply Current (VCC)
BST - LX forced to 5VΩ3.5DH Gate Driver On-Resistance
TON = GND (1000kHz)ns375Minimum Off-Time (Note 1)TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz)500
Measured at FB with respect to unloaded output voltage%-12.5-7.5VGATE Lower Trip Threshold
Measured at FB with respect to unloaded output voltage%+7.5+12.5VGATE Upper Trip Threshold
BIAS AND REFERENCE
FAULT PROTECTION
GATE DRIVERS
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
Typical Operating Characteristics

(Circuit of Figure 1, V+ = 12V, VDD= VCC= SKP/SDN= 5V, VOUT= 1.25V, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
300kHz VOLTAGE POSITIONED
MAX1718 toc01
LOAD CURRENT (A)
EFFICIENCY (%)65SKIP MODE
V+ = 7V
SKIP MODE
V+ = 20V
PWM MODE
V+ = 12V
PWM MODE
V+ = 20V
SKIP MODE
V+ = 12V
PWM MODE
V+ = 7V
FREQUENCY vs. LOAD CURRENT
MAX1718 toc02
LOAD CURRENT (A)
FREQUENCY (kHz)
PWM MODE
SKIP MODE
FREQUENCY vs. INPUT VOLTAGE
MAX1718 toc03
INPUT VOLTAGE (V)
FREQUENCY (kHz)
IOUT = 18A
IOUT = 3A
FREQUENCY vs. TEMPERATURE
MAX1718 toc04
TEMPERATURE (°C)
FREQUENCY (kHz)
IOUT = 19A
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
MAX1718 toc05
TEMPERATURE (°C)
CURRENT (A)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX1718\ toc06
INPUT VOLTAGE (V)
SUPPLY CURRENT (
ICC + IDD
Note 1:
On-Time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced to 5V, and a 500pF
capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to
MOSFET switching speeds.
Note 2:
Specifications to TA= -40°C are guaranteed by design and not production tested.
ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= SKP/SDN= 5V, VOUT= 1.25V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
ZMODE = VCCkΩ95DAC B-Mode Programming
Resistor, High
D0–D4, ZMODE, SUS, OVPV0.8Logic Input Low Voltage
CONDITIONSUNITSMINTYPMAXPARAMETER

D0–D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor,
ZMODE = VCCkΩ1.05DAC B-Mode Programming
Resistor, Low
D0–D4, ZMODE, SUS, OVPV2.4Logic Input High Voltage
LOGIC AND I/O
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX1718 toc07
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
ICC + IDD
40μs/div
LOAD-TRANSIENT RESPONSE
(PWM MODE)

MAX1718 toc08b
B0A
A = VOUT, 50mV/div, AC-COUPLED
B = INDUCTOR CURRENT, 10A/div
40μs/div
LOAD-TRANSIENT RESPONSE
(SKIP MODE)

MAX1718 toc08a
A = VOUT, 50mV/div, AC-COUPLED
B = INDUCTOR CURRENT, 10A/div
100μs/div
STARTUP WAVEFORM
(PWM MODE, NO LOAD)

MAX1718 toc09
B0A
A = VOUT, 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
100μs/div
STARTUP WAVEFORM
(PWM MODE, IOUT = 12A)

MAX1718 toc10
BOA
A = VOUT, 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
40μs/div
DYNAMIC OUTPUT VOLTAGE TRANSITION
(PWM MODE)

MAX1718 toc11
BOA
A = VOUT, 100mV/div, AC-COUPLED
B = INDUCTOR CURRENT, 10A/div
C = VGATE, 5V/div
D = ZMODE, 5V/div
VOUT = 1.15V TO 1.25V
IOUT = 3A, RTIME = 62kΩ
Typical Operating Characteristics (continued)

(Circuit of Figure 1, V+ = 12V, VDD= VCC= SKP/SDN= 5V, VOUT= 1.25V, TA= +25°C, unless otherwise noted.)
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

100μs/div
SHUTDOWN WAVEFORM
(PWM MODE, NO LOAD)

MAX1718 toc13
B0A
A = VOUT, 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
100μs/div
SHUTDOWN WAVEFORM
(PWM MODE, IOUT = 12A)

MAX1718 toc14
B0A
A = VOUT, 1V/div
B = INDUCTOR CURRENT, 10A/div
C = SKP/SDN, 5V/div
Typical Operating Characteristics (continued)

(Circuit of Figure 1, V+ = 12V, VDD= VCC= SKP/SDN= 5V, VOUT= 1.25V, TA= +25°C, unless otherwise noted.)
40μs/div
DYNAMIC OUTPUT VOLTAGE TRANSITION
(PWM MODE)

MAX1718 toc12
B0A
A = VOUT, 500mV/div, AC-COUPLED
B = INDUCTOR CURRENT, 10A/div
C = VGATE, 5V/div
D = SUS, 5V/div
VOUT = 0.7V TO 1.25V
IOUT = 3A, RTIME = 62kΩ
OFFSET FUNCTION SCALE FACTOR
vs. DAC SETTING
MAX1718 toc15
DAC SETTING (V)
POS-NEG SCALE FACTOR
MEASURED
THEORETICAL
OUTPUT VOLTAGE
vs. POS-NEG DIFFERENTIAL
MAX1718 toc16
POS-NEG (mV)
OUTPUT VOLTAGE (V)
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
Typical Operating Characteristics (continued)

(Circuit of Figure 1, V+ = 12V, VDD= VCC= SKP/SDN= 5V, VOUT= 1.25V, TA= +25°C, unless otherwise noted.)
OUTPUT VOLTAGE DISTRIBUTION
MAX1718 toc17
OUTPUT VOLTAGE ERROR (%)
SAMPLE PERCENTAGE (%)
VOUT = 1.25V
REFERENCE VOLTAGE DISTRIBUTION
MAX1718 toc18
REFERENCE VOLTAGE (V)
SAMPLE PERCENTAGE (%)
Analog Supply Voltage Input for PWM Core. Connect VCCto the system supply voltage (4.5V to 5.5V) with a
series 20Ωresistor. Bypass to GND with a 0.22µF (min) capacitor. VCC9
Suspend-Mode Voltage Select Input. S0 and S1 are four-level digital inputs that select the suspend-mode
VID code for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID code is delivered
to the DAC (see the Internal Multiplexers (ZMODE/SUS)section).
S0, S17, 8CCIntegrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CC to GND to set the
integration time constant (see the Integrator Amplifiers/Output Voltage Offsets section).
Feedback Offset Adjust Negative Input. The output shifts by an amount equal to the difference between POS
and NEG multiplied by a scale factor that depends on the DAC codes (see the Integrator Amplifiers/Output
Voltage Offsets section). Connect both POS and NEGto REF if the offset function is not used.
NEG5FBFeedback Input. Connect FB to the junction of the external inductor and the positioning resistor (Figure 1).
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 470kΩ
to 47kΩresistor sets the clock from 38kHz to 380kHz, fSLEW= 150kHz ✕120kΩ/ RTIME.TIME3SKP/SDN
Combined Shutdown and Skip-Mode Control. Drive SKP/SDNto GND for shutdown. Leave SKP/SDNopen for
low-noise forced-PWM mode, or drive to VCCfor pulse-skipping operation. Low-noise forced-PWM mode caus-
es inductor current recirculation at light loads and suppresses pulse-skipping operation. Forcing SKP/SDNto
12V to 15V disables both the overvoltage protection and undervoltage protection circuits and clears the fault
latch, with otherwise normal pulse-skipping operation. Do not connect SKP/SDNto > 15V.
Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot
timing. DH on-time is inversely proportional to input voltage over a range of 2V to 28V.V+1
PINNAMEFUNCTION
Pin Description
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
Pin Description (continued)

Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V. Bypass to GND with a 1µF capacitor. VDD17
Low-Side Gate Driver Output. DL swings GND to VDD.DL16
Analog and Power Ground. Also connects to the current-limit comparator.GND15
Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. If VFBis not within
a ±10% window of the DAC setting, VGATE is asserted low. During DAC code transitions, VGATE is forced
high until 1 clock period after the slew-rate controller finishes the transition. VGATE is low during shutdown.
VGATE14
Feedback Offset Adjust Negative Input. The output shifts by an amount equal to the difference between POS
and NEG multiplied by a scale factor that depends on the DAC codes (see the Integrator Amplifiers/Output
Voltage Offsets section). Connect both POS and NEGto REF if the offset function is not used.
POS13
Current-Limit Adjustment. The GND - LX current-limit threshold defaults to 100mV if ILIM is connected to
VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to
3V range. The logic threshold for switchover to the 100mV default value is approximately VCC- 1V. Connect
ILIM to REF for a fixed 200mV threshold.
ILIM12
2V Reference Output. Bypass to GND with 0.22µF (min) capacitor. Can source 50µA for external loads.
Loading REF degrades FB accuracy according to the REF load-regulation error.REF11
On-Time Selection Control Input. This is a four-level input that sets the K factor (Table 2) to determine
DH on-time. Connect TON to the following pins for the indicated operation:
GND = 1000kHz
REF = 550kHz
Open = 300kHz
VCC= 200kHz
TON10
PINNAMEFUNCTION

Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0 and
S1, is delivered to the DAC. Connect SUS to GND if the Suspend-mode multiplexer is not used (see the
Internal Multiplexers(ZMODE/SUS) section).
SUS18
Performance-Mode MUX Control Input. If SUS is low, ZMODE selects between two different VID DAC codes.
If ZMODE is low, the VID DAC code is set by the logic-level voltages on D0–D4. On the rising edge of
ZMODE, during power-up with ZMODE high, or on the falling edge of SUS when ZMODE is high, the VID
DAC code is determined by the impedance at D0–D4 (see the Internal Multiplexers (ZMODE/SUS)section).
ZMODE19
Overvoltage Protection Control Input. Connect OVPlow to enable overvoltage protection. Connect OVPhigh
to disable overvoltage protection. The overvoltage trip threshold is approximately 2V. The state of OVPdoes
not affect output undervoltage fault protection or thermal shutdown.
OVP20
VID DAC Code Inputs. D0 is the LSB, and D4 is the MSB of the internal 5-bit VID DAC (Table 3). If ZMODE
is low, D0–D4 are high-impedance digital inputs, and the VID DAC code is set by the logic-level voltages on
D0–D4. On the rising edge of ZMODE, during power-up with ZMODE high, or on the falling edge of SUS
when ZMODE is high, the VID DAC code is determined by the impedance at D0–D4 as follows:
Logic low = source impedance is ≤1kΩ+ 5%.
Logic high = source impedance is ≥100kΩ- 5%.
D4–D021–25
Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in
Figure 1. An optional resistor in series with BST allows the DH pullup current to be adjusted (Figure 8).BST26
Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It also connects to
the current-limit comparator and the skip-mode zero-crossing comparator. LX27
High-Side Gate-Driver Output. DH swings LX to BST.DH28
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

VCC
VCC
5V INPUT
BATT 7V TO 24V
POWER-GOOD
OUTPUT
0.68μH
SKP/SDN
TON
1μF17
OUTPUT
0.6V TO 1.75V
CMPSH-3
CENTRAL
SEMICONDUCTOR
CMSH5-40
1μF
0.1μF
0.22μF
47pF
IRF7811A
FDS7764A
100kΩ
C2, 25V, X5R
5 x 10μF
6 x 270μF, 2V
PANASONIC SP
EEFUE0D271R
20Ω
SHUTDOWN
BST
GND
NEG
POS
VGATE
OVP
VDD
MAX1718D4S1S0SUS
MUX CONTROL
SUSPEND
INPUT
DECODER
ZMODE
TIME
REF
ILIM
62kΩ
100kΩ
100kΩ
4.75kΩ
511kΩ
0.004Ω
REF
R19
27.4kΩ
R18
24.9kΩ
SUMIDA
CEP125#4712-TO11
Figure 1. Standard Application Circuit
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
Detailed Description
5V Bias Supply (VCCand VDD)

The MAX1718 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator.
The 5V bias supply must provide VCC(PWM controller)
and VDD(gate-drive power), so the maximum current
drawn is:
IBIAS= ICC+ f (QG1+ QG2) = 10mA to 40mA (typ)
where ICCis 800µA (typ), f is the switching frequency,
and QG1and QG2are the MOSFET data sheet total
gate-charge specification limits at VGS= 5V.
V+ and VDDcan be tied together if the input power
source is a fixed 4.5V to 5.5V supply. If the 5V bias
supply is powered up prior to the battery supply, the
enable signal(SKP/SDNgoing from low to high or
open) must be delayed until the battery voltage is pre-
sent to ensure startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward

The Quick-PWM control architecture is a pseudofixed-
frequency, constant-on-time current-mode type with
voltage feed-forward (Figure 2). This architecture relies
on the output filter capacitor’s ESR to act as the cur-
rent-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined sole-
ly by a one-shot whose period is inversely proportional
to input voltage and directly proportional to output volt-
age. Another one-shot sets a minimum off-time (400ns
typ). The on-time one-shot is triggered if the error com-
parator is low, the low-side switch current is below the
current-limit threshold, and the minimum off-time one-
shot has timed out.
On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V+ input, and proportional
to the output voltage. This algorithm results in a nearly
constant switching frequency despite the lack of a
fixed-frequency clock generator. The benefits of a con-
stant switching frequency are twofold: first, the frequency
can be selected to avoid noise-sensitive regions such
as the 455kHz IF band; second, the inductor ripple-cur-
rent operating point remains relatively constant, resulting
in easy design methodology and predictable output
voltage ripple.
On-Time = K (VOUT+ 0.075V) / VIN
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate the expect-
ed drop across the low-side MOSFET switch (Table 2).
The on-time one-shot has good accuracy at the operating
points specified in the Electrical Characteristics table
(±10% at 200kHz and 300kHz, ±12% at 550kHz and
1000kHz). On-times at operating points far removed from
the conditions specified in the Electrical Characteristics
table can vary over a wider range. For example, the
1000kHz setting will typically run about 10% slower with
inputs much greater than +5V due to the very short on-
times required.
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Character-
istics table are influenced by switching delays in the
Table 1. Component Suppliers
MANUFACTURERUSA PHONEFACTORY FAX

Central Semiconductor516-435-1110516-435-1824
Dale-Vishay402-564-3131402-563-6418
Fairchild408-721-2181408-721-1635
International Rectifier310-322-3331310-322-3332
Kemet408-986-0424408-986-1442
Motorola602-303-5454602-994-6430
Nihon847-843-7500847-843-2798
Panasonic714-373-7939714-373-7183
Taiyo Yuden408-573-4150408-573-4159
TDK847-390-4373847-390-4428
Toko800-745-8656408-943-9790
Sanyo619-661-6835619-661-1055
SGS-Thomson617-259-0300617-259-9442
Sumida708-956-0666708-956-0702
Zetex516-543-7100516-864-7630
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

REF
-10%
FROM
D/A
REF
REF
OVP
ZMODETIME
10k
ERROR
AMP
TOFF
TON
REF
+10%
NEG
R-2R
D/A CONVERTER
CHIP SUPPLYgm
POS
VGATED1D2D3S1SUSS0D4
ON-TIME
COMPUTE
TON
1-SHOT
1-SHOT
TRIG
VBATT
2V TO 28V
TRIG
REF
REF
GND
OUTPUT
VCC
VDD
ZERO CROSSING
CURRENT
LIMIT
BST
ILIM
REF
OVP/UVP
DETECT
SKP/SDN
TON
70kΩ
MAX1718
MUXES AND SLEW CONTROL1
Figure 2. Functional Diagram
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

external high-side MOSFET. Resistive losses, including
the inductor, both MOSFETs, output capacitor ESR, and
PC board copper losses in the output and ground tend
to raise the switching frequency at higher output cur-
rents. Also, the dead-time effect increases the effective
on-time, reducing the switching frequency. It occurs
only in PWM mode (SKP/SDN= open) and during
dynamic output voltage transitions when the inductor
current reverses at light or negative load currents. With
reversed inductorcurrent, the inductor’s EMF causes
LX to go high earlier than normal, extending the on-time
by a period equal to the DH-rising dead time.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switching
frequency is:
where VDROP1is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and tONis the on-time calculat-
ed by the MAX1718.
Integrator Amplifiers/Output
Voltage Offsets

Two transconductance integrator amplifiers provide a
fine adjustment to the output regulation point. One
amplifier forces the DC average of the feedback volt-
age to equal the VID DAC setting. The second amplifier
is used to create small positive or negative offsets from
the VID DAC setting, using the POS and NEG pins.
The integrator block has the ability to lower the output
voltage by 8% and raise it by 8%. For each amplifier,
the differential input voltage range is at least ±80mV
total, including DC offset and AC ripple. The two ampli-
fiers’ outputs are directly summed inside the chip, so
the integration time constant can be set easily with one
capacitor at the CC pin. Use a capacitor value of 47pF
to 1000pF (47pF typ). The gmof each amplifier is
160µmho (typ).
The POS/NEG amplifier is used to add small offsets to
the VID DAC setting or to correct for voltage drops. To
create an output offset, bias POS and NEG to a voltage
(typically VOUTor REF) within their common-mode
range, and offset them from one another with a resistive
divider (Figures 3 and 4). If VPOSis higher than VNEG,
then the output is shifted in the positive direction. If
VNEGis higher than VPOS, then the output is shifted in
the negative direction. The amount of output offset is
less than the difference from POS to NEG by a scale
factor that varies with the VID DAC setting as shown in
Table 3. The common-mode range of POS and NEG is
0.4V to 2.5V.
For applications that require multiple offsets, an exter-
nal multiplexer can be used to select various resistor
values (Figure 5).
Both the integrator amplifiers can be disabled by con-
necting NEG to VCC.
Forced-PWM Mode (SKP/SDNOpen)

The low-noise forced-PWM mode (SKP/SDNopen) dis-
ables the zero-crossing comparator, allowing the induc-
tor current to reverse at light loads. This causes the
low-side gate-drive waveform to become the comple-
ment of the high-side gate-drive waveform. The benefit
of forced-PWM mode is to keep the switching frequen-
cy fairly constant, but it comes at a cost: the no-load
battery current can be 10mA to 40mA, depending on
the external MOSFETs and switching frequency.
Forced-PWM mode is required during downward output
voltage transitions. The MAX1718 uses PWM mode dur-
ing all transitions, but only while the slew-rate controller
is active. Due to voltage positioning, when a transition
uses high negative inductor current, the output voltage
does not settle to its final intended value until well after
the slew-rate controller terminates. Because of this it is
possible, at very high negative slew currents, for the out-
put to end up high enough to cause VGATE to go low. VVVV
OUTDROPINDROPDROP=+ 1
Table 2. Approximate K-Factor Errors
MIN RECOMMENDED VBATT ATTON
SETTING
TON
FREQUENCY
(kHZ)
K-FACTOR
(µs)
APPROXIMATE K-
FACTOR ERROR (%)
VOUT = 1.25V (V)VOUT = 1.75V (V)

VCC2005±101.72.3
OPEN3003.3±101.82.5
REF5501.8±12.52.63.5
GND10001.0±12.53.64.9
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

Thus, it is necessary to use forced PWM mode during all
negative transitions. Most applications should use PWM
mode exclusively, although there is some benefit to
using skip mode while in the low-power suspend state
(see the Using Skip Mode During Suspend (SKP/SDN=
VCC) section.)
Automatic Pulse-Skipping Switchover

In skip mode (SKP/SDNhigh), an inherent automatic
switchover to PFM takes place at light loads (Figure 6).
This switchover is effected by a comparator that trun-
cates the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between con-
tinuous and discontinuous inductor-current operation.
The load-current level at which PFM/PWM crossover
occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak
ripple current, which is a function of the inductor value
(Figure 6). For a battery range of 7V to 24V, this thresh-
old is relatively constant, with only a minor dependence
on battery voltage:
where K is the on-time scale factor (Table 2). For exam-
ple, in the standard application circuit this becomes:
The crossover point occurs at a lower value if a swing-
ing (soft-saturation) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response, especially at low input voltage levels.
Current-Limit Circuit

The current-limit circuit employs a unique “valley” current-
sensing algorithm that uses the on-resistance of the
low-side MOSFET as a current-sensing element. If the
current-sense signal is above the current-limit thresh-
old, the PWM is not allowed to initiate a new cycle1256812527. .. . . μA××−=KVLOADSKIPOUTBATTOUT
BATT() ≈××−
REF
MAX1718
POS
NEG
Figure 3. Resistive Divider from REF
MAX1718
POS
NEG
Figure 4. Resistive Divider from OUTPUT
MAX1718
SEL
MUX
POS
NEG
MAX4524
Figure 5. Programmable Offset Voltage
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

(Figure 7). The actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit
characteristic and maximum load capability are a func-
tion of the MOSFET on-resistance, inductor value, and
battery voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the undervoltage protection circuit, this current-
limit method is effective in almost every circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUTis sinking
current. The negative current-limit threshold is set to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when ILIM is
adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. The current-limit threshold volt-
age adjustment range is from 50mV to 300mV. In the
adjustable mode, the current-limit threshold voltage is
precisely 1/10th the voltage seen at ILIM. The threshold
defaults to 100mV when ILIM is connected to VCC. The
logic threshold for switchover to the 100mV default
value is approximately VCC- 1V.
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). For a high-accuracy
current-limit application, see Figure 16.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the current-
sense signals seen by LX and GND. Place the IC close
to the low-side MOSFET with short, direct traces, mak-
ing a Kelvin sense connection to the source and drain
terminals.
MOSFET Gate Drivers (DH, DL)

The DH and DL drivers are optimized for driving mod-
erate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VBATT- VOUTdifferential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time cir-
cuit to work properly. Otherwise, the sense circuitry in the
MAX1718 will interpret the MOSFET gate as “off” while
there is actually still charge left on the gate. Use very
short, wide traces measuring 10 to 20 squares (50 to 100
mils wide if the MOSFET is 1 inch from the MAX1718).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typ) internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω(typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time
of the inductor node, due to capacitive coupling from
the drain to the gate of the low-side synchronous-rectifi-
er MOSFET. However, for high-current applications,you
might still encounter some combinations of high- and
low-side FETs that will cause excessive gate-drain cou-
pling, which can lead to efficiency-killing, EMI-
producing shoot-through currents. This is often remedied
by adding a resistor in series with BST, which increases
the turn-on time of the high-side FET without degrading
the turn-off time (Figure 8).
POR

Power-on reset (POR) occurs when VCCrises above
approximately 2V, resetting the fault latch and preparing
the PWM for operation. VCCundervoltage lockout
INDUCTOR CURRENT
ILOAD = IPEAK/2
ON-TIME0TIME
IPEAKL
VBATT - VOUT∆i=
Figure 6. Pulse-Skipping/Discontinuous Crossover Point
INDUCTOR CURRENT
ILIMIT
ILOADTIME
IPEAK
Figure 7. “Valley” Current-Limit Threshold Point
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)

(UVLO) circuitry inhibits switching, forces VGATE low,
and forces the DL gate driver high (to enforce output
overvoltage protection).When VCCrises above 4.2V, the
DAC inputs are sampled and the output voltage begins
to slew to the DAC setting.
For automatic startup, the battery voltage should be
present before VCC. If the MAX1718 attempts to bring
the output into regulation without the battery voltage
present, the fault latch will trip. The SKP/SDNpin can
be toggled to reset the fault latch.
Shutdown

When SKP/SDNgoes low, the MAX1718 enters low-
power shutdown mode. VGATE goes low immediately.
The output voltage ramps down to 0V in 25mV steps at
the clock rate set by RTIME. When the DAC reaches the
0V setting, DL goes high, DH goes low, the reference is
turned off, and the supply current drops to about 2µA.
When SKP/SDNgoes high or floats, the reference pow-
ers up, and after the reference UVLO is passed, the
DAC target is evaluated and switching begins. The
slew-rate controller ramps up from 0Vin 25mV steps to
the currently selected code value (based on ZMODE
and SUS). There is no traditional soft-start (variable cur-
rent limit) circuitry, so full output current is available
immediately. VGATE goes high after the slew-rate con-
troller has terminated and the output voltage is in regu-
lation.
UVLO

If VCCdrops low enough to trip the UVLO comparator, it
is assumed that there is not enough supplyvoltage to
make valid decisions. To protect the output from over-
voltage faults, DL is forced high in this mode. This will
force the output to GND, but it will not use the slew-rate
controller. This results in large negative inductor current
and possibly small negative output voltages. If VCC
likely to drop in this fashion, the outputcan be clamped
with a Schottky diode to GND to reduce the negative
excursion.
DAC Inputs D0–D4

The digital-to-analog converter (DAC) programs the
output voltage. It typically receives a preset digital code
from the CPU pins, which are either hard-wired to GND
or left open-circuit. They can also be driven by digital
logic, general-purpose I/O, or an external mux. Do not
leave D0–D4 floating—use 1MΩor less pullups if the
inputs may float. D0–D4 can be changed while the
SMPS is active, initiating a transition to a new output
voltage level. If this mode of DAC control is used, connect
ZMODE and SUS low. Change D0–D4 together, avoid-
ing greater than 1µs skew between bits. Otherwise,
incorrectDAC readings may cause a partial transition to
the wrong voltage level, followed by the intended transi-
tion to the correct voltage level, lengthening the overall
transition time. The available DAC codes and resulting
output voltages (Table 3) are compatible with IMVP-II
specification.
Internal Multiplexers (ZMODE, SUS)

The MAX1718 has two unique internal VID input multi-
plexers (muxes) that can select one of three different
VID DAC code settings for different processor states.
Depending on the logic level at SUS, the Suspend
(SUS) mode mux selects the VID DAC code settings
from either the ZMODE mux or the S0/S1 input decoder.
The ZMODE mux selects one of the two VID DAC code
settings from the D0–D4 pins, based on either voltage
on the pins or the output of the impedance decoder
(Figure 9).
When SUS is high, the Suspend mode mux selects the
VID DAC code settings from the S0/S1 input decoder.
The outputs of the decoder are determined by inputs
S0 and S1 (Table 4).
When SUS is low, the Suspend mode mux selects the
output of the ZMODE mux. Depending on the logic level
at ZMODE, the ZMODE mux selects the VID DAC code
settings using either the voltage on D0–D4 or the output
of the impedance decoder (Table 5).
If ZMODE is low, the logic-level voltages on D0–D4 set
the VID DAC settings. This is called Logic mode. In this
mode, the inputs are continuously active and can be
dynamically changed by external logic. The Logic
mode VID DAC code setting is typically used for the
Battery mode state, and the source of this code is
sometimes the VID pins of the CPU with suitable pullup
resistors.
BST
+5V
VBATT
5Ω TYP
MAX1718
Figure 8. Reducing the Switching-Node Rise Time
MAX1718
Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP-II)
Table 3. Output Voltage vs. DAC CodesD3D2D1D0OUTPUT
VOLTAGE (V)
POS/NEG SCALE
FACTOR
0001.750.900011.700.900101.650.900111.600.891001.550.891011.500.891101.450.881111.400.880001.350.880011.300.870101.250.870111.200.861001.150.861011.100.851101.050.851111.000.840000.9750.840010.9500.830100.9250.830110.9000.821000.8750.821010.8500.821100.8250.811110.8000.810000.7750.800010.7500.800100.7250.790110.7000.781000.6750.781010.6500.771100.6250.761110.6000.76
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