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MAX1586CETM+N/AN/a2500avaiHigh-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smartphones
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MAX1586CETM ,High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and SmartphonesFeaturesThe MAX1586/MAX1587 power-management ICs are ♦ Six Regulators in One Package®optimized for ..
MAX1586CETM+ ,High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smartphonesfeatures anadditional linear regulator (V6) for VCC_USIM and low-MAIN BATTERYIN MAX1586battery and ..
MAX1586CETM+T ,High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and SmartphonesApplicationsVCC_MEM 2.5VV2PDA, Palmtop, and Wireless HandheldsVCC_COREV30.8V TO 1.3VMRThird-Generat ..
MAX1586ETM ,0.3-6.0V; high-efficiency, low-Iq PMICs with dynamic core for PDAs and smart phones. For PDA, palmtop and wireless handhelds, 3-generation smart cell phones, internet appliances and web-booksFeaturesThe MAX1586/MAX1587 power-management ICs are ♦ Six Regulators in One Package:optimized for ..
MAX1587AETL ,High-Efficiency / Low-IQ PMICs with Dynamic Core for PDAs and Smart PhonesMAX1586A/MAX1586B/MAX1587A19-3089; Rev 0; 12/03High-Efficiency, Low-I PMICs withQDynamic Core for P ..
MAX1587AETL+ ,High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and SmartphonesELECTRICAL CHARACTERISTICS(V = 3.6V, V = 3.0V, V = 1.1V, V = 1.35V, circuit of Figure 5, T = 0°C to ..
MAX4252EBL+T ,UCSP, Single-Supply, Low-Noise, Low-Distortion, Rail-to-Rail Op AmpsFeatures! Available in Space-Saving UCSP, SOT23, andThe MAX4249–MAX4257 low-noise, low-distortion o ..
MAX4252ESA ,Dual, single-supply operation +2.4V to 5.5V, low-noise, low-distortion, Rail-to-Rail op amp. Gain bandwidth 3MHz, min stable gain 1V/V.features make the' Input Common-Mode Voltage Range Includesdevices an ideal choice for portable/bat ..
MAX4252ESA+ ,UCSP, Single-Supply, Low-Noise, Low-Distortion, Rail-to-Rail Op Ampsfeatures makeGroundthe devices an ideal choice for portable/battery-powered! Outputs Swing Within 8 ..
MAX4252EUA ,Dual, single-supply operation +2.4V to 5.5V, low-noise, low-distortion, Rail-to-Rail op amp. Gain bandwidth 3MHz, min stable gain 1V/V.MAX4249–MAX425719-1295; Rev 2; 4/98SOT23, Single-Supply, Low-Noise,Low-Distortion, Rail-to-Rail Op ..
MAX4252EUA ,Dual, single-supply operation +2.4V to 5.5V, low-noise, low-distortion, Rail-to-Rail op amp. Gain bandwidth 3MHz, min stable gain 1V/V.ELECTRICAL CHARACTERISTICS(V = +5V, V = 0V, V = 0V, V = V /2, R tied to V /2, SHDN = V or open, T = ..
MAX4252EUA+ ,UCSP, Single-Supply, Low-Noise, Low-Distortion, Rail-to-Rail Op AmpsEVALUATION KIT AVAILABLE MAX4249–MAX4257UCSP, Single-Supply, Low-Noise, Low-Distortion, Rail-to-Ra ..


MAX1586AETM+-MAX1586AETM+T-MAX1586BETM+-MAX1586BETM+T-MAX1586CETM-MAX1586CETM+-MAX1586CETM+T-MAX1587AETL+-MAX1587AETL+T-MAX1587CETL+-MAX1587CETL+T-MAX1587CETLT-MAX1587CETL-T
High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smartphones
General Description
The MAX1586/MAX1587 power-management ICs are
optimized for devices using Intel XScale®microproces-
sors, including Smart Phones, PDAs, internet appli-
ances, and other portable devices requiring substantial
computing and multimedia capability at low power.
The ICs integrate seven high-performance, low-operating-
current power supplies along with supervisory and
management functions. Included are three step-down
DC-DC outputs, three linear regulators, and a seventh
always-on output. DC-DC converters power I/O, DRAM,
and the CPU core. The I/O supply can be preset to
3.3V or adjusted to other values.The DRAM supply on
the A and C devices is preset for 1.8V or 2.5V, while the
MAX1586B DRAM supply is preset for 3.3V or 2.5V. The
DRAM supply on all parts can also be adjusted with
external resistors. The CPU core supply is serial pro-
grammed for dynamic voltage management and, on C
devices, can supply up to 0.9A. Linear-regulated out-
puts are provided for SRAM, PLL, and USIM supplies.
To minimize quiescent current, critical power supplies
have bypass “sleep” LDOs that can be activated when
output current is very low. Other functions include sep-
arate on/off control for all DC-DC converters, low-bat-
tery and dead-battery detection, a reset and power-OK
output, a backup-battery input, and a two-wire serial
interface.
All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre-
quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The core out-
put can be forced into PWM mode at all loads to mini-
mize noise.A 2.6V to 5.5V input voltage range allows
1-cell lithium-ion (Li+), 3-cell NiMH, or a regulated 5V
input. The MAX1587 is available in a tiny 6mm x 6mm,
40-pin thin QFN package. The MAX1586 features an
additional linear regulator (V6) for VCC_USIM and low-
battery and dead-battery comparators. The MAX1586 is
available in a 7mm x 7mm, 48-pin thin QFN package.
Applications

PDA, Palmtop, and Wireless Handhelds
Third-Generation Smart Cell Phones
Internet Appliances and Web-Books
Features
Six Regulators in One Package
Step-Down DC-DC for I/O at 1.3A
Step-Down DC-DC for Memory at 0.9A
Step-Down Serial-Programmed DC-DC for CORE
Up to 0.9A
Three LDO Outputs for SRAM, PLL, and USIM
Always-On Output for VCC_BATT
Low Operating Current
60µA in Sleep Mode (Sleep LDOs On)
130µA with DC-DCs On (Core Off)
200µA All Regulators On, No Load
5µA Shutdown Current
Optimized for XScale ProcessorsBackup-Battery Input1MHz PWM Switching Allows Small External
Components
Tiny 6mm x 6mm, 40-Pin and 7mm x 7mm, 48-Pin
Thin QFN Packages
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Ordering Information

MAX1586
MAX1587
VCC_IO 3.3V
VCC_MEM 2.5V
VCC_CORE
0.8V TO 1.3V
VCC_USIM
0V, 1.8V, 3.0V
MAIN BATTERY
VCC_PLL 1.3V
VCC_SRAM 1.1V
BACKUP
BATTERY
BKBT
RSO
VCC_BATT
POK
nRESET
nVCC_FAULT
SYS_EN
PWR_EN
ON1-2
ON3-6
nBATT_FAULTDBO
Simplified Functional Diagram

19-3089; Rev 4; 4/09
EVALUATION KIT
AVAILABLE
Pin Configurations and Selector Guide appear at end of
data sheet.
PARTTEMP RANGEPIN-PACKAGE
MAX1586AETM
-40°C to +85°C48 Thin QFN 7mm x 7mm
MAX1586BETM
-40°C to +85°C48 Thin QFN 7mm x 7mm
MAX1586CETM
-40°C to +85°C48 Thin QFN 7mm x 7mm
MAX1587AETL
-40°C to +85°C40 Thin QFN 6mm x 6mm
MAX1587CETL
-40°C to +85°C40 Thin QFN 6mm x 6mm
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, IN45, IN6, MR, LBO, DBO, RSO, POK, SCL, SDA,
BKBT, V7, SLP, SRAD, PWM3 to GND...............-0.3V to +6V
REF, CC_, ON_, FB_, DBI, LBI, V1, V2, RAMP, BYP,to GND ...........................................-0.3V to (VIN+ 0.3V)
PV1, PV2, PV3, SLPIN to IN...................................-0.3V to +0.3V
V4, V5 to GND..........................................-0.3V to (VIN45 + 0.3V)
V6 to GND..................................................-0.3V to (VIN6 + 0.3V)
PV1 to PG1............................................................-0.3V to +6.0V
PV2 to PG2............................................................-0.3V to +6.0V
PV3 to PG3............................................................-0.3V to +6.0V
LX1 Continuous Current....................................-1.30A to +1.30A
LX2 Continuous Current........................................-0.9A to +0.9A
LX3 Continuous Current........................................-0.9A to +0.9A
PG1, PG2, PG3 to GND.........................................-0.3V to +0.3V
V1, V2, V4, V5, V6 Output Short-Circuit Duration.......Continuous
Continuous Power Dissipation (TA = +70°C)
6mm x 6mm 40-Pin Thin QFN
(derate 26.3mW/°C above +70°C)...........................2105mW
7mm x 7mm 48-Pin Thin QFN
(derate 26.3mW/°C above +70°C)...........................2105mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally2.65.5V
IN45, IN6 Supply Voltage Range2.45.5V
VIN rising2.252.402.55IN Undervoltage-Lockout (UVLO)
ThresholdVIN falling2.2002.352.525V
MAX158632Only V7 on, VIN below
DBI threshold VIN = 3.0VMAX15875
MAX1586130REG1 and REG2 on in
switch mode, REG3 offMAX1587130
MAX158660REG1 and REG2 on in
sleep mode, REG3 offMAX158760
MAX1586225
Quiescent Current
No load (IPV1 +
IPV2 + IPV3 + IIN +
ISLPIN + IIN45 +
IIN6)
All REGs onMAX1587200
ON1 = 04BKBT Input CurrentON1 = IN0.8µA
REF Output Voltage0 to 10µA load1.23751.251.2625V
SYNCHRONOUS-BUCK PWM REG1

REG1 Voltage AccuracyFB1 = GND, 3.6V ≤ VPV1 ≤ 5.5V, load = 0 to 1300mA3.253.33.35V
FB1 Voltage AccuracyFB1 used with external resistors, 3.6V ≤ VPV1 ≤ 5.5V,
load = 0 to 1300mA1.2311.251.269V
FB1 Input CurrentFB1 used with external resistors100nA
Error-Amplifier TransconductanceReferred to FB87µS
Load = 800mA180280Dropout Voltage (Note 1)Load = 1300mA293450mV
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINTYPMAXUNITS

ILX1 = -180mA0.180.3p-Channel On-ResistanceILX1 = -180mA, VPV1 = 2.6V0.210.35Ω
ILX1 = 180mA0.130.225n-Channel On-ResistanceILX1 = 180mA, VPV1 = 2.6V0.150.25Ω
Current-Sense Transresistance0.5V/A
p-Channel Current-Limit Threshold-1.55-1.80-2.10A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
OUT1 Maximum Output Current2.6V ≤ VPV1 ≤ 5.5V (Note 3)1.3A
LX1 Leakage CurrentVPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V-20+0.1+20µA
SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA2.4632.52.537
MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.7731.81.827REG2 Voltage Accuracy
MAX1586B, FB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA3.253.33.35
FB2 Voltage AccuracyFB2 used with external resistors, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.2311.251.269V
FB2 Input CurrentFB2 used with external resistors, VFB2 = 1.25V100nA
Error-Amplifier TransconductanceReferred to FB87µS
Dropout VoltageLoad = 900mA (Note 1)243380mV
ILX2 = -180mA0.2250.375p-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.260.425Ω
ILX2 = 180mA0.150.25n-Channel On-ResistanceILX2 = 180mA, VPV2 = 2.6V0.170.275Ω
Current-Sense Transresistance0.7V/A
p-Channel Current-Limit Threshold-1.1-1.275-1.50A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
OUT2 Maximum Output Current2.6V ≤ VPV2 ≤ 5.5V (Note 3)0.9A
LX2 Leakage CurrentVPV2 = 5.5V, LX2 = GND or PV2, VON2 = 0V-10+0.1+10µA
SYNCHRONOUS-BUCK PWM REG3

MAX1586A, MAX1586B, MAX1587A,
load = 0 to 500mA-1.5+1.5
REG3 Output Voltage Accuracy
REG3 from 0.7V to
1.475V, 2.6V ≤
VPV3 ≤ 5.5VMAX1586C, MAX1587C,
load = 0 to 900mA-1.5+1.5
Error-Amplifier Transconductance68µS
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINTYPMAXUNITS

ILX3 = -180mA0.2250.375p-Channel On-ResistanceILX2 = -180mA, VPV3 = 2.6V0.260.425Ω
ILX3 = 180mA0.150.25n-Channel On-ResistanceILX3 = 180mA, VPV3 = 2.6V0.170.275Ω
MAX1586A, MAX1586B, MAX1587A1.1Current-Sense TransresistanceMAX1586C, MAX1587C0.55V/A
MAX1586A, MAX1586B, MAX1587A-0.60-0.7-0.85p-Channel Current-Limit ThresholdMAX1586C, MAX1587C-1.125-1.35-1.700A
PWM Skip-Mode Transition Load
CurrentDecreasing load current (Note 2)30mA
MAX1586A, MAX1586B, MAX1587A0.5OUT3 Maximum Output Current2.6V ≤ VPV3 ≤ 5.5V
(Note 3)MAX 1586C, MAX1587C0.9A
LX3 Leakage CurrentVPV3 = 5.5V, LX3 = GND or PV2, VON3 = 0V-10+0.1+10µA
LDOS V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current35mA
V7 Output Current30mA
REG4 Output VoltageLoad = 0.1mA to 35mA1.2611.31.339V
REG4 NoiseWith 1µF COUT and 0.01µF CBYP15µVRMS
REG5 Output VoltageLoad = 0.1mA to 35mA1.0671.11.133V
IN45, IN6 Input Voltage Range2.45.5V
0V setti ng ( ei ther ON 6 l ow or ser i al p r og r am m ed ) 0
1.8V setting, load = 0.1mA to 35mA1.7461.81.854
2.5V setting, load = 0.1mA to 35mA2.4252.52.575
REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)MAX1586
3.0V setting, load = 0.1mA to 35mA2.913.03.09
V1 on and in regulationVV1V7 Output VoltageV1 offVBKBTV
V1 and V2 SLEEP Output Voltage
AccuracySet to same output voltage as REG1 and REG2-3.0+3.0%
V1 and V2 SLEEP Dropout VoltageLOAD = 20mA75150mV
V6 Dropout VoltageM AX 1586 3V m od e, l oad = 30m A, 2.5V m od e, l oad = 30m A110200mV
V7 Switch Voltage DropLOAD = 20mA, VBKBT = VV1 = 3.0V100200mV
V4, V5, V6 Output Current Limit 40 90 mA
BKBT Leakage 1 µA
OSCILLATOR

PWM Switching Frequency0.9311.07MHz
SUPERVISORY/MANAGEMENT FUNCTIONS

Rising9294.7597POK Trip Threshold (Note 4)Falling88.590.592.5%
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINTYPMAXUNITS

LBI = IN (for preset)3.513.63.69LBI Threshold (Falling)MAX1586 hysteresis is
5% (typ)With resistors at LBI0.981.001.02V
DBI = IN (for preset)3.0243.153.276DBI Threshold (Falling)MAX1586 hysteresis is
5% (typ)With resistors at LBI1.2081.2321.256V
RSO Threshold (Falling)Voltage on REG7, hysteresis is 5% (typ)2.252.412.56V
RSO Deassert Delay6165.570ms
LBI Input Bias CurrentMAX1586-50-5nA
DBI Input Bias CurrentMAX15861550nA
Thermal-Shutdown TemperatureTJ rising+160°C
Thermal-Shutdown Hysteresis15°C
LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level2.6V ≤ V7 ≤ 5.5V, sinking 1mA0.4V
LBO, DBO, POK, RSO Output Low
LevelV7 = 1V, sinking 100µA0.4V
LBO, DBO, POK, RSO Output-High
Leakage CurrentPin = 5.5V0.2µA
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level2.6V ≤ VIN ≤ 5.5V1.6V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level2.6V ≤ VIN ≤ 5.5V0.4V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage CurrentPin = GND, 5.5V-1+1µA
SERIAL INTERFACE

Clock Frequency400kHz
Bus-Free Time Between START and
STOP1.3µsol d Ti m e Rep eated S TART C ond i ti on0.6µs
CLK Low Period1.3µs
CLK High Period0.6µsetup Ti m e Rep eated S TART C ond i ti on0.6µs
DATA Hold Time0µs
DATA Setup Time100ns
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input
Filter of Both DATA and CLK Signalsns
Setup Time for STOP Condition0.6µs
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = 0°C to +85°C,unless otherwise noted. Typical values
are at TA= +25°C.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINMAXUNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range
PV1, PV2, PV3, IN, and SLPIN must connect together
externally2.65.5V
IN45, IN6 Supply Voltage Range2.45.5V
VIN rising2.252.55IN Undervoltage-Lockout (UVLO)
ThresholdVIN falling2.2002.525V
SYNCHRONOUS-BUCK PWM REG1

FB1 = GND, 3.6V ≤ VPV1 ≤ 5.5V, load = 0 to 1300mA3.253.35REG1 Voltage AccuracyFB1 = IN, 3.6V ≤ VPV1 ≤ 5.5V, load = 0 to 1300mA2.9553.045V
FB1 Voltage AccuracyFB1 used with external resistors, 3.6V ≤ VPV1 ≤ 5.5V,
load = 0 to 1300mA1.2311.269V
FB1 Input CurrentFB1 used with external resistors100nA
Load = 800mA (Note 1)280Dropout VoltageLoad = 1300mA (Note 1)450mV
ILX1 = -180mA0.3p-Channel On-ResistanceILX1 = -180mA, VPV1 = 2.6V0.35Ω
ILX1 = 180mA0.225n-Channel On-ResistanceILX1 = 180mA, VPV1 = 2.6V0.25Ω
p-Channel Current-Limit Threshold-1.55-2.10A
OUT1 Maximum Output Current2.6V ≤ VPV1 ≤ 5.5V (Note 3)1.30A
LX1 Leakage CurrentVPV1 = 5.5V, LX1 = GND or PV1, VON1 = 0V-10+10µA
SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ VPV2 ≤ 5.5V, load = 0 to 900mA2.4632.537
MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.7731.827REG2 Voltage Accuracy
MAX1586B, FB2 = IN, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA3.253.35
FB2 Voltage AccuracyFB2 used with external resistors, 3.6V ≤ VPV2 ≤ 5.5V,
load = 0 to 900mA1.2311.269V
FB2 Input CurrentFB2 used with external resistors, VFB2 = 1.25V100nA
Dropout VoltageLoad = 900mA (Note 1)380mV
ILX2 = -180mA0.375p-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.425Ω
ILX2 = -180mA0.25n-Channel On-ResistanceILX2 = -180mA, VPV2 = 2.6V0.275Ω
p-Channel Current-Limit Threshold-1.1-1.50A
OUT2 Maximum Output Current2.6V ≤ VPV2 ≤ 5.5V (Note 3)0.9A
LX2 Leakage CurrentVPV2 = 5.5V, LX2 = GND or PV2, VON2 = 0V-10+10µA
ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINMAXUNITS
SYNCHRONOUS-BUCK PWM REG3

MAX1586A, MAX1586B, MAX1587A,
load = 0 to 500mA-1.5+1.5
REG3 Output Voltage Accuracy
REG3 from 0.7V to
1.475V, 2.6V ≤
VPV3 ≤ 5.5VMAX1586C, MAX1587C,
load = 0 to 900mA-1.5+1.5
ILX3 = -180mA0.375p-Channel On-ResistanceILX2 = -180mA, VPV3 = 2.6V0.425Ω
ILX3 = 180mA0.25n-Channel On-ResistanceILX3 = 180mA, VPV3 = 2.6V0.275Ω
MAX1586A, MAX1586B, MAX1587A-0.60-0.85p-Channel Current-Limit ThresholdMAX1586C, MAX1587C-1.125-1.700A
MAX1586A, MAX1586B, MAX1587A0.5OUT3 Maximum Output Current2.6V ≤ VPV3 ≤ 5.5V
(Note 3)MAX1586C, MAX1587C0.9A
LX3 Leakage CurrentVPV3 = 5.5V, LX3 = GND or PV2, VON3 = 0V-10+10µA
LDOs V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current35mA
V7 Output Current30mA
REG4 Output VoltageLoad = 0.1mA to 35mA1.2541.346V
REG5 Output VoltageLoad = 0.1mA to 35mA1.0611.139V
IN45, IN6 Input Voltage Range2.45.5V
1.8V setting, load = 0.1mA to 35mA1.7371.863
2.5V setting, load = 0.1mA to 35mA2.4122.588REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)MAX1586
3.0V setting, load = 0.1mA to 35mA2.8953.105
V1 and V2 SLEEP Output Voltage
AccuracySet to same output voltage as REG1 and REG2-3.5+3.5%
V1 and V2 SLEEP Dropout VoltageLoad = 20mA150mV
V6 Dropout VoltageM AX 1586 3V m od e, l oad = 30m A; 2.5V m od e, l oad = 30m A200mV
V7 Switch Voltage DropLoad = 20mA, VBKBT = VV1 = 3.0V200mV
V4, V5, V6 Output Current Limit 40 mA
BKBT Leakage 1 µA
OSCILLATOR

PWM Switching Frequency0.931.07MHz
SUPERVISORY/MANAGEMENT FUNCTIONS

Rising9297POK Trip Threshold (Note 4)Falling88.592.5%
LBI = IN (for preset)3.513.69LBI Threshold (Falling)MAX1586,
hysteresis is 5% (typ)With resistors at LBI0.981.02V
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
PARAMETERCONDITIONSMINMAXUNITS

DBI = IN (for preset)2.9933.307DBI Threshold (Falling)MAX1586,
hysteresis is 5% (typ)With resistors at LBI1.2081.256V
RSO Threshold (Falling)Voltage on REG7, hysteresis is 5% (typ)2.252.60V
RSO Deassert Delay6269ms
LBI Input Bias CurrentMAX1586-50nA
DBI Input Bias CurrentMAX158675nA
LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level2.6V ≤ V7 ≤ 5.5V, sinking 1mA0.4V
LBO, DBO, POK, RSO, SDA Output
Low LevelV7 = 1V, sinking 100µA0.4V
LBO, DBO, POK, RSO Output-High
Leakage CurrentPin = 5.5V0.2µA
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level2.6V ≤ VIN ≤ 5.5V1.6V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level2.6V ≤ VIN ≤ 5.5V0.4V
ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage CurrentPin = GND, 5.5V-1+1µA
SERIAL INTERFACE

Clock Frequency400kHz
Bus-Free Time Between START and
STOP1.3µs
Hold Time Repeated START
Condition0.6µs
CLK Low Period1.3µs
CLK High Period0.6µs
Setup Time Repeated START
Condition0.6µs
DATA Hold Time0µs
DATA Setup Time100ns
Setup Time for STOP Condition0.6µs
ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C,unless otherwise noted.) (Note 5)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Note 1:
Dropout voltage is guaranteed by the p-channel switch resistance and assumes a maximum inductor resistance of 45mΩ.
Note 2:
The PWM-skip-mode transition has approximately 10mA of hysteresis.
Note 3:
The maximum output current is guaranteed by the following equation:
where:
and RN = n-channel synchronous rectifier RDS(ON)
RP = p-channel power switch RDS(ON)
RL = external inductor ESR
IOUT(MAX) = maximum required load current
f = operating frequency minimum
L = external inductor value
ILIMcan be substituted for IOUT(MAX) (desired) when solving for D. This assumes that the inductor ripple current is
small relative to the absolute value.
Note 4:
POK only indicates the status of supplies that are enabled (except V7). When a supply is turned off, POK does not trigger
low. When a supply is turned on, POK immediately goes low until that supply reaches regulation. POK is forced low when all
supplies (except V7) are disabled.
Note 5:
Specifications to -40°C are guaranteed by design, not production tested.VIRRRR
OUTOUTMAXNLOUTMAXNP=++−VDxLDOUTMAX
LIMOUT()=−+−12xfxL
ELECTRICAL CHARACTERISTICS (continued)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Typical Operating Characteristics

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
0.1110100100010,000
REG1 3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT

MAX1586A/86B/87A toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG2 2.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1586A/86B/87A toc02
LOAD CURRENT (mA)
EFFICIENCY (%)VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG3 1.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1586A/86B/87A toc03
LOAD CURRENT (mA)
EFFICIENCY (%)VIN = 3.6V
VIN = 4.0VVIN = 5.0V
REG3 1.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
MAX1586A/86B/87A toc03B
LOAD CURRENT (mA)
EFFICIENCY (%)VIN = 3.6V
VIN = 4.0V
VIN = 5.0V
L3 = 4.7μH
C17 = 44μFMAX1586C
MAX1587C
REG3 1.3V OUTPUT WITH FORCED-PWM
EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc04B
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 5.0V
VIN = 4.0V
L3 = 4.7μH
C17 = 44μF
MAX1586C
MAX1587C
REG3 1.3V OUTPUT WITH FORCED-PWM
EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc04
LOAD CURRENT (mA)
EFFICIENCY (%)
VIN = 3.6V
VIN = 5.0V
VIN = 4.0V
REG1 SLEEP LDO 3.3V OUTPUT
EFFICIENCY vs. LOAD CURRENT
MAX1586A/86B/87A toc05
EFFICIENCY (%)
VIN = 3.6V
VIN = 4.0V
VIN = 5.0V
REG2 SLEEP LDO 2.5V OUTPUT
EFFICIENCY vs. LOAD CURRENT

MAX1586A/86B/87A toc06
EFFICIENCY (%)
VIN = 3.6VVIN = 4.0V
VIN = 5.0V
QUIESCENT CURRENT
vs. SUPPLY VOLTAGE
MAX1586A/86B/87A toc07
INPUT CURRENT (
BKBT BIASED AT 3.6V
V1, V2, AND V3 ON
V1 AND V2 ON
V1 ON
V1 AND V2 SLEEP
V1 SLEEP
ALL BUT V7 OFF
120
DROPOUT VOLTAGE
vs. LOAD CURRENT
MAX1586A/86B/87A toc08
LOAD CURRENT (mA)
DROPOUT VOLTAGE (mV)
REG1 3.3V OUTPUT
CHANGE IN OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1586A/86B/87A toc09
LOAD CURRENT (mA)
CHANGE IN OUTPUT VOLTAGE (mV)
VIN = 3.6V
REG1 3.3V OUTPUT
REG3 1.3V OUTPUT
REG2 2.5V OUTPUT
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
MAX1586A/86B/87A toc10
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
TA = -40°C
TA = +85°C
TA = +25°C
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1586A/86B/87A toc11
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
REG1 SWITCHING WAVEFORMS
WITH 800mA LOAD

MAX1586A/86B/87A toc12
400ns/div
500mA/div
10mv/div
AC-COUPLED
2V/div
VLX1
IL1
REG1 SWITCHING WAVEFORMS
WITH 10mA LOAD

MAX1586A/86B/87A toc13
20μs/div
500mA/div
50mv/div
AC-COUPLED
2V/div
VLX1
IL1
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Typical Operating Characteristics (continued)

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
REG3 SWITCHING WAVEFORMS
WITH 250mA LOAD

MAX1586A/86B/87A toc14
400ns/div
500mA/div
10mv/div
AC-COUPLED
2V/div
IL3
VLX3
REG3 PULSE-SKIP SWITCHING
WAVEFORMS WITH 10mA LOAD

MAX1586A/86B/87A toc15
10μs/div
500mA/div
10mv/div
AC-COUPLED
2V/divVLX3
IL3
REG3 FORCED-PWM SWITCHING
WAVEFORMS WITH 10mA LOAD

MAX1586A/86B/87A toc16
400ns/div
0mA
500mA/div
10mv/div
AC-COUPLED
2V/div
VLX3
IL3
V7 AND RSO
STARTUP WAVEFORMS

MAX1586A/86B/87A toc17
10ms/div
2V/div
2V/div
2V/div
RSO
VIN
SYS_EN STARTUP WAVEFORMS

MAX1586A/86B/87A toc18
2ms/div
2V/div
2V/div
2V/div
2V/div
VEN1
AND
VEN2
VPOK
PWR_EN STARTUP WAVEFORMS

MAX1586A/86B/87A toc19
1ms/div
2V/div
2V/div
2V/div
2V/div
2V/div
VEN3
AND
VEN45
VPOK
Typical Operating Characteristics (continued)

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
REG1 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc20
200μs/div
100mV/div
AC-COUPLED
ILOAD1
200mA/div
REG2 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc21
200μs/div
100mV/div
AC-COUPLED
ILOAD2
200mA/div
REG3 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc22
200μs/div
100mV/div
AC-COUPLED
ILOAD3
200mA/div
REG3 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc22B
100μs/div
850mA
50mA
100mV/div
ILOAD3
500mA/div
MAX1586C
MAX1587C
REG3 OUTPUT VOLTAGE CHANGING FROM
1.3V TO 1.0V WITH DIFFERENT VALUES OF CRAMP

MAX1586A/86B/87A toc23
200μs/div
CRAMP = 2200pF
CRAMP = 1500pF
CRAMP = 1000pF
CRAMP = 330pF
REG6 USIM TRANSITIONS

MAX1586A/86B/87A toc24
10μs/div
500mV/divV6
2.5V TO 3.0V
1.8V TO 2.5V
0 TO 1.8V
Typical Operating Characteristics (continued)

(Circuit of Figure 6, VIN = 3.6V, TA = +25°C, unless otherwise noted.)
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Pin Description
PIN
MAX
MAX
NAMEFUNCTION
—LBI
Dual Mode™, Low-Battery Input. Connect to IN to set the low-battery threshold to 3.6V (no resistors
needed). Connect LBI to a resistor-divider for an adjustable LBI threshold. When VIN is below the set
threshold, LBO output switches low. LBO is deactivated and forced low when VIN is below the dead-battery
(DBI) threshold and when all REGs are disabled.40CC1REG1 Compensation Node. Connect a series resistor and capacitor from CC1 to GND to compensate the
regulation loop. See the Compensation and Stability section.FB1REG1 Feedback Input. Connect FB1 to GND to set V1 to 3.3V. Connect FB1 to external feedback resistors
for other output voltages.BKBTInput Connection for Backup Battery. This input can also accept the output of an external boost converter.V7
Also known as VCC_BATT. V7 is always active if main or backup power is present. It is the first regulator
that powers up. V7 has two states:
1) V7 tracks V1 if ON1 is high and V1 is in regulation.
2) V7 tracks VBKBT when ON1 is low or V1 is out of regulation.V1REG1 Voltage-Sense Input. Connect directly to the REG1 output voltage. The output voltage is set by FB1
to either 3.3V or adjustable with resistors.SLPINInp ut to V 1 and V 2 S l eep Reg ul ator s. The i np ut to the stand b y r eg ul ator s at V 1 and V 2. C onnect S LP IN to IN .V2REG2 Voltage-Sense Input. Connect directly to the REG2 output voltage. The output voltage is set by FB2
to either 1.8V/2.5V (MAX1586A, MAX1587A), 3.3V/2.5V (MAX1586B), or adjustable with resistors.FB2
REG2 Feedback Input. Connect to GND to set V2 to 2.5V on all devices. Connect FB2 to IN to set V2 to
1.8V on the MAX1586A and MAX1587A. Connect FB2 to IN to set V2 to 3.3V on the MAX1586B. Connect
FB2 to external feedback resistors for other voltages.8CC2REG2 Compensation Node. Connect a series resistor and capacitor from CC2 to GND to compensate the
regulation loop. See the Compensation and Stability section.9 POK
Power-OK Output. Open-drain output that is low when any of the V1–V6 outputs are below their regulation
threshold. When all activated outputs are in regulation, POK is high impedance. POK maintains a valid low
output with V7 as low as 1V. POK does not flag an out-of-regulation condition while REG3 is transitioning
between voltages set by serial programming. POK also does not flag for any REG channel that has been
turned off; however, if all REG channels are off (V1–V6), then POK is forced low. If VIN < VUVLO, then POK is
low. POK is expected to connect to nVCC_FAULT.10SCLSerial Clock Input11SDA
Serial Data Input. Data is read on the rising edge of SCL. Serial data programs the REG3 (core) and REG6
(VCC_USIM) voltage. REG3 and REG6 can be programmed even when off, but at least one of the ON_ pins
must be logic-high to activate the serial interface. On power-up, REG3 defaults to 1.3V and REG6 defaults
to 0V.12PWM3Force V3 to PWM at All Loads. Connect PWM3 to GND for normal operation (skip mode at light loads). Drive
or connect high for forced-PWM operation at all loads for V3 only.—LBOLow-Battery Output. Open-drain output that goes low when VIN is below the threshold set by LBI.
High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones
Pin Description (continued)
PIN
MAX
MAX
NAMEFUNCTION
13PV2REG2 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.14LX2REG2 Switching Node. Connects to REG2 inductor.15PG2REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.16INMain Battery Input. This input provides power to the IC.17RAMPV3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100kΩ. FB3 regulates to 1.28 x VRAMP.18GNDAnalog Ground19REFReference Output. Output of the 1.25V reference. Bypass to GND with a 0.1µF or greater capacitor.20BYPLow-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01µF capacitor from BYP to GND.—DBO
Dead or Missing Battery Output. DBO is an open-drain output that goes low when VIN is below the
threshold set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is
expected to connect to nBATT_FAULT on Intel CPUs.21ON2
On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 are connected to SYS_EN.—ON4
On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON4 is connected to PWR_EN.23V4Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.24IN45Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to VIN.25V5Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.—ON5
On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5
output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other
inputs. It is expected that ON5 is connected to PWR_EN.26PG3REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close as possible to the IC.27LX3REG3 Switching Node. Connects to the REG3 inductor.28PV3REG3 Power Input. Bypass to PG3 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.34ON3
On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.
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