MAX147BCAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0; f = ..
MAX147BCAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsMAX146/MAX14719-0465; Rev 2; 10/01+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs
MAX147BCPP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsMAX146/MAX14719-0465; Rev 1; 6/97+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs_______________
MAX147BCPP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsMAX146/MAX14719-0465; Rev 2; 10/01+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs
MAX147BEAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsApplications+3VPortable Data Logging Data AcquisitionVCH0 V DDDD 0.1μFMedical Instruments Battery- ..
MAX147BEAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsMAX146/MAX14719-0465; Rev 1; 6/97+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs_______________
MAX4053CSE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 2; 10/05Low-Voltage, CMOS AnalogMultiplexers/Switches
MAX4053EEE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX4053EEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4053EPE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 0; 1/96Low-Voltage, CMOS AnalogMultiplexers/Switches___ ..
MAX4053EPE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesApplications♦ Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment♦ Low Crosstalk: < -90dB (50Ω ..
MAX4053ESE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 0; 1/96Low-Voltage, CMOS AnalogMultiplexers/Switches___ ..
MAX146AEAP+-MAX146BCAP+-MAX146BEAP+-MAX147BCAP+-MAX147BCPP+-MAX147BEAP+-MAX147BEAP+T
+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs
General DescriptionThe MAX146/MAX147 12-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX146 oper-
ates from a single +2.7V to +3.6V supply; the MAX147
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The
MAX146/MAX147 use either the internal clock or an exter-
nal serial-interface clock to perform successive-approxi-
mation analog-to-digital conversions.
The MAX146 has an internal 2.5V reference, while the
MAX147 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX146/MAX147, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX146/MAX147 are available in 20-pin DIP and
SSOP packages.
For 4-channel versions of these devices, see the
MAX1246/MAX1247 data sheet.
________________________ApplicationsPortable Data LoggingData Acquisition
Medical InstrumentsBattery-Powered Instruments
Pen DigitizersProcess Control
____________________________Features8-Channel Single-Ended or 4-Channel
Differential InputsSingle-Supply Operation
+2.7V to +3.6V (MAX146)
+2.7V to +5.25V (MAX147)Internal 2.5V Reference (MAX146)Low Power
1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsVDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
AGND
DGND
VDD
CH7
4.7μF
0.1μFCH0
0V TO+2.5VANALOGINPUTSMAX146
CPU
+3V
VREF
0.047μF
REFADJ
ypical Operating Circuit19-0465; Rev 2; 10/01
PART
MAX146ACPPMAX146BCPP
MAX146ACAP0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGEPIN-PACKAGE20 Plastic DIP
20 Plastic DIP
20 SSOP
EVALUATION KIT
AVAILABLE
Ordering Information
Ordering Information continued at end of data sheet.*Dice are specified at TA= +25°C, DC parameters only.
MAX146BCAP0°C to +70°C20 SSOP
INL
(LSB)±1/2
±1/2
SPI and QSPI are registered trademarks of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor
Corp.
Pin Configuration appears at end of data sheet.MAX146BC/D0°C to +70°CDice*±1
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND.................................................-0.3V to 6V
AGND to DGND......................................................-0.3V to 0.3V
CH0–CH7, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF, REFADJ to AGND...........................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................................-0.3V to 6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX146_C_P/MAX147_C_P..............................0°C to +70°C
MAX146_E_P/MAX147_E_P............................-40°C to +85°C
MAX146_MJP/MAX147_MJP........................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Relative Accuracy (Note 2)3565tCONVConversion Time (Note 5)
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth-85Channel-to-Channel Crosstalk90
LSB±0.25Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits12Resolution
LSBGain Error (Note 3)±0.5±4
Offset Error
±1.0LSB
±2.0
INL
±0.5±3LSB±0.5±4
UNITSMINTYPMAXSYMBOLPARAMETERExternal clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN= VDD
Internal clock, SHDN= FLOAT
MAX14_A
-3dB rolloff
65kHz, 2.500Vp-p(Note 4)
MAX14_A/MAX14_B
MAX14_A/MAX14_B
MAX14_B
MAX147C
MAX14_A
MAX14_B/MAX147C
CONDITIONS±1.0MAX14_A/MAX14_BDifferential NonlinearityLSB±0.8DNLMAX147C
No Missing CodesBits12NMC73SINADSignal-to-Noise + Distortion RatioMAX147C-88THDTotal Harmonic DistortionUp to the 5th
harmonic
MAX14_A/MAX14_B
MAX147C90SFDRSpurious-Free Dynamic RangeMAX147C
DC ACCURACY(Note 1)
DYNAMICSPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)
CONDITIONSPARAMETERSYMBOLMINTYPMAXUNITS1.5tACQTrack/Hold Acquisition Time
MHz
SHDN= FLOATMHz
Aperture Delay
Internal Clock FrequencySHDN= VDD2.0External Clock Frequency Data transfer only<50Aperture Jitter
On/off leakage current, VCH_= 0V or VDD
Bipolar, COM = VREF / 2
Unipolar, COM = 0V
±0.01±1µA
Input Voltage Range, Single-
Ended and Differential (Note 6)±VREF / 20 to VREF
Multiplexer Leakage Current
REFADJ Adjustment Range±1.5%
Capacitive Bypass at REFADJ0.047µF
External compensation modeCapacitive Bypass at VREF4.7µFInternal compensation mode0
0 to 0.2mA output loadLoad Regulation (Note 7)0.35mV
MAX146_M
VREF Temperature Coefficient
±30±80
ppm/°CMAX146_E±30±60
MAX146_C±30±50
VREF Short-Circuit Current30mA= +25°CVREF Output Voltage2.4802.5002.520V
Input Capacitance16pF
VREF Input Voltage Range
(Note 8)1.0VDD+
50mVV
External compensation mode
MAX146
Reference Buffer Gain2.06V/V
Internal compensation modeCapacitive Bypass at VREF0µF
REFADJ Buffer Disable ThresholdVDD-
0.5V
VREF = 2.5VVREF Input Current100150µA
VREF Input Resistance1825kΩ
Shutdown VREF Input Current0.0110µA
MAX147
MAX146
MAX147REFADJ Input Current
±50
±10µA
ANALOG/COM INPUTS
INTERNAL REFERENCE (MAX146 only, reference buffer enabled)
EXTERNALREFERENCE AT VREF (Buffer disabled)
EXTERNALREFERENCE AT REFADJ
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)3.0VIH
VDD= 3.6V
DIN, SCLK, CSInput High VoltageVDD> 3.6V, MAX147 only±0.3PSRSupply Rejection (Note 10)Full-scale input, external reference = 2.5V,
VDD= 2.7V to VDD(MAX)15CINDIN, SCLK, CSInput Capacitance±0.01±1IINDIN, SCLK, CSInput Leakage0.2VHYSTDIN, SCLK, CSInput Hysteresis0.8VILDIN, SCLK, CSInput Low Voltage
2.0±4.0ISSHDNInput Current0.4VSLSHDNInput Low VoltageVDD- 0.4VSHSHDNInput High Voltage
SHDN= 0VorVDD±100SHDNMaximum Allowed
Leakage, Mid InputVDD / 2VFLTSHDNVoltage, Floating
SHDN= FLOAT
SHDN= FLOAT
UNITSMINTYPMAXSYMBOLPARAMETER(Note 9)
VIN= 0V or VDD
VDD ≤3.6V
IDD
CONDITIONSPositive Supply Current, MAX146µA
1.22.0±0.01±10ILThree-State Leakage CurrentVDD- 0.5VOHOutput Voltage High0.8VOLOutput Voltage Low0.4
2.703.6015COUTThree-State Output Capacitance
MAX146= VDD(Note 9)= VDD
ISOURCE= 0.5mA
ISINK= 16mA
ISINK= 5mA2.705.25VDDPositive Supply VoltageMAX147
Operating mode,
full-scale input
VDD= 5.25V
VDD= 3.6V
2.115VDD= 5.25V
VDD= 3.6V1.210Full power-down1.82.570
Operating mode, full-scale input
Fast power-down
Full power-down1.1VDD- 1.1VSMSHDNInput Mid Voltage
IDDPositive Supply Current, MAX147
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS(DOUT, SSTRB)
POWERREQUIREMENTSIDDPositive Supply Current, MAX147µA
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsFigure 1
Typical Operating Characteristics(VDD= 3.0V, VREF = 2.5V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. CODE
MAX146/47-01
CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
VDD (V)
INL (LSB)
MAX146/47-02
MAX146
MAX147
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
INL (LSB)
MAX146/47-03
MAX147
MAX146
VDD = 2.7V
TIMING CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); TA= TMINto TMAX; unless otherwise noted.)
Note 1:Tested at VDD= 2.7V; COM = 0; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.5V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Guaranteed by design. Not subject to production testing.
Note10:Measured as |VFS(2.7V) - VFS(VDD, MAX)|.
Internal clock mode only (Note 9)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX14_ _C/E
CONDITIONSMAX14_ _Mns20240Figure 1
tCSH240tSTRCSRise to SSTRBOutput Disable240tSDVCSFall to SSTRBOutput Enable
240tSSTRBSCLKFall to SSTRBns
200tCLSCLK Pulse Width Low200SCLK Pulse Width High0CSto SCLK Rise Hold100tCSSCSto SCLK Rise Setup240tTRCSRise to Output Disable240tDVCSFall to Output Enable
tCH200tDOSCLK Fall to Output Data Valid0tDHDIN to SCLK Hold1.5tACQAcquisition TimetSCKSSTRB Rise to SCLK Rise100tDS
UNITSMINTYPMAXSYMBOLPARAMETER
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsSUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX146/47-04
RL = ∞
CODE = 101010100000CLOAD = 50pF
MAX147
MAX146
CLOAD = 20pF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VDD (V)
SHUTDOWN SUPPLY CURRENT (
MAX146/47-05FULL POWER-DOWN
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
VDD (V)
VREF (V)
MAX146/47-06
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX146/47-07
MAX147
MAX146
RLOAD = ∞
CODE = 10101010000010203040506070
FFT PLOTAMPLITUDE (dB)
MAX146/47-10VDD = 2.7V
fIN = 10kHz
fSAMPLE = 133kHz
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
SHUTDOWN CURRENT (
MAX1247-08
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
VREF (V)
MAX146/47-09
VDD = 2.7V
VDD = 3.6V
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
MAX146/47-11
ENOB
VDD = 2.7V
Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsOFFSET vs. SUPPLY VOLTAGE
VDD (V)
OFFSET (LSB)
MAX146/47-12
GAIN ERROR
vs. SUPPLY VOLTAGE
VDD (V)
GAIN ERROR (LSB)
MAX146/47-13
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
GAIN MATCHING (LSB)
MAX146/47-14
OFFSET vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET (LSB)-57014512095
MAX146/47-15
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
OFFSET MATCHING (LSB)
MAX146/47-18
GAIN ERROR
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN ERROR (LSB)451201459570
MAX146/47-16
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN MATCHING (LSB)451451209570
MAX146/47-17
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)-57014512095
MAX146/47-19
Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.5V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
NAMEFUNCTION1–8CH0–CH7Sampling Analog Inputs
PINCOMGround reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.SHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX146/MAX147 down; otherwise, they are
fully operational. Pulling SHDNhigh puts the reference-buffer amplifier in internal compensation mode.
Letting SHDNfloat puts the reference-buffer amplifier in external compensation mode.DOUTSerial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CSis high.DGNDDigital GroundAGNDAnalog GroundVREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX146 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.SCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)CSActive-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT is
high impedance.DINSerial Data Input. Data is clocked in at SCLK’s rising edge.SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX146/MAX147 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CSis high (external clock
mode).
______________________________________________________________Pin DescriptionVDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOL
VDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) VOH to High-Zb) VOL to High-Z
Figure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable TimeREFADJInput to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.VDDPositive Supply Voltage
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________Detailed DescriptionThe MAX146/MAX147 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX146/
MAX147.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN-(the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a 16pF x [(VIN+) -
(VIN-)] charge from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
INPUT
SHIFT
REGISTERCONTROL
LOGIC
INTCLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX146)
T/HANALOG
INPUTMUX
12-BIT
SARADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20kΩ
*A ≈ 2.00 (MAX147)
CH67
CH78
CH45
CH56
CH12
CH23
CH34
CH01
MAX146
MAX147
SHDN
≈ 2.06*A
Figure 3.Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
9kΩ
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsThe time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ= 9 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5µs. Note
that source impedances below 1kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand AGND, allow the channel input pins to swing
from AGND -0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
Quick LookTo quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
0.1μF
2.5V
+3V
VDD
DGND
AGND
COM
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01μF
CH7
REFADJ
VREF
0.1μF
0V TO
2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1CH2CH3CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX146
MAX147
+3V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
COMP
1000pF
VOUT
+3V
MAX872
OPTIONAL FOR MAX146,
REQUIRED FOR MAX147
Figure 5. Quick-Look Circuit
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
BITNAMEDESCRIPTION7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
5 SEL1SEL0UNI/BIP1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.SGL/DIF1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode0Full power-down1Fast power-down (MAX146 only)0Internal clock mode1 External clock mode
Table 1.Control-Byte Format
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
Table 2.Channel Selection in Single-Ended Mode (SGL/DIF= 1)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7COM0+–
0+–
1+–
1+–
0+–
0+–
1+–
1+ –
Table 3.Channel Selection in Differential Mode (SGL/DIF= 0)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH70+–
1+–
0+–
1+–
0–+
1–+
0–+
1–+
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsSSTRB
SCLK
DIN
DOUT812162024
START
SEL2SEL1SEL0UNI/
BIPSGL/
DIFPD1PD0
B11
MSBB10B9B8B7B6B5B4B3B2B1B0
LSB
ACQUISITION
(fSCLK = 2MHz)
IDLE
FILLED WITH ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1RB2RB3
1.5μs
Figure 6.24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK≤2MHz)
How to Start a ConversionStart a conversion by clocking a control byte into DIN.
With CSlow, each rising edge on SCLK clocks a bit from
DIN into the MAX146/MAX147’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX146/MAX147 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time.Using the Typical Operating
Circuit,the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
20 for MAX146/MAX147 QSPI connections.
Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is two’s
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock ModesThe MAX146/MAX147 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX146/MAX147. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
