MAX1459AAP+ ,2-Wire, 4-20mA Smart Signal ConditionerFeaturesThe MAX1459 highly integrated analog-sensor signal♦ Highly Integrated Sensor Signal Conditi ..
MAX145ACUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXApplications MAX144ACPA 0°C to +70°C 8 Plastic DIP ±0.5MAX144BCPA 0°C to +70°C 8 Plastic DI ..
MAX145ACUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXapplications, or for other circuits withINLdemanding power-consumption and space require-PART TEMP. ..
MAX145AEUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXFeaturesThe MAX144/MAX145 low-power, 12-bit analog-to-' Single-Supply Operation (+2.7V to +5.25V)di ..
MAX14634EWC+T ,Ultra-Low On-Resistance and Compact Bidirectional Battery SwitchesApplicationsrefer to www.maximintegrated.com/MAX14634.related.Tablet PC Battery SwitchesSmartphone ..
MAX14640ETA+ ,USB Host Adapter EmulatorsApplicationsthe dedicated charging port (DCP) charging while in the ● Laptop/Desktop Computersstand ..
MAX4052ACSE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4052AEEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesApplications♦ Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment♦ Low Crosstalk: < -90dB (50Ω ..
MAX4052AESE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4052AESE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesApplications♦ Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment♦ Low Crosstalk: < -90dB (50Ω ..
MAX4052AESE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 2; 10/05Low-Voltage, CMOS AnalogMultiplexers/Switches
MAX4052CEE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesFeaturesThe MAX4051/MAX4052/MAX4053 and MAX4051A/' Pin Compatible with Industry-Standard MAX4052A/M ..
MAX1459AAP+
2-Wire, 4-20mA Smart Signal Conditioner
General DescriptionThe MAX1459 highly integrated analog-sensor signal
conditioner is optimized for piezoresistive sensor calibra-
tion and compensation with minimal external compo-
nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit DACs.
Achieving a total error factor within 1% of the sensor’s
repeatability errors, the MAX1459 compensates offset,
offset temperature coefficient (offset TC), full-span output
(FSO), FSO temperature coefficient (FSOTC), and FSO
nonlinearity of silicon piezoresistive sensors.
The MAX1459 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal through digital-to-analog converters
(DACs), thereby eliminating quantization noise.
The MAX1459 allows temperature compensation via the
external sensor, an internal temperature-dependent
resistor, or a dedicated external temperature transduc-
er. Accuracies better than 0.5% can be achieved with
low-cost external temperature sensors (i.e., silicon tran-
sistor), depending on sensor choice.
Built-in testability features on the MAX1459 result in the
integration of three traditional sensor-manufacturing
operations into one automated process:
Pretest:Data acquisition of sensor performance
under the control of a host test computer.
Calibration and compensation:Computation and
storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1459.
Final test operation:Verification of transducer cali-
bration and compensation without removal from the
pretest socket.
Although optimized for use with piezoresistive sensors,
the MAX1459 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.
________________________Applications4–20mA Transmitters
Piezoresistive Pressure and Acceleration
Industrial Pressure Sensors
Load Cells/Wheatstone Bridges
Strain Gauges
Temperature Sensors
FeaturesHighly Integrated Sensor Signal Conditioner for
2-Wire, 4–20mA TransmittersSensor Errors Trimmed Using Correction
Coefficients Stored in Internal EEPROM—
Eliminates the Need for Laser Trimming and
PotentiometersCompensates Offset, Offset TC, FSO, FSOTC,
FSO LinearityProgrammable Current Source (0.1mA to 2.0mA)
for Sensor ExcitationFast Signal-Path Settling Time (≈1ms)Accepts Sensor Outputs from +1mV/V to +40mV/V Fully Analog Signal PathInternal or External Temperature Reference
CompensationAutomated Pilot Production (Calibration/
Compensation) System AvailableWrite Protection for EEPROM Data Security
Pin Configuration
Ordering Information
MAX1459
2-Wire, 4–20mA
Smart Signal ConditionerSCLKVDD
NBIAS
CK50
TEMP2
TEMP1
INM
INP
BDRIVE
TOP VIEW
MAX1459
SSOPDIO
AMP+
FSOTC
AMP-
AMPOUT
VSS
OUT
TEMPIN
ISRC
19-1619; Rev 0; 1/00
*Dice are tested at TA= +25°C, DC parameters only.
Functional Diagram appears at end of data sheet.
EVALUATION KIT AVAILABLE20 SSOP
Dice*
20 SSOP
PIN-PACKAGETEMP. RANGE0°C to +70°C
0°C to +70°C
-40°C to +125°CMAX1459AAP
MAX1459C/D
MAX1459CAP
PART
For custom versions of the MAX1459, see the Customization
section at end of data sheet.
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VDDto VSS......................................-0.3V to +6V
All Other Pins...................................(VSS- 0.3V) to (VDD+ 0.3V)
Short-Circuit Duration, FSOTC, OUT, BDRIVE...........Continuous
Continuous Power Dissipation (TA= +70°C)
20-Pin SSOP (derate 8.00mW/°C above +70°C)..........640mW
Operating Temperature Ranges
MAX1459CAP......................................................0°C to +70°C
MAX1459AAP.................................................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLMINTYPMAXUNITSAmplifier Gain Nonlinearity0.01%VDD
Input-Referred Offset Tempco±0.5µV/°C
Input ImpedanceRIN1MΩ
Output Step Response2ms
Common-Mode Rejection RatioCMRR90dB
Input-Referred Adjustable Offset
Range±150mV
Supply VoltageVDD4.55.05.5V
Supply CurrentIDD2.02.5mA
Input-Referred Adjustable Full-
Span Output (FSO) Range+1 to +40mV/V
Differential Signal Gain Range+41 to +230V/V
Minimum Differential Signal Gain+36+41+44V/V
Differential Signal Gain Tempco±50ppm/°C
Output Current Range-0.45 0.45
(sink)(source)mA
Output Noise500µVRMS
CONDITIONS(Note 5)
(Notes 2, 3)
63% of final value
Selectable in eight steps= TMINto TMAX
From VSSto VDD
At minimum gain (Note 4)= TMINto TMAX
VOUT= (VSS+ 0.25V) to (VDD- 0.25V)
DC to 10Hz (gain = 41,
source impedance = 5kΩ)
RNBIAS= 402kΩ, VDD= 5.0V (Note 1)
Output Voltage SwingVSS + 0.05VDD- 0.05VNo load
VSS + 0.25VDD- 0.2510kΩload
GENERAL CHARACTERISTICS
ANALOG INPUT (PGA)
ANALOG OUTPUT (PGA)Bridge Current RangeIBDRIVE0.10.52.0mA
Bridge Voltage SwingVBDRIVEVSS + 1.3VDD- 1.3VIBDRIVE= 2mA
Reference Input Voltage Range
(ISRC)VISRCVSS + 1.3VDD- 1.3V
CURRENT SOURCE
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
MAX1459
2-Wire, 4–20mA
Smart Signal ConditionerFSO DAC Bit WeightΔVISRCΔCode1.22mV/bit
FSOTC DAC Bit WeightΔVFSOTΔCode0.6mV/bit
DAC reference = VDD= 5.0V
DAC reference = VBDRIVE= 2.5V
Offset DAC Bit WeightΔVOUTΔCode2.8mV/bit
Offset TC DAC Bit WeightΔVOUTΔCode1.4mV/bit
DAC reference = VDD= 5.0V
DAC reference = VBDRIVE= 2.5V
DAC Resolution12Bits
Differential NonlinearityDNL±1.5LSB
PARAMETERSYMBOLMINTYPMAXUNITSDAC Bit Weight9mV/bit
DAC Resolution3Bits
Output Voltage Swing0.24.0V
Current Drive-2020µA
Current Source Reference
ResistorRISRC100kΩ
FSO Trim ResistorRFTC100kΩ
Temperature-Dependent
ResistorRTEMP100kΩ
CONDITIONSInput referred, VDD= 5V (Note 6)
No load, VB= 5V
VFSOTC= 2.5V
Input Common-Mode RangeCMRVSSVDDV
Open-Loop GainAV60dB
Offset Voltage (as unity-gain
follower)-3030mVVIN= VDD/2
Output SwingVSS+ 0.05VDD - 0.05VNo load
Output Current±1mA
DIGITAL-TO-ANALOG CONVERTERS
IRO DAC
FSOTC BUFFER (FSOTC Pin)
INTERNAL RESISTORS
AUXILIARY OP AMP
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
__________________________________________Typical Operating Characteristics(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX1459 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VOUT = 2.47V AT +25°C
RTEMP vs. TEMPERATURE
MAX1459 toc02
TEMPERATURE (°C)
TEMP
VOUT vs. TEMPERATURE
MAX1459 toc03
TEMPERATURE (°C)
OUT
(V)
VOUT = 2.5V AT +25°C
VIN = 56.5mV
VOUT = 2.47V AT +25°C
VIN = 0
Note 1:Excludes the sensor or load current.
Note 2:All electronics temperature errors are compensated together with sensor errors.
Note 3:The sensor and the MAX1459 must always be at the same temperature during calibration and use.
Note 4:This is the maximum allowable sensor offset.
Note 5:This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge
voltage of 2.5V. Sensors smaller than +10mV/V require an auxiliary op amp.
Note 6:Bit weight is ratiometric to VDD.
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
ISINK= 2mAV0.5VOLLow-Level Output Voltage
ISOURCE= 1mAV4VOHHigh-Level Output Voltage2Input Hysteresis0.25 x VDDVILLow-Level Input Voltage0.75 x VDDVIHHigh-Level Input Voltage
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
DIGITAL PINS
MAX1459
2-Wire, 4–20mA
Smart Signal ConditionerTemperature Sensor Terminal 1TEMP116
Temperature Sensor Terminal 2. RTEMPis a 100kΩtemperature-dependent resistor with 4600ppm/°C
tempco.TEMP217
Output Voltage. OUT is a Rail-to-Rail®output that can drive resistive loads down to 10kΩand capacitive
loads up to 0.1µF.OUT11
Negative Power Supply VSS12
Sensor Excitation Current Output. The current source that drives the bridge.BDRIVE13
Positive Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.INP14
Negative Sensor Input. Input impedance is typically 1MΩ. Rail-to-rail input range.INM15
Auxiliary Op Amp Negative InputAMP-7
Auxiliary Op Amp OutputAMPOUT8
Input pin for an External Temperature-Dependent Reference Voltage for FSOTC DAC and OTC DAC. In the
default mode, the MAX1459 uses the temperature-dependent bridge drive voltage as the FSOTC DAC and
OTC DAC reference.
TEMPIN9
Current Source Reference. An internal 100kΩresistor (RISRC) connects ISRC to VSS(see Functional
Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISRC.ISRC10
Auxiliary Op Amp Positive InputAMP+6
Buffered Full-Span Output Temperature Coefficient DAC Output. An internal 100kΩresistor (RFTC) con-
nects FSOTC to ISRC (see Functional Diagram). Optionally, external resistors can be used in place of or in
parallel with RFTCand RISC.
FSOTC5
Write Enable, Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set
the DAC refresh-rate mode. Internally pulled to VDDwith a 1MΩ(typ) resistor. See the Chip-Select (CS)
and Write-Enable (WE)section.4
Data Input/Output. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ(typical)
resistor. High impedance when CS is low. DIO3
Positive Power-Supply Input. Connect a 0.1µF capacitor from VDDto VSS.VDD20
Clock Output, nominally 50kHzCK5018
Chip Current Bias Source. Connect an external 402kΩ±1% resistor between VDDand NBIAS.NBIAS19
Pin DescriptionChip-Select Input. The MAX1459 is selected when this pin is high. When low, OUT and DIO become high
impedance. Internally pulled to VDDwith a 1MΩ(typical) resistor. Leave unconnected for normal operation.CS2
Data Clock Input. Used only during programming/testing. Internally pulled to VSSwith a 1MΩ(typical) resistor.
Data is clocked in on the rising edge of the clock. Recommended SCLKfrequency is below 50kHz.SCLK
PINFUNCTIONNAMERail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
MAX1459
_______________Detailed DescriptionThe MAX1459 provides an analog amplification path for
the sensor signal and a digital path for calibration and
temperature correction. Calibration and correction is
achieved by varying the offset and gain of a program-
mable-gain amplifier (PGA) and by varying the sensor
bridge current. The PGA utilizes a switched-capacitor
CMOS technology, with an input-referred offset trim-
ming range of ±63mV (9mV steps). An additional out-
put-referred fine offset trim is provided by the offset
DAC (approximately 2.8mV steps). The PGA provides
eight gain values from +41V/V to +230V/V. The bridge
current source is programmable from 0.1mA to 2mA.
The MAX1459 uses four 12-bit DACs with calibration
coefficients stored by the user in an internal 128-bit
EEPROM. This memory contains the following informa-
tion as 12-bit-wide words:Configuration registerOffset calibration coefficientOffset temperature error compensation coefficientFull-span output (FSO) calibration coefficientFSO temperature error compensation coefficient24 user-defined bits for customer programming of
manufacturing data (e.g., serial number and date)
Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and FSO values as a func-
tion of voltage.
FSOTC CompensationSilicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(VBDRIVE) increases with temperature. This depen-
dence of VBDRIVEon the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi-
tivity tempco (TCS) so that, with constant voltage exci-
tation, FSO will decrease with temperature, causing a
full-span output temperature coefficient (FSOTC) error.
However, if the bridge voltage can be made to increase
with temperature at the same rate that TCS decreases
with temperature, the FSO will remain constant.
FSOTC compensation is accomplished by resistor
RFTCand the FSOTC DAC, which modulate the excita-
tion reference current at ISRC as a function of tempera-
ture (Figure 2). FSO DAC sets VISRCand remains
constant with temperature while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
VBDRIVE, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSOTC errors are
compensated and FSO will be constant with tempera-
ture.
OFFSET TC CompensationCompensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
what percentage of the temperature-dependent voltage
VBDRIVEmust be added to the output summing junction
to correct the error. Use the offset TC DAC to adjust the
amount of BDRIVE voltage that is added to the output
summing junction (Figure 3).
Analog Signal PathThe fully differential analog signal path consists of four
stages:Front-end summing junction for coarse offset correction3-bit PGA with eight selectable gains ranging from
41 through 230Three-input-channel summing junctionDifferential to single-ended output buffer with rail-to-
rail output (Figure 3)
Coarse Offset CorrectionThe sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR > 90dB, an input impedance of approxi-
mately 1MΩ, and a common-mode input voltage range
from VSSto VDD. At this summing junction, a coarse off-
set-correction voltage is added, and the resultant volt-
2-Wire, 4–20mA
Smart Signal ConditionerVOLTAGE (V)
PRESSURE
PMINPMAX
FULL-SCALE (FS)
FULL-SPAN OUTPUT (FSO)
OFFSET
Figure 1. Typical Pressure-Sensor Output
age is fed into the PGA. The 3-bit (plus sign) input-
referred offset DAC (IRO DAC) generates the coarse
offset-correction voltage. The DAC voltage reference is
1.25% of VDD; thus, a VDDof 5V results in a front-end
offset-correction voltage ranging from -63mV to +63mV,
in 9mV steps (Table 1). To add an offset to the input
signal, set the IRO sign bit high; to subtract an offset
from the input signal, set the IRO sign bit low. The IRO
DAC bits (C2, C1, C0, and IRO sign bit) are pro-
grammed in the configuration register (see Internal
EEPROM section).
Programmable-Gain AmplifierThe programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing JunctionThe third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset sign
bit and offset TC sign bit are stored in the configuration
register. The offset sign bit determines whether the off-
set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the off-
set TC sign bit. Alternately, positive offset TC errors dic-
tate a logic low for the offset TC sign bit. The output of
the summing junction is fed to the output buffer.
MAX1459
2-Wire, 4–20mA
Smart Signal ConditionerFigure 2. Bridge Excitation Circuit
VDD
AA ≈ 12IISRC = IBDRIVEI = IISRC
ISRC
FSOTC
RISRC
BDRIVE
VDD
RFTC
EXTERNAL
SENSOR
FSO
DAC
FSOTC
DAC
SOTC
BDRIVE1.25% VDD
SOFF
INP
INMA0
PGAΣΣA = 1OUT
A = 2.3
A = 2.3
OFFTC
DACIRO
DAC
VDD
OFFSET
DAC
Figure 3. Signal-Path Block Diagram
MAX1459
Output BufferThe output buffer (OUT) can swing within 50mV of the
supply rails with no load, or within 0.25V of either rail
while driving a 10kΩload. OUT can easily drive 0.1µF
of capacitance. The output is current limited and can
be shorted to either VDDor VSSindefinitely. If CS is
brought low, OUT goes high impedance, resulting in
typical output impedance of 1MΩ. This feature allows
parallel MAX1459 connections, reducing test system
wire harness complexity.
Bridge DriveFine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 2). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor RISRCand by the voltage at node ISRC (con-
trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA ≅
12) and then made available at BDRIVE for sensor exci-
tation. Modulation of this current with respect to tem-
perature can be used to correct FSOTC errors, while
modulation with respect to the output voltage (VOUT)
can be used to correct FSO linearity errors.
Voltage Drive SensorFor sensors with negligible FSOTC, the MAX1459 can
be configured as a fixed-voltage drive by shorting ISRC
and BDRIVE. Offset TC can then be compensated with
RTEMP. Set configuration register bit 5 to 1, and con-
nect TEMPIN to a temperature-dependent voltage
source. This source can easily be generated by induc-
ing a current through RTEMP. For more information on
this application, refer to the MAX1459 Reference Man-
ual.
Digital-to-Analog ConvertersThe four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
The FSO DAC takes its reference from VDDand con-
trols VISRC, which sets the baseline sensor excitation
current. The FSO DAC is used for fine adjustments to
the FSO. The offset DAC also takes its reference from
VDDand provides a 1.22mV resolution with a VDDof
5V. The output of the offset DAC is fed into the output
summing junction where it is gained by approximately
2.3, which increases the resulting output-referred off-
set-correction resolution to 2.8mV.
Both the offset TC and FSOTC DACs take their refer-
ences from a temperature-dependent voltage. In
default mode, this voltage is internally connected to
BDRIVE. Alternatively, a different temperature sensor
can be used through TEMPIN by setting bit 5 of the
configuration register. This temperature sensor can be
either RTEMPor an external temperature resistor.
2-Wire, 4–20mA
Smart Signal ConditionerOUTPUT-
REFERRED IRO
DAC STEP SIZE
(VDD= 5V) (V)
PGA
GAIN
(+V/+V)
PGA
VALUEA0A200
Table 2. PGA Gain Settings and IRO DAC
Step Size0
-18-0.360100-2-0.181000-1000-0+0.181001+1
+18+0.360101+2
+27+0.541101+3
+36+0.720011+4
+45+0.901011+5
+54+1.080111+6
VALUEC0C2C1SIGN+63
OFFSET
CORREC-
TION AT
VDD = 5V
(mV)+1.25
OFFSET
CORREC-
TION
PERCENT
OF VDD
(%)
IRO DAC11+7
Table 1. Input-Referred Offset DAC
Correction Values
The offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via RFTCto correct FSOTC errors.
Internal ResistorsThe MAX1459 contains three internal resistors (RISRC,
RFTC, and RTEMP) optimized for common silicon PRTs.
RISRC(in conjunction with the FSO DAC) programs the
nominal sensor excitation current. RFTC(in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both RISRCand RFTChave a nominal value of 100kΩ. If
external resistors are used, RISRCand RFTCcan be
disabled by setting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
RTEMPis a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100kΩat
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor. The
two RTEMP terminals are available as pin 16 and pin 17
of the MAX1459.
Internal EEPROMThe MAX1459 has a 128-bit internal EEPROM arranged
as eight 16-bit registers. The 4 uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4): Configuration register (Table 3) 12-bit calibration coefficients for the offset and FSO
DACs12-bit compensation coefficients for the offset TC
and FSOTC DACsTwo general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
The EEPROM is bit addressable. Program the EEPROM
using the following steps, where the bits have address-
es from 0 to 127 (07F hex):Read the entire EEPROM, and temporarily store the
reserved bits.Erase the entire EEPROM, which causes all bits to
be 0 (see the ERASE EEPROM Commandsection).Program 1 to the required bits, including the reserved
bits (see the WRITE EEPROM BIT Commandsection).Read the whole EEPROM, either with the READ EEP-
ROM BIT or with the READ EEPROM MATRIX com-
mands (see the READ EEPROM BIT Command and
READ EEPROM MATRIX Commandsections).
Configuration RegisterThe configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (RFTCand
RISRC).
DAC RegistersThe offset, offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
Detailed Description of the Digital Lines
Chip-Select (CS) and Write-Enable (WE)CS is used to enable OUT, control serial communica-
tion, and force an update of the configuration and DAC
registers:A low on CS disables serial communication and
places OUT in a high-impedance state.A transition from low to high on CS forces an update
of the configuration and DAC registers from the
MAX1459
2-Wire, 4–20mA
Smart Signal Conditioner
Table 3. Configuration Register
Description1256
BIT
EEPROM
ADDRESS (hex)10
Offset TC Sign Bit, SOTC
Offset Sign Bit, SOFF
PGA Gain (LSB), A0
PGA Gain, A1
PGA Gain (MSB), A2
Temperature Sensor Selection Bit
(0 = default VBDRIVE)
Reserved “0”
RISRC/RFTCSelection Bit
(0 = enable internal), IRS
IRO LSB, C0
IRO, C1
IRO MSB, C2
IRO Sign, SIRO
DESCRIPTION
CONFIGURATION REGISTER
MAX1459EEPROM when the U bit of the INITsequence is
zero.A transition from high to low on CS terminates pro-
gramming mode.A logic high on CS enables OUT and serial commu-
nication (seeCommunication Protocol section).
WE controls the refresh rate for the internal configura-
tion and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.A low on WE disables the erase/write operations and
also disables register refreshing from the EEPROM.A high on WE selects a refresh rate of approximately
400 times per second and enables EEPROM
erase/write operations.It is recommended that WE be connected to VSS
after the MAX1459 EEPROM has been programmed.
SCLK (Serial Clock)SCLK must be driven externally and is used to input
commands to the MAX1459 or program the internal
EEPROM contents. Input data on DIO is latched on the
rising edge of SCLK.
2-Wire, 4–20mA
Smart Signal Conditioner
Table 4. EEPROM Memory Map
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
Reserved
EE Address
Contents
EE Address
Contents0D080B090604070502
Configuration011D181B191614171512
MSBOffsetLSB112D282B292624272522
MSBOffset TCLSB213D383B393634373532
MSBFSOLSB314D484B494644474542
MSBFSOTCLSB416D686B696664676562
User-Defined Bits617D787B797674777572
User-Defined Bits71
Note:The MAX1459 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
= Reserved Bits535055575456595B585A5F
Reserved
Data Input/OutputThe DIO line is an input/output pin used to issue com-
mands to the MAX1459 (input mode) or read the
EEPROM contents (output mode).
In input mode (the default mode), data on DIO is
latched on each rising edge of SCLK. Therefore, data
on DIO must be stable at the rising edge of SCLK and
should transition on the falling edge of SCLK.
DIO will switch to output mode after receiving either the
READ EEPROM command or the READ EEPROM
MATRIX command. See the Read EEPROMsection for
detailed information.
Communication ProtocolTo initiate communication, the first 8 bits on DIO after
CS transitions from low to high mustbe 101010U0 (AA
hex or A8 hex, defined as the INIT sequence). The
MAX1459 will then begin accepting 16-bit control
words (Figure 4).
If the INIT SEQUENCE is not detected, all subsequent
data on DIO is ignored until CS again transitions from
low to high and the correct INIT SEQUENCE is received.
The U bit of the INIT SEQUENCE controls the updating
of the DACs and configuration register from the internal
EEPROM. If this bit is low (U = 0, INIT SEQUENCE = A8
hex), all four internal DACs and the configuration regis-
ter will be updated from the EEPROM on the next rising
edge of CS (this is also the default on power-up). If the
U bit is high (INIT SEQUENCE = AA hex), the DACs
and configuration register will not be updated from the
internal EEPROM; they will retain their current value on
any subsequent CS rising edge. The MAX1459 contin-
ues to accept control words until CS is brought low.
Control WordsAfter receiving the INIT SEQUENCE on DIO, the
MAX1459 begins latching in 16-bit control words, MSB
first (Figure 5).
The first 4 bits of the control word (the MSBs,
CM3–CM0) are the command field. The last 12 bits
(D11–D0) represent the data field. The MAX1459 sup-
ports the commands listed in Table 5.
No-OP Command (0 hex)The no-operation (No-OP) command must be issued
before and after the commands ERASE EEPROM and
WRITE EEPROM BIT. In the case of the ERASE EEP-
ROM command, the control word must be 0000 hex. In
the case of the WRITE EEPROM BIT command, the
command field must be 0h, and the data field must
have, in its lower bits, the EEPROM address to be writ-
ten (Figure 6). For example, to write location 1C hex of
MAX1459
2-Wire, 4–20mA
Smart Signal ConditionerFigure 5. Control-Word Timing Diagram
SCLK
DIO
COMMAND
MSBLSBLSBMSB
MSBLSB
DATA
16-BIT CONTROL WORDD6D8D5D7D4D3D2D1D0CM3CM0CM2D11CM1D10
Figure 4. Communication Sequence
SCLK
DIO
tMIN = 1.5ms16 CLK
CYCLES
INIT
SEQUENCECONTROL
WORD
CONTROL
WORD
CONTROL
WORDS
16 CLK
CYCLES
n x 16 CLK
CYCLES101CM3CM3CM2CM2DODO0U010
8 CLK
CYCLES
MAX1459the EEPROM (one of the reserved bits), the necessary
commands are:
001C hex:No-OP command, with address 1C hex
in the data field
201C hex:WRITE EEPROM BIT command, with
address 1C hex in the data field
001C hex:No-OP command, with address 1C hex
in the data field
ERASE EEPROM Command (1 hex)When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic 0. The data field of the 16-bit word is ignored
(Figure 7).
Important: An internal charge pump develops voltagesgreater than 20V for EEPROM programming operations.
The EEPROM control logic requires 10ms to erase the
EEPROM. After sending a write or erase command, fail-
ure to wait 10ms before issuing another command may
result in unreliable EEPROM operation. The maximum
number of EEPROM ERASE cycles should not ex-
ceed 100.
WRITE EEPROM BIT Command (2 hex)The WRITE EEPROM BIT command stores a logic high
at the memory location specified by the lower 7 bits of
the data field (D6–D0). The higher bits of the data field
(D11–D7) are ignored (Figure 8). Note that to write to
the internal EEPROM, WE and CS must be high. In
2-Wire, 4–20mA
Smart Signal ConditionerLOAD REGISTER11Fh11
READ EEPROM MATRIX11Eh10
CONTROL OUTPUT MUX10Dh11
WRITE Data to FSOTC DAC10Ch10
No-OP000h00
ERASE EEPROM001h01
WRITE EEPROM BIT012h00
READ EEPROM BIT013h01
MAXIM RESERVED104h00
MAXIM RESERVED105h01
MAXIM RESERVED116h00
MAXIM RESERVED117h01
WRITE Data to
Configuration Register008h10
WRITE Data to Offset DAC009h11
WRITE Data to Offset-TC
DAC01Ah10
WRITE Data to FSO DAC01Bh11
FUNCTIONCM2CM1HEX
CODECM3CM0Figure 7. ERASE EEPROM Command Timing Diagram
SCLK
DIO
COMMAND
MSBLSBLSBMSB
MSBLSB
DATA
16-BIT CONTROL WORD - ERASE EEPROM COMMAND (1XXX HEX)XXXXXXXXX010X0X
Figure 6. No-OP Command Timing Diagram
SCLK
DIO
COMMAND
MSBLSBLSBMSB
MSBLSB
DATA
16-BIT CONTROL WORD - NO-OP COMMAND (OOXX HEX)A60A50A4A3A2A1A0000000
Table 5. MAX1459 Commands
