MAX144AEUA+T ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAXApplications0°C toMAX144BCUA 8 µMAX ±1 U8-1+70°CBattery-Powered Systems Instrumentation 0°C toMAX14 ..
MAX144BCPA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXMAX144/MAX14519-1387; Rev 0; 11/98+2.7V, Low-Power, 2-Channel, 108ksps,Serial 12-Bit ADCs in 8-Pin ..
MAX144BCUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXApplications MAX144ACPA 0°C to +70°C 8 Plastic DIP ±0.5MAX144BCPA 0°C to +70°C 8 Plastic DI ..
MAX144BEUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V, V = 2.5V, 0.1µF capacitor at REF, f = 2.17MHz, 16 c ..
MAX1450EAP ,Low-Cost, 1%-Accurate Signal Conditioner for Piezoresistive SensorsApplicationsPiezoresistive Pressure and AccelerationRail-to-Rail is a registered trademark of Nippo ..
MAX14510EEVB+T ,USB 2.0 Hi-Speed and Audio Switches with Negative Signal CapabilityApplicationsUTQFNCell PhonesMP3 Players7 6AOR 8 5 VCCNotebook ComputersMAX14510E/VB 9 4 GNDMAX14511 ..
MAX4042EUA+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsFeaturesThe MAX4040–MAX4044 family of micropower op amps♦ Single-Supply Operation Down to +2.4Voper ..
MAX4043ESD ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsMAX4040–MAX404419-1377; Rev 0; 5/98Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O O ..
MAX4043EUB ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsFeaturesThe MAX4040–MAX4044 family of micropower op amps' Single-Supply Operation Down to +2.4Voper ..
MAX4044ESD ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsGeneral Description ________
MAX404CPA ,Video Operational AmplifierELECTRICAL CHARACTERISTICS (continued)
(V+ : +5\/, V- = -5V, -3V < VIN < +3V, RL = 1000, CL = 15pF ..
MAX404CSA ,Video Operational AmplifierELECTRICAL CHARACTERISTICS
(V+ = +5\/, V- = -5V, -3V < VIN < +3V, RL --100Q,CL :15pF,unless otherw ..
MAX144ACPA+-MAX144AEUA+-MAX144AEUA+T
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX
General DescriptionThe MAX144/MAX145 low-power, 12-bit analog-to-
digital converters (ADCs) are available in 8-pin µMAX®
and DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD= +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the automatic shutdown (0.2µA) further
reduces power consumption.
The MAX144 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX145 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data-
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™-compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 10-bit ADCs, see the
MAX157 and MAX159 data sheets.
Applications
FeaturesSingle-Supply Operation (+2.7V to +5.25V) Two Single-Ended Channels (MAX144) One
Pseudo-Differential Channel (MAX145) Low Power
0.9mA (108ksps, +3V Supply)
100µA (10ksps, +3V Supply)
10µA (1ksps, +3V Supply)
0.2µA (Power-Down Mode)Internal Track/Hold 108ksps Sampling Rate SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial
Interface Space-Saving 8-Pin µMAX Package Pin-Compatible 10-Bit Versions Available
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
PART TEMP
RANGE
PIN-
PACKAGE INL
(LSB) PKG
CODE
MAX144ACUA0°C to
+70°C8 µMAX±0.5U8-1
MAX144BCUA0°C to
+70°C8 µMAX±1U8-1
MAX144ACPA0°C to
+70°C8 Plastic DIP±0.5P8-1
MAX144BCPA0°C to
+70°C8 Plastic DIP±1P8-1
MAX144BC/D0°C to
+70°CDice*±1—
MAX144AEUA-40°C to
+85°C8 µMAX±0.5U8-1
MAX144BEUA-40°C to
+85°C8 µMAX±1U8-1
MAX144AEPA-40°C to
+85°C8 Plastic DIP±0.5P8-1
MAX144BEPA-40°C to
+85°C8 Plastic DIP±1P8-1
MAX144AMJA-55°C to
+125°C8 CERDIP**±0.5J8-2
MAX144BMJA-55°C to
+125°C8 CERDIP**±1J8-2
Ordering InformationCS/SHDN
REFGND
SCLK
DOUT
( ) ARE FOR MAX145 ONLY
CH0 (CH+)
CH1 (CH-)
VDD
μMAX/DIP
TOP VIEW
MAX144
MAX145
Pin Configuration19-1387; Rev 2; 10/05
*Dice are specified at TA= +25°C, DC parameters only.
**Contact factory for availability.
Ordering Information continued at end of data sheet.Battery-Powered Systems
Portable Data Logging
Isolated Data Acquisition
Process-Control Monitoring
Instrumentation
Test Equipment
Medical Instruments
System Supervision
µMAX is a registered trademark of Maxim Integrated Products, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
2.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND ................. -0.3V to (VDD+ 0.3V)
REF to GND .............................................. -0.3V to (VDD+ 0.3V)
Digital Inputs to GND.............................................. -0.3V to +6V
DOUT to GND............................................ -0.3V to (VDD+ 0.3V)
DOUT Sink Current ........................................................... 25mA
Continuous Power Dissipation (TA= +70°C)
μMAX (derate 4.1mW/°C above +70°C) .................... 330mW
Plastic DIP (derate 9.09mW/°C above +70°C)............727mW
CERDIP (derate 8.00mW/°C above +70°C) ............... 640mW
Operating Temperature Ranges (TA)
MAX144/MAX145_C_A.......................................0°C to +70°C
MAX144/MAX145_E_A....................................-40°C to +85°C
MAX144/MAX145_M_A ................................ -55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
MAX14_A
MAX14_B
No missing codes over temperature
CONDITIONSLSB±0.5INLRelative Accuracy (Note 2)
Bits12RESResolution
LSB±0.75DNLDifferential Nonlinearity
UNITSMINTYPMAXSYMBOLPARAMETERppm/°C±0.8Gain Temperature Coefficient
LSB±3
LSB±3Offset Error
Gain Error
LSB±0.05Channel-to-Channel Offset
Matching
LSB±0.05Channel-to-Channel Gain
Matching
-3dB rolloff
fIN= 65kHz, VIN= 2.5Vp-p (Note 4)
External clock, fSCLK= 2.17MHz,
16 clocks/conversion cycle
MHz1.0Full-Power Bandwidth
MHz2.25-85Channel-to-Channel Crosstalk
Small-Signal Bandwidth7.4tCONVConversion Time (Note 5)
Total Harmonic Distortion
(including 5th-order harmonic)70SINADSignal-to-Noise Plus
Distortion Ratio-80THD80SFDRSpurious-Free Dynamic Range
Internal clock mode, for data transfer only
External clock mode
Internal clock5MHz0.12.17fSCLK<50Aperture Jitter
Serial Clock Frequency72.5tACQT/H Acquisition Time25Aperture Delay
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(fIN(sine-wave)= 10kHz, VIN= 2.5Vp-p, 108ksps, fSCLK= 2.17MHz, CH- = GND for MAX145)
CONVERSION RATE(Note 3)
.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
VREF= 2.5V
On/off leakage current, VIN= 0 to VDD1825Input Resistance1001400VDD
+ 50mVVREFInput Voltage Range
Input Current0.0110
CONDITIONSShutdown REF Input Current±0.01±1Multiplexer Leakage Current0VREFVINAnalog Input Voltage Range16CINInput Capacitance
UNITSMINTYPMAXSYMBOLPARAMETERInput Leakage CurrentIIN±1μA
Input HysteresisVHYS0.2V
0.25μA
Input High VoltageVIH2.0V3.0
Input Low VoltageVIL0.8V
Positive Supply CurrentIDD0.92.0mA
Three-State Output CapacitanceCOUT15pF
Positive Supply VoltageVDD2.75.25V
Power-Supply Rejection
Shutdown, CS/SHDN = GND
Operating mode
PSR±0.15mV
CS/SHDN = VDD(Note 8)
VDD= 2.7V to 5.25V,
VREF = 2.5V, full-scale input (Note 9)
Three-State Output Leakage
Current±10μA
Output High VoltageVOHVDD- 0.5V
Output Low Voltage
Input Capacitance
VIN= 0 or VDD
CIN15pF
VOL0.4V0.5
VDD≤3.6V
VDD> 3.6V
CS/SHDN = VDD
ISOURCE= 0.5mA
(Note 8)
ISINK= 5mA
ISINK= 16mA
ANALOG INPUTS
EXTERNAL REFERENCE
DIGITAL INPUTS (CS/SHDN) AND OUTPUT (DOUT)
POWER REQUIREMENTS(Note 6)
(Note 7)
MAX144/MAX145
+2.7V, Low-Power, 2-Channel, 108ksps,
Serial 12-Bit ADCs in 8-Pin µMAX
TIMING CHARACTERISTICS (Figure 7) (VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps), CH-= GND
for MAX145, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSWake-Up Time2.5µs
CS/SHDN Fall to Output EnabletDVCL = 100pF120ns
CS /SHDN Rise to Output DisabletTRCL = 100pF, Figure 1120ns
SCLK Fall to Output Data ValidtDOCL = 100pF, Figure 120120ns
External clock0.12.17SCLK Clock FrequencyfSCLKInternal clock, SCLK for data transfer only05MHz
External clock215
SCLK Pulse Width HightCHInternal clock, SCLK for data transfer only
(Note 8)50ns
External clock215
SCLK Pulse Width LowtCLInternal clock, SCLK for data transfer only
(Note 8)50ns
SCLK to CS /SHDN SetuptSCLKS60ns
CS /SHDN Pulse WidthtCS60ns
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3:Offset nulled.
Note 4:"On" channel is grounded; sine wave applied to "off" channel (MAX144 only).
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from GND to VDD(MAX145 only).
Note 7:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8:Guaranteed by design. Not subject to production testing.
Note 9:Measured as VFS(2.7V) -VFS(5.25V).
.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXSUPPLY CURRENT
vs. SUPPLY VOLTAGE
AX144/5-01
SUPPLY VOLTAGE (V)
(m
VREF = VDD
RL = ¥
CL = 50pF
CODE = 101010100000
SHUTDOWN CURRENT
vs. TEMPERATURE
AX144/5-05
TEMPERATURE (°C)
(nA
VREF = VDD
SUPPLY CURRENT
vs. TEMPERATURE
AX144/5-02
TEMPERATURE (°C)
(m
VREF = VDD
RL = ¥
CL = 50pF
CODE = 101010100000
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
AX144/5-04
SUPPLY VOLTAGE (V)
(n
VREF = VDD
Typical Operating Characteristic(VDD= +3.0V, VREF= 2.5V, 0.1μF at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C,
unless otherwise noted.)
SUPPLY CURRENT
vs. SAMPLING RATEX144/5-03
SAMPLING RATE (sps)
(m
10,000
0.11001k10k110100k
VDD = VREF
CL = 20pF
CODE = 101010100000
OFFSET ERROR
vs. SUPPLY VOLTAGE
AX144/5-06
SUPPLY VOLTAGE (V)
(L
OFFSET ERROR
vs. TEMPERATURE
AX144/5-07
TEMPERATURE (°C)
(L
GAIN ERROR
vs. SUPPLY VOLTAGE
X144/5-08
VDD (V)
ER
(L
GAIN ERROR
vs. TEMPERATURE
AX144/5-09
(L
TEMPERATURE (°C)
-60-1015-35406590115140
2.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXTypical Operating Characteristics (continued)(VDD= +3.0V, VREF= 2.5V, 0.1μF at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps), CH- = GND for MAX145, TA= +25°C,
unless otherwise noted.)
Pin DescriptionExternal Reference Voltage Input. Sets the analog voltage range. Bypass with a 100nF capacitor close to
the device.REF5
Active-Low Chip-Select Input/Active-High Shutdown Input. Pulling CS/SHDN high puts the device into
shutdown with a maximum current of 5μA.CS/SHDN6
Serial Data Output. Data changes state atSCLK’s falling edge. High impedance whenCS/SHDN
is high.DOUT7
Serial Clock Input. DOUT changes on the falling edge of SCLK.SCLK8
Analog and Digital GroundGND4
Analog Input: MAX144 = single-ended (CH1); MAX145 = differential (CH-)CH1 (CH-)3
PINAnalog Input: MAX144 = single-ended (CH0); MAX145 = differential (CH+)CH0 (CH+)2
Positive Supply Voltage, +2.7V to +5.25VVDD1
FUNCTIONNAMEINTEGRAL NONLINEARITY
vs. OUTPUT CODE
AX144/5-10
OUTPUT CODE
(L
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
AX144/5-11
VDD (V)
(L
INTEGRAL NONLINEARITY
vs. TEMPERATURE
AX144/5-12
(L
TEMPERATURE (°C)
FFT PLOT
144/5-13
FREQUENCY (kHz)
(d
VDD = +2.7V
fIN = 10kHz
fSAMPLE = 108ksps
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
AX144/5-14
FREQUENCY (kHz)
VDD = +2.7V
_______________Detailed DescriptionThe MAX144/MAX145 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track-and-hold (T/H)
structure to convert an analog signal to a serial 12-bit
digital output data stream.
This flexible serial interface provides easy interface to
microprocessors (μPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX144 (2 channels, single-ended) and the MAX145
(1 channel, pseudo-differential).
Analog Inputs: Single-Ended (MAX144)
and Pseudo-Differential (MAX145) The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit of
Figure 3. In single-ended mode (MAX144), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however, the output
data will still contain the channel identification bit
(before the MSB).
For the MAX145, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1μF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXCL
DOUT
a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-ZCL
DOUT
GNDGND
VDD
b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-ZFigure 1. Load Circuits for Enable and Disable Time
MAX144
MAX145
12-BIT
SAR
ADC
SCLK
( ) ARE FOR MAX145OUT
ANALOG
INPUT
MUX
(2 CHANNEL)
CH0
(CH+)
CH1
(CH-)
REF
T/H
CONTROL
LOGIC
SCLK
CS/SHDN
INTERNAL
CLOCK
OUTPUT
REGISTER
DOUT
Figure 2. Simplified Functional Diagram
CH0
(CH+)
CH1
(CH-)
( ) ARE FOR MAX145
SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN-
DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN-
RIN
9kW
ZERO
REF
GND
TRACKHOLD
COMPARATOR
TO SAR
T/H
CHOLD
16pFINPUT
MUX
12-BIT CAPACITIVE DAC
CSWITCH
CONTROL LOGIC
MAX144
MAX145
Figure 3. Analog Input Channel Structure
The capacitive digital-to-analog converter (DAC)adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 12-bit
resolution. This action is equivalent to transferring a
16pF ·[(VIN+) - (VIN-)] charge from CHOLDto the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/Hold (T/H)The ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX144 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX145
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”) and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLDcharges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ= 9(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN(9kΩ) is the input resistance, and CIN(16pF) is the
input capacitance of the ADC. Source impedances
below 1kΩhave no significant impact on the AC perfor-
mance of the MAX144/MAX145.
Higher source impedances can be used if a 0.01μF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX144/MAX145 T/H stage offers a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
make it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADCs sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous or
switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband response.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand GND, allow each input channel to swing
within GND - 300mV to VDD+ 300mV without damage.
However, for accurate conversions, both inputs must not
exceed VDD+ 50mV or be less than GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.2.7V, Low-Power, 2-Channel, 108ksps, rial 12-Bit ADCs in 8-Pin μMAXSHDN
OUTCLK
REFEXTERNAL
REFERENCE
CS/SHDN
DOUTP/mC
MAX7410
MAX7414
CH0VDD
VDD
VDD
GNDOSGNDCOM
0.01mF**
0.1mF
470W**
0.01mF
CH1IN
fC = 15kHz3
SCLK
MAX144
1.5MHz
OSCILLATOR
**USED TO ATTENUATE SWITCHED-CAPACITOR FILTER CLOCK NOISE
Figure 4. Analog Input with Anti-Aliasing Filter Structure
