MAX1416EUE+ ,16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCsFeaturesThe MAX1415/MAX1416 low-power, 2-channel, serial-● Improve Measurement Quality with Excelle ..
MAX1422ECM ,12-Bit, 20Msps, 3.3V, Low-Power ADC with Internal ReferenceELECTRICAL CHARACTERISTICS(V = V = 3.3V, AGND = DGND = 0, V = ±1.024V, differential input voltage a ..
MAX1425EAI ,10-Bit / 20Msps ADCApplicationsPin ConfigurationMedical Ultrasound ImagingTOP VIEWCCD Pixel ProcessingIR Focal Plane A ..
MAX1426EAI ,10-Bit / 10Msps ADCApplicationsPin ConfigurationMedical Ultrasound ImagingTOP VIEWCCD Pixel ProcessingIR Focal Plane A ..
MAX1426EAI-T ,10-Bit, 10Msps ADCApplicationsPin ConfigurationMedical Ultrasound ImagingCCD Pixel Processing TOP VIEW+IR Focal Plane ..
MAX1444EHJ ,10-Bit / 40Msps / 3.0V / Low-Power ADC with Internal ReferenceELECTRICAL CHARACTERISTICS(V = 3V; OV = 2.7V; 0.1µF and 1µF capacitors from REFP, REFN, and COM to ..
MAX4040ESA+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsApplicationsMAX4041ESA -40°C to +85°C 8 SO —Battery-Powered Strain GaugesMAX4041EUA -40°C to +85°C ..
MAX4040EUA ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS—T = +25°CA(V = +5.0V, V = 0, V = 0, V = V / 2, SHDN = V , R = 100kΩ tied ..
MAX4040EUK ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op Ampsapplications.Ordering InformationThe MAX4040 is offered in a space-saving 5-pin SOT23PIN- SOT packa ..
MAX4040EUK+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS—T = +25°C (continued)A(V = +5.0V, V = 0V, V = 0V, V = V / 2, SHDN = V , ..
MAX4040EUK-T ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op Ampsapplications.Ordering InformationThe MAX4040 is offered in a space-saving 5-pin SOT23PIN- SOT packa ..
MAX4040EUK-T ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op Ampsapplications.Ordering InformationThe MAX4040 is offered in a space-saving 5-pin SOT23PIN- SOT packa ..
MAX1415EWE+-MAX1416EUE+
16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
General DescriptionThe MAX1415/MAX1416 low-power, 2-channel, serial-
output analog-to-digital converters (ADCs) use a sigma-
delta modulator with a digital filter to achieve 16-bit
resolution with no missing codes. These ADCs are
pin-compatible upgrades to the MX7705/AD7705. The
MAX1415/MAX1416 feature an internal oscillator (1MHz
or 2.4576MHz), an on-chip input buffer, and a program-
mable gain amplifier (PGA). The devices offer an SPI-/
QSPI™-/MICROWIRE®-compatible serial interface.
The MAX1415/MAX1416 are available in 16-pin PDIP,
SO, and TSSOP packages.
Applications●Industrial Instruments●Weigh Scales●Strain-Gauge Measurements●Loop-Powered Systems●Flow and Gas Meters●Medical Instrumentation●Pressure Transducers●Thermocouple Measurements●RTD Measurements
Beneits and Features●Improve Measurement Quality with Excellent DC
Accuracy16-Bit Sigma-Delta ADC with Two Fully-Differential
Input Channels0.0015% INL (max) with No Missing Codes●Minimize Power Consumption with Low-Power
Dissipation1.2mW (max) 3V supply• 2μA (typ) Power-Down Current●Lower System Cost with Integrated FunctionalityPGA with 1 to 128 Programmable GainOptional Input Buffers> 98dB 50Hz/60Hz Rejection●Increase System Accuracy with Built-in Self
CalibrationOn-Demand Offset and Gain Self-Calibration and
System CalibrationUser-Programmable Offset and Gain Registers●Flexible Single-Supply Options2.7V to 3.6V (MAX1415)4.75V to 5.25V (MAX1416)●Pin Compatible Upgrades for MX7705/AD7705
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
MAX1415
MAX1416MUX
CLOCK
GENERATOR
DIGITAL
FILTER
2nd-ORDER
SIGMA-DELTA
MODULATOR
PGA
BUFFER
BUFFER
SERIAL INTERFACE,
REGISTERS,
AND
CONTROL
VDD
GND
SCLK
DIN
DOUT
CLKIN
CLKOUT
AIN1+
AIN1-
AIN2+
AIN2-
REF+
REF-
S1 AND S2 ARE OPEN IN
BUFFERED MODE AND CLOSED
IN UNBUFFERED MODE
DRDY
RESET
Functional Diagram
EVALUATION KIT AVAILABLE
VDD to GND ............................................................-0.3V to +6V
All Other Pins to GND ..............................-0.3V to (VDD + 0.3V)
Maximum Current Input into Any Pin .................................50mA
Continuous Power Dissipation (TA = +70°C)16-Pin PDIP (derate 10.5mW/°C above +70°C) .........842mW16-Pin TSSOP (derate 9.4mW/°C above +70°C) ........755mW16-Pin Wide SO (derate 9.5mW/°C above +70°C) .....762mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = 3V, VGND = 0V, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND = 0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution (No Missing Codes)16Bits
Output Noise(Tables 1, 3)µV
Integral NonlinearityINLGain = 1, bipolar mode, unbuffered±0.0015%FSR
Unipolar Offset ErrorAfter calibration(Note 1)µV
Unipolar Offset Drift(Note 2)0.5µV/°C
Bipolar Zero ErrorAfter calibration(Note 1)µV
Bipolar Zero Drift (Note 2)
Gain = 1 to 40.5
µV/°CGain = 8 to 1280.1
Positive Full-Scale ErrorAfter calibration(Notes 1, 3)µV
Full-Scale Drift(Notes 2, 4)0.5µV/°C
Gain ErrorAfter calibration(Notes 1, 5)µV
Gain Drift(Notes 2, 6)0.5ppm of
FSR/°C
Bipolar Negative Full-Scale ErrorAfter calibration±0.003%FSR
Bipolar Negative Full-Scale Drift
(Note 2)
Gain = 1 to 41
µV/°CGain = 8 to 1280.6
ANALOG INPUTS (AIN1+, AIN1-, AIN2+, AIN2-)AIN Differential Input Voltage
Range (Note 7)
Unipolar input range0VREF /
GAIN
Bipolar input range-VREF
/ GAIN
VREF /
GAIN
AIN Absolute Input Voltage
Range (Note 8)
UnbufferedGND -
30mV
VDD +
30mV
BufferedGND +
50mV
VDD -
1.5V
Electrical Characteristics—MAX1415
(VDD = 3V, VGND = 0V, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND = 0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1415 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAIN Input Capacitance
Gain = 134Gain = 238
Gain = 445
Gain = 8 to 12860
AIN Input Sampling Rate fsGain = 1 to 128fCLKIN
/ 64MHz
Input Common-Mode RejectionCMR
Gain = 1105Gain = 2110
Gain = 4120
Gain = 8 to 128130
Normal-Mode 50Hz RejectionFor ilter notches of 25Hz, 50Hz,
±0.02 x fNOTCH98dB
Normal-Mode 60Hz RejectionFor ilter notches of 20Hz, 60Hz,
±0.02 x fNOTCH98dB
Common-Mode 50Hz RejectionFor ilter notches of 25Hz, 50Hz,
±0.02 x fNOTCH150dB
Common-Mode 60Hz RejectionFor ilter notches of 20Hz, 60Hz,
±0.02 x fNOTCH150dB
EXTERNAL REFERENCE (REF+, REF-)REF Differential Input RangeVREF(Note 9)1.001.75V
REF Absolute Input Voltage RangeGNDVDDV
REF Input CapacitanceGain = 1 to 12810pF
REF Input Sampling Rate fsfCLKIN
/ 64MHz
DIGITAL INPUTS (DIN, SCLK, CS, RESET)Input High VoltageVIH2.0V
Input Low VoltageVIL0.4V
Input Hysteresis VHYSTDIN, CS, RESET250mVSCLK500
Input CurrentIIN±1µA
Input Capacitance5pF
CLKIN INPUTCLKIN Input High VoltageVCLKINH2.5V
CLKIN Input Low VoltageVCLKINL0.4V
CLKIN Input CurrentICLKIN±10µA
DIGITAL OUTPUTS (DOUT, DRDY, CLKOUT)Output-Voltage Low VOLDOUT and DRDY, ISINK = 100µA0.4
(VDD = 3V, VGND = 0V, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND = 0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1415 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput-Voltage HighVOHDOUT and DRDY, ISOURCE = 100µAVDD -0.6V
CLKOUT, ISOURCE = 10µAVDD -0.6V
Tri-State Leakage CurrentILDOUT only±10µA
Tri-State Output CapacitanceCOUTDOUT only9pF
SYSTEM CALIBRATIONFull-Scale Calibration RangeGAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 x
VREF /
GAIN
1.05 x
VREF /
GAIN
Offset Calibration RangeGAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 x
VREF /
GAIN
1.05 x
VREF /
GAIN
Input SpanGAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
0.8 x
VREF /
GAIN
2.1 x
VREF /
GAIN
POWER REQUIREMENTSPower-Supply Voltage VDD2.73.6V
Power-Supply Current (Note 12)IDD
Unbuffered, fCLKIN = 1MHz, gain = 1 to 1280.40
Buffered, fCLKIN = 1MHz, gain = 1 to 1280.725
Unbuffered,
fCLKIN = 2.4576MHz
Gain = 1 to 40.55
Gain = 8 to 1280.55
Buffered,
fCLKIN = 2.4576MHz
Gain = 1 to 40.825
Gain = 8 to 1281.0
Power-down mode (Note 13)8µA
Power-Supply Rejection RatioPSRRVDD = 2.7V to 3.6V(Note 14)dB
EXTERNAL-CLOCK TIMING SPECIFICATIONSCLKIN FrequencyfCLKIN(Note 15)4002500kHz
Duty Cycle4060%
INTERNAL-CLOCK TIMING SPECIFICATIONS
Internal-Clock FrequencyfCLK
MAX1415AE__,
fCLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
TA = -40°C to
+85°C±4
MAX1415C__,
fCLK = 1MHz (CLK = 0)
or 2.4576MHz (CLK = 1)
TA = 0°C to
+70°C±4
MAX1415E__,
fCLK = 1MHz (CLK = 0)
TA = -40°C to 0°C±7
(VDD = 3V, VGND = 0V, VREF+ = 1.225V, VREF- = GND, external fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND = 0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
(Note 16) (Figures 8, 9)
(VDD = 5V, VGND = 0V, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND =
0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1415 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSTypical Conversion-Time Variation∆tCONVtCONV = 1/ODR±0.5%
Timing Characteristics—MAX1415
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDRDY High Time500/
fCLKINs
Reset Pulse-Width Low100ns
DRDY Fall to CS Fall Setup Timet10ns
CS Fall to SCLK Rise Setup Timet2120ns
SCLK Fall to DOUT Valid Delayt30100ns
SCLK Pulse-Width Hight4100ns
SCLK Pulse-Width Lowt5100ns
CS Rise to SCLK Rise Hold Timet60ns
Bus Relinquish Time After SCLK
Rising Edget7100ns
SCLK Fall to DRDY Rise Delayt8100ns
DIN to SCLK Setup Timet930ns
DIN to SCLK Hold Timet1020ns
Electrical Characteristics—MAX1416
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution (No Missing Codes)16Bits
Output Noise(Tables 1, 3)µV
Integral NonlinearityINLGain = 1, bipolar mode, unbuffered±0.0015%FSR
Unipolar Offset Error After calibration(Note 1)µV
Unipolar Offset Drift(Note 2)0.5µV/°C
Bipolar Zero ErrorAfter calibration(Note 1)µV
Bipolar Zero Drift (Note 2)Gain = 1 to 40.5µV/°C
Gain = 8 to 1280.1
(VDD = 5V, VGND = 0V, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND =
0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1416 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPositive Full-Scale ErrorAfter calibration(Notes 1, 3)µV
Full-Scale Drift(Notes 2, 4)0.5µV/°C
Gain Error After calibration(Notes 1, 5)µV
Gain Drift(Notes 2, 6)0.5ppm of
FSR/°C
Bipolar Negative Full-Scale ErrorAfter calibration±0.003%FSR
Bipolar Negative Full-Scale Drift
(Note 2)
Gain = 1 to 41
µV/°C
Gain = 8 to 1280.6
ANALOG INPUTS (AIN1+, AIN1-, AIN2+, AIN2-)AIN Differential Input Voltage Range
(Note 7)
Unipolar input range0VREF /
GAINV
Bipolar input range-VREF /
GAIN
VREF /
GAIN
AIN Absolute Input Voltage Range
(Note 8)
UnbufferedGND -
30mV
VDD +
30mV
BufferedGND +
50mV
VDD -
1.5V
AIN DC Leakage CurrentUnselected input channel1nA
AIN Input Capacitance
Gain = 134
Gain = 238
Gain = 445
Gain = 8 to 12860
AIN Input Sampling Rate fsGain = 1 to 128fCLKIN
/ 64MHz
Input Common-Mode RejectionCMR
Gain = 196Gain = 2105
Gain = 4110
Gain = 8 to 128130
Normal-Mode 50Hz RejectionFor ilter notches of 25Hz, 50Hz,
±0.02 x fNOTCH98dB
Normal-Mode 60Hz RejectionFor ilter notches of 20Hz, 60Hz,
±0.02 x fNOTCH98dB
Common-Mode 50Hz RejectionFor ilter notches of 25Hz, 50Hz,
±0.02 x fNOTCH150dB
Common-Mode 60Hz RejectionFor ilter notches of 20Hz, 60Hz,
±0.02 x fNOTCH150dB
(VDD = 5V, VGND = 0V, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND =
0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1416 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCE (REF+, REF-)REF Differential Input RangeVREF(Note 9)13.5V
REF Absolute Input Voltage RangeGNDVDDV
REF Input CapacitanceGain = 1 to 12810pF
REF Input Sampling Rate fsfCLKIN
/ 64MHz
DIGITAL INPUTS (DIN, SCLK, CS, RESET)Input High VoltageVIH2V
Input Low VoltageVIL0.8V
Input Hysteresis VHYSTDIN, CS, RESET250SCLK500
Input CurrentIIN±1µA
Input Capacitance5pF
CLKIN INPUTCLKIN Input High VoltageVCLKINH3.5V
CLKIN Input Low VoltageVCLKINL0.8V
CLKIN Input CurrentICLKIN±10µA
DIGITAL OUTPUTS (DOUT, DRDY, CLKOUT)Output-Voltage LowVOLDOUT and DRDY, ISINK = 800µA 0.4CLKOUT, ISINK = 10µA0.4
Output-Voltage HighVOHDOUT and DRDY, ISOURCE = 200µA 4.0CLKOUT, ISOURCE = 10µA4.0
Tri-State Leakage CurrentILDOUT only±10µA
Tri-State Output CapacitanceCOUTDOUT only9pF
SYSTEM CALIBRATIONFull-Scale Calibration RangeGAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 x
VREF /
GAIN
+1.05 x
VREF /
GAIN
Offset Calibration RangeGAIN = selected PGA gain (1 to 128)
(Note 10)
-1.05 x
VREF /
GAIN
+1.05 x
VREF /
GAIN
Input SpanGAIN = selected PGA gain (1 to 128)
(Notes 10, 11)
0.8 x
VREF /
GAIN
2.1 x
VREF /
GAIN
POWER REQUIREMENTSPower-Supply VoltageVDD4.755.25V
(VDD = 5V, VGND = 0V, VREF+ = 2.5V, VREF- = GND, fCLKIN = 2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1μF, CREF- to GND =
0.1μF, TA = TMIN to TMAX, unless otherwise noted.)
(Note 16) (Figures 8, 9)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Electrical Characteristics—MAX1416 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-Supply Current (Note 12)IDD
Unbuffered, fCLKIN = 1MHz, gain = 1 to 1280.45
Buffered, fCLKIN = 1MHz, gain = 1 to 1280.78
Unbuffered,
fCLKIN = 2.4576MHz
Gain = 1 to 40.6
Gain = 8 to 1280.6
Buffered,
fCLKIN = 2.4576MHz
Gain = 1 to 40.95
Gain = 8 to 1281.1
Power-down mode (Note 13)16µA
Power-Supply Rejection RatioPSRRVDD = 4.75V to 5.25V(Note 14)dB
EXTERNAL-CLOCK SPECIFICATIONSCLKIN Frequency fCLKIN(Note 15)4002500kHz
Duty Cycle4060%
INTERNAL-CLOCK TIMING SPECIFICATIONSInternal-Clock FrequencyfCLK
MAX1416AE__,
fCLK = 1MHz (CLK = 0) or
2.4576MHz (CLK = 1)
TA = -40°C to
+85°C±4
MAX1416C__,
fCLK = 1MHz (CLK = 0) or
2.4576MHz (CLK = 1)
TA = 0°C to
+70°C±4
MAX1416E__,
fCLK = 1MHz (CLK = 0) or
2.4576MHz (CLK = 1)
TA = -40°C to 0°C±7
TA = 0°C to +85°C±4
Typical Conversion-Time Variation∆tCONVtCONV = 1/ODR,
CLK = 0 (1MHz), INTCLK = 1±0.5%
Timing Characteristics—MAX1416
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDRDY High Time500 /
fCLKINs
Reset Pulse-Width Low100ns
DRDY Fall to CS Fall Setup Timet10ns
CS Fall to SCLK Rise Setup Timet2120ns
SCLK Fall to DOUT Valid Delayt3080ns
SCLK Pulse-Width Hight4100ns
SCLK Pulse-Width Lowt5100ns
CS Rise to SCLK Rise Hold Timet60ns
Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given
temperature.
Note 2: Recalibration at any temperature removes these drift errors.
Note 3: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 4: Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
input ranges.
Note 5: Gain error does not include zero-scale errors. It is calculated as (full-scale error – unipolar offset error) for unipolar rang-
es, and (full-scale error – bipolar zero error) for bipolar ranges.
Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero drift. Effectively, it is the drift of the part if only zero-
scale calibrations are performed.
Note 7: The analog input voltage range on AIN+ is given here with respect to the voltage on AIN- on the MAX1415/MAX1416.
Note 8: This common-mode voltage range is allowed, provided that the input voltage on the analog inputs does not go more posi-
tive than (VDD + 30mV) or more negative than (GND - 30mV). Parts are functional with voltages down to (GND - 200mV),
but with increased leakage at high temperature.
Note 9: The REF differential voltage, VREF, is the voltage on REF+ referenced to REF- (VREF = VREF+ - VREF-).
Note 10: Guaranteed by design.
Note 11: These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (VDD +
30mV) or go more negative than (GND - 30mV). The offset-calibration limit applies to both the unipolar zero point and the
bipolar zero point.
Note 12: When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the supply
current and power dissipation varies depending on the crystal or resonator type. Supply current is measured with the digi-
tal inputs connected to 0 or VDD, CLKIN connected to an external clock source, and CLKDIS = 1.
Note 13: If the external master clock continues to run in power-down mode, the power-down current typically increases to 67μA
at 3V. When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the
clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type
(see the Power-Down Modes section).
Note 14: Measured at DC and applied in the selected passband. PSRR at 50Hz exceeds 120dB with filter notches of 25Hz or
50Hz. PSRR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz.PSRR depends on both gain and VDD.
Note 15: Provide fCLKIN whenever the MAX1415/MAX1416 are not in power-down mode. If no clock is present, the device can
draw higher-than-specified current and can possibly become uncalibrated.
Note 16: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
(Note 16) (Figures 8, 9)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Timing Characteristics—MAX1416 (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK Fall to DRDY Rise Delayt8100ns
DIN to SCLK Setup Timet930ns
DIN to SCLK Hold Timet1020ns
GAINPSRR (VDD = 5V)PSRR (VDD = 3V) (dB)908678788485
8 to 1289193
Table 1. MAX1415—Output RMS Noise vs. Gain and Output Data Rate (3V)MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
FILTER FIRST
NOTCH
AND OUTPUT DATA RATE (Hz)
-3dB FREQUENCY(Hz)
TYPICAL OUTPUT RMS NOISE (µV)
GAIN248163264128
BUFFERED (fCLKIN = 1MHz)5.242.851.632.160.700.670.630.640.626.553.461.921.136.050.750.730.700.70
UNBUFFERED (fCLKIN = 1MHz)5.243.091.701.050.720.660.640.600.606.553.581.941.230.800.770.730.700.70
BUFFERED (fCLKIN = 2.4576MHz)13.13.031.971.341.010.950.930.960.9515.723.622.141.521.050.981.031.041.00
UNBUFFERED (fCLKIN = 2.4576MHz)13.13.761.630.960.690.660.640.590.6115.723.111.861.120.780.750.710.710.69
500131280.67143.1575.8434.7017.889.194.904.98
Table 2. MAX1415—Peak-to-Peak Resolution vs. Gain and Output Data RateMAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
FILTER FIRST
NOTCH AND OUTPUT
DATA RATE (Hz)
-3dB FREQUENCY(Hz)
TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)
GAIN248163264128
BUFFERED (fCLKIN = 1MHz)5.2416161616151413126.551616161215141312
UNBUFFERED (fCLKIN = 1MHz)5.2416161616151413126.551616161615141312
BUFFERED (fCLKIN = 2.4576MHz)13.1161616151514131215.721616161514131211
UNBUFFERED (fCLKIN = 2.4576MHz)13.1161616161514131215.721616161615141312
500131101010101010109
Table 3. MAX1416—Output RMS Noise vs. Gain and Output Data Rate (5V)MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
FILTER FIRST
NOTCH AND OUTPUT DATA RATE (Hz)
-3dB FREQUENCY(Hz)
TYPICAL OUTPUT RMS NOISE (µV)
GAIN248163264128
BUFFERED (fCLKIN = 1MHz)5.243.511.871.110.750.700.710.670.656.554.462.391.320.900.830.810.750.74
UNBUFFERED (fCLKIN = 1MHz)5.243.881.921.170.760.720.700.650.656.555.002.601.410.870.830.810.730.74
BUFFERED (fCLKIN = 2.4576MHz)13.14.102.561.681.231.191.211.151.1915.724.522.961.891.321.321.271.281.31
UNBUFFERED (fCLKIN = 2.4576MHz)13.13.211.841.140.760.730.720.640.6515.723.932.211.370.870.810.770.740.73
500131520.55302.42136.5468.6636.9418.649.349.49
Table 4. MAX1416—Peak-to-Peak Resolution vs. Gain and Output Data RateMAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
FILTER FIRST
NOTCH AND OUTPUT
DATA RATE (Hz)
-3dB FREQUENCY(Hz)
TYPICAL PEAK-TO-PEAK RESOLUTION (BITS)
GAIN248163264128
BUFFERED (fCLKIN = 1MHz)5.2416161616161514136.551616161616151413
UNBUFFERED (fCLKIN = 1MHz)5.2416161616161514136.551616161616151413
BUFFERED (fCLKIN = 2.4576MHz)13.1161616161514131215.721616161615141312
UNBUFFERED (fCLKIN = 2.4576MHz)13.1161616161615141315.721616161616151413
500131101010101010109
(MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V,
VREF- = GND, TA = +25°C, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Typical Operating Characteristics
TYPICAL OUTPUT NOISE
(MAX1416, BUFFERED MODE)MAX1415/MAX1416 toc01
READING NUMBER
CODE READ
VDD = 5V,
VREF = 2.5V
GAIN = 128
ODR = 60Hz
RMS NOISE = 1.3µV
HISTOGRAM OF TYPICAL OUTPUT NOISE
(MAX1416, BUFFERED MODE)MAX1415/MAX1416 toc02
CODE
OCCURRENCE
VDD = 5V, VREF = 2.5V
GAIN = 128
ODR = 60Hz
RMS NOISE = 1.3µV
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1415)MAX1415/MAX1416 toc03
SUPPLY VOLTAGE (V)
OFFSET ERROR (%FSR)
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1416)
MAX1415/MAX1416 toc04
SUPPLY VOLTAGE (V)
OFFSET ERROR (%FSR)3510-15
OFFSET ERROR vs. TEMPERATURE
MAX1415/MAX1416 toc05
TEMPERATURE (°C)
OFFSET ERROR (%FSR)
MAX1415
MAX1416
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1415)MAX1415/MAX1416 toc06
SUPPLY VOLTAGE (V)
GAIN ERROR (%FSR)
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1416)
MAX1415/MAX1416 toc07
GAIN ERROR (%FSR)
GAIN ERROR vs. TEMPERATURE
MAX1415/MAX1416 toc08
GAIN ERROR (%FSR)3510-15
MAX1415
MAX1416
(MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V,
VREF- = GND, TA = +25°C, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Typical Operating Characteristics (continued)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1415)MAX1415/MAX1416 toc09
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
A: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 8 TO 128
B: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 4
E: UNBUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
C: BUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
D: UNBUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 128
SUPPLY CURRENT vs. TEMPERATURE
(MAX1415)
MAX1415/MAX1416 toc11
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
A: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 8 TO 128
B: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 4
E: UNBUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
C: BUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
D: UNBUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 128
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1416)
MAX1415/MAX1416 toc10
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
A: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 8 TO 128
B: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 4
E: UNBUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
C: BUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
D: UNBUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 128C3510-15
SUPPLY CURRENT vs. TEMPERATURE
(MAX1416)
MAX1415/MAX1416 toc12
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
A: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 8 TO 128
B: BUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 4
E: UNBUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
C: BUFFERED MODE
fCLKIN = 1MHz,
GAIN = 1 TO 128
D: UNBUFFERED MODE
fCLKIN = 2.4576MHz,
GAIN = 1 TO 128
(MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V,
VREF- = GND, TA = +25°C, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Typical Operating Characteristics (continued)
SUPPLY CURRENT vs. fCLKIN
(MAX1415)fCLKIN (MHz)
MAX1415/MAX1416 toc13
SUPPLY CURRENT (mA)
A: BUFFERED MODE
CLK = 1,
GAIN = 128
B: BUFFERED MODE
CLK = 1,
GAIN = 1
E: UNBUFFERED MODE
CLK = 0,
GAIN = 1, 128
C: BUFFERED MODE
CLK = 0,
GAIN = 1, 128
D: UNBUFFERED MODE
CLK = 1,
GAIN = 1, 128
GAIN32168421128
SUPPLY CURRENT vs. GAIN
(MAX1415)MAX1415/MAX1416 toc15
SUPPLY CURRENT (mA)
A: BUFFERED MODE
CLK = 1, CLKDIV = 1,
fCLKIN = 4.9152MHz
B: BUFFERED MODE
CLK = 1, CLKDIV = 0,
fCLKIN = 2.4576MHz
E: UNBUFFERED MODE
CLK = 1, CLKDIV = 0,
fCLKIN = 2.4576MHz
F: UNBUFFERED MODE
CLK = 0, CLKDIV = 0,
fCLKIN = 1MHz
C: BUFFERED MODE
CLK = 0, CLKDIV = 0,
fCLKIN = 1MHz
D: UNBUFFERED MODE
CLK = 1, CLKDIV = 1,
fCLKIN = 4.9152MHz
A, B
D, E
SUPPLY CURRENT vs. fCLKIN
(MAX1416)fCLKIN (MHz)
MAX1415/MAX1416 toc14
SUPPLY CURRENT (mA)
A: BUFFERED MODE
CLK = 1,
GAIN = 128
B: BUFFERED MODE
CLK = 1,
GAIN = 1
E: UNBUFFERED MODE
CLK = 0,
GAIN = 1, 128
C: BUFFERED MODE
CLK = 0,
GAIN = 1, 128
D: UNBUFFERED MODE
CLK = 1,
GAIN = 1, 128
GAIN32168421128
SUPPLY CURRENT vs. GAIN
(MAX1416)MAX1415/MAX1416 toc16
SUPPLY CURRENT (mA)
A: BUFFERED MODE
CLK = 1, CLKDIV = 1,
fCLKIN = 4.9152MHz
B: BUFFERED MODE
CLK = 1, CLKDIV = 0,
fCLKIN = 2.4576MHz
E: UNBUFFERED MODE
CLK = 1, CLKDIV = 0,
fCLKIN = 2.4576MHz
F: UNBUFFERED MODE
CLK = 0, CLKDIV = 0,
fCLKIN = 1MHz
C: BUFFERED MODE
CLK = 0, CLKDIV = 0,
fCLKIN = 1MHz
D: UNBUFFERED MODE
CLK = 1, CLKDIV = 1,
fCLKIN = 4.9152MHzC
(MAX1415: VDD = 5V, VREF+ = 2.5V, VREF- = GND, TA = +25°C, unless otherwise noted.) (MAX1416: VDD = 3V, VREF+ = 1.225V,
VREF- = GND, TA = +25°C, unless otherwise noted.)
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Typical Operating Characteristics (continued)
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1415)SUPPLY VOLTAGE (V)
POWER-DOWN SUPPLY CURRENT (nA)
MAX1415/MAX1416 toc17
EXTERNAL OSCILLATOR STARTUP TIME2ms/div
VDD
5V/div
CLKOUT
5V/div
CLKOUT
5V/div
MAX1415/MAX1416 toc20
4.9152MHz CRYSTAL
2.4576MHz CRYSTAL
INTERNAL OSCILLATOR STARTUP TIME4µs/div
SCLK
5V/div
CLKOUT
5V/div
CLK = 1
CLKOUT
5V/div
CLK = 0
MAX1415/MAX1416 toc21
16th RISING EDGE OF SCLK
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1416)
SUPPLY VOLTAGE (V)
POWER-DOWN SUPPLY CURRENT (nA)
MAX1415/MAX1416 toc18
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATUREMAX1415/MAX1416 toc19
TEMPERATURE (°C)
POWER-DOWN SUPPLY CURRENT (nA)3510-15
MAX1415
VDD = 5V
MAX1416
VDD = 3V
MAX1415/MAX141616-Bit, Low-Power, 2-Channel,
Sigma-Delta ADCs
Pin Description
PINNAMEFUNCTIONSCLKSerial Clock Input. Apply an external serial clock to transfer data to and from the device at data rates
up to 5MHz.CLKINClock Input. Connect a crystal/resonator between CLKIN and CLKOUT, or drive CLKIN externally with
a CMOS-compatible clock source. Connect CLKIN to GND when using the internal oscillator.CLKOUT
Clock Output. Connect a crystal/resonator between CLKIN and CLKOUT. When enabled, CLKOUT
provides a CMOS-compatible, inverted clock output. CLKOUT can drive one CMOS load. Set CLKDIS
= 0 in the clock register to enable CLKOUT. Set CLKDIS = 1 in the clock register to disable CLKOUT.CS
Active-Low Chip-Select Input. CS selects the active device in systems with more than one device on
the serial bus. Drive CS low to clock data in on DIN and to clock data out on DOUT. When CS is high,
DOUT is high impedance. Connect CS to GND for 3-wire operation.RESETActive-Low Reset Input. Drive RESET low to reset the MAX1415/MAX1416 to power-on reset status.AIN2+Channel 2 Positive Analog Input AIN1+Channel 1 Positive Analog InputAIN1-Channel 1 Negative Analog InputREF+Positive Reference InputREF-Negative Reference InputAIN2-Channel 2 Negative Analog InputDRDYActive-Low Data Ready Output. DRDY goes low when a new conversion result is available in the data
register. When a read operation of a full output word completes, DRDY returns high. DOUTSerial Data Output. DOUT outputs serial data from the data register. DOUT changes on the falling
edge of SCLK and is valid on the rising edge of SCLK. When CS is high, DOUT is high impedance. DINSerial Data Input. Data on DIN is clocked in on the rising edge of SCLK when CS is low.VDDPower Input. Connect VDD to a 2.7V to 3.6V power supply for the MAX1415, and connect VDD to a
4.75V to 5.25V power supply for the MAX1416. GNDGround
