MAX1408CAI+ ,Low-Power, 16-Bit Multichannel DAS with Internal Reference, 10-Bit DACs, and RTCfeatures a 50mV trip threshold for the♦ 10-Bit Force/Sense DACs signal-detect comparator while the ..
MAX1409CAP ,Low-Power / 16-Bit Multichannel DAS with Internal Reference /10-Bit DACs / and RTCApplications+1.8V and +2.7V RESET and Power-Supply Voltage MonitorsMedical Instruments Signal Detec ..
MAX1414CAI ,Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTCELECTRICAL CHARACTERISTICS(DV = AV = +2.7V to 3.6V, 4.7µF at REF, internal V , 18nF between CPLL an ..
MAX1414CAI ,Low-Power, 16-Bit Multichannel DAS with Internal Reference,10-Bit DACs, and RTCApplications+1.8V and +2.7V RESET and Power-Supply Voltage MonitorsMedical Instruments Signal Detec ..
MAX1414CAI+ ,Low-Power, 16-Bit Multichannel DAS with Internal Reference, 10-Bit DACs, and RTCapplications. All the devices operate from a sin-gle +2.7V to +3.6V power supply and consume a♦ 2.5 ..
MAX1414CAI+T ,Low-Power, 16-Bit Multichannel DAS with Internal Reference, 10-Bit DACs, and RTCELECTRICAL CHARACTERISTICS(DV = AV = +2.7V to 3.6V, 4.7µF at REF, internal V , 18nF between CPLL an ..
MAX4032EUT+T ,5V, 6dB Video Buffer with Sync-Tip Clamp, Output Sag Correction, and 150nA Shutdown CurrentELECTRICAL CHARACTERISTICS(V = 5.0V, GND = 0V, C = 0.1µF from IN to GND, R = infinity to GND, SAG s ..
MAX4032EXT+T ,5V, 6dB Video Buffer with Sync-Tip Clamp, Output Sag Correction, and 150nA Shutdown CurrentBlock DiagramVideo-Enabled Cell PhonesNotebook ComputersPortable/Flat-Panel DisplaysTOP VIEW VCCMAX ..
MAX4037EUT ,Low IBIAS, +1.4V/800nA, Rail-to-Rail Op Amps with +1.2V Buffered ReferenceApplicationsPIN- TOPBattery-Powered/Solar-Powered SystemsPART TEMP RANGEPACKAGE MARKPortable Medica ..
MAX4039EUB ,Low IBIAS / +1.4V/800nA / Rail-to-Rail Op Amps with +1.2V Buffered ReferenceApplications PACKAGE MARKMAX4036EXK-T -40°C to +85°C 5 SC70-5 AFRBattery-Powered/Solar-Powered Syst ..
MAX4040ESA ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsApplicationsMAX4041ESA -40°C to +85°C 8 SO —Battery-Powered Strain GaugesMAX4041EUA -40°C to +85°C ..
MAX4040ESA+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsApplicationsMAX4041ESA -40°C to +85°C 8 SO —Battery-Powered Strain GaugesMAX4041EUA -40°C to +85°C ..
MAX1408CAI+-MAX1414CAI+-MAX1414CAI+T
Low-Power, 16-Bit Multichannel DAS with Internal Reference, 10-Bit DACs, and RTC
General DescriptionThe MAX1407/MAX1408/MAX1409/MAX1414 are low-
power, general-purpose, multichannel data-acquisition
systems (DAS). These devices are optimized for low-
power applications. All the devices operate from a sin-
gle +2.7V to +3.6V power supply and consume a
maximum of 1.15mA in Run mode and only 2.5µA in
Sleep mode.
The MAX1407/MAX1408/MAX1414 feature a differential
8:1 input multiplexer to the ADC, a programmable
three-state digital output, an output to shutdown an
external power supply, and a data ready output from
the ADC. The MAX1408 has eight auxiliary analog
inputs, while the MAX1407/MAX1414 include four auxil-
iary analog inputs and two 10-bit force/sense DACs.
The MAX1414 features a 50mV trip threshold for the
signal-detect comparator while the others have a 0mV
trip threshold. The MAX1409 is a 20-pin version of the
DAS family with a differential 4:1 input multiplexer to the
ADC, one auxiliary analog input, and one 10-bit
force/sense DAC.
The MAX1407/MAX1408/MAX1414 are available in
space-saving 28-pin SSOP packages, while the
MAX1409 is available in a 20-pin SSOP package.
ApplicationsMedical Instruments
Industrial Control Systems
Portable Equipment
Data-Acquisition System
Automatic Testing
Robotics
Features+2.7V to +3.6V Supply Voltage Range in Standby,
Idle, and Run Mode (Down to 1.8V in Sleep Mode) 1.15mA Run Mode Supply Current 2.5µA Sleep Mode Supply Current (Wake-Up, RTC,
and Voltage Monitor Active)Multichannel 16-Bit Sigma-Delta ADC
±1.5 LSB (typ) Integral Nonlinearity
30Hz or 60Hz Continuous Conversion Rate
Buffered or Unbuffered Mode
Gain of +1/3, +1, or +2V/V
Unipolar or Bipolar Mode
On-Chip Offset Calibration10-Bit Force/Sense DACs Buffered 1.25V, 18ppm/°C (typ) Bandgap
Reference OutputSPI™/QSPI™or MICROWIRE™-Compatible Serial
InterfaceSystem Support Functions
RTC (Valid til 9999) and Alarm
High-Frequency PLL Clock Output (2.4576MHz)
+1.8V and +2.7V RESETand Power-Supply
Voltage Monitors
Signal Detect Comparator
Interrupt Generator (INTand DRDY)
Three-State Digital Output
Wake-Up Circuitry28-Pin SSOP (MAX1407/MAX1408/MAX1414),
20-Pin SSOP (MAX1409)
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC19-2229; Rev 0; 10/01
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information
PARTTEMP. RANGEPIN-PACKAGE
MAX1407CAI0°C to +70°C28 SSOP
MAX1408CAI0°C to +70°C28 SSOP
MAX1409CAP0°C to +70°C20 SSOP
MAX1414CAI0°C to +70°C28 SSOP
OUT2
IN3
DVDD
DGND
SCLK
DIN
DOUT
CLKIN
CLKOUT
FOUT
IN2
IN1
CPLL
AVDD
AGND
REF
IN0
OUT1
FB1
FB2
TOP VIEW
MAX1407
MAX1414
WU2
RESET
WU1
INT
DRDY
SHDN
Pin Configurations
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +6V
AVDDto DVDD......................................................-0.3V to +0.3V
Analog Inputs to AGND.........................-0.3V to +(AVDD+ 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
Maximum Current Input Into Any Pin..................................50mA
Continuous Power Dissipation (TA= +70°C)
20-Pin SSOP (derate 8.0mW/°C above +70°C)...........640mW
28-Pin SSOP (derate 9.52mW/°C above +70°C).........762mW
DVDDto DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Analog Outputs to AGND......................-0.3V to +(AVDD+ 0.3V)
Digital Outputs to DGND.......................-0.3V to +(AVDD+ 0.3V)
REF to AGND.........................................-0.3V to +(AVDD+ 0.3V)
Operating Temperature Range:
MAX14__CA_......................................................0°C to +70°C
MAX14__EA_...................................................-40°C to +85°C
Lead Temperature (soldering, 10s)................................+300 °C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
ELECTRICAL CHARACTERISTICS(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T S
ADC ACCURACYResolution (No Missing Codes)RES16Bits
Unbuffered mode, Unipolar mode, gain = 1,
VNEG = 0.2V, fully differential input (Note 7)1.53.5nb uffer ed m od e, U ni p ol ar m od e, g ai n = 2,N E G = 0.625V , p seud o- d i ffer enti al i np ut1.75
Unbuffered mode, Bipolar mode, gain = 1,
VNEG = 0.625V, fully differential input1.70
Integral NonlinearityINL
Buffered mode, Bipolar mode, gain = 2,
VNEG = 0.625V, fully differential input2.50
LSB
Gain = 2±5
Gain = 1±10Unipolar
Gain = 1/3±30
Gain = 2±8
Gain = 1±16.5
Output RMS Noise (Note 1)
Bipolar Mode
Gain = 1/3±48.5
µVRMS
Offset ErrorOn-chip calibration removes this error±1% of FS R
Offset Drift±0.5µV/°C
Gain ErrorExcludes offset and reference errors±1% of FS R
Gain DriftExcludes offset and reference errors±1p p m /° C
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T S1/3PGA GainSee PGA Gain section
V/V
Power-Supply Rejection RatioGain = 1, unipolar and buffered mode70dB
RATE bit = 030Output Update RateContinuous
conversionRATE bit = 160Hz
Turn-On TimeExcluding reference50µs
SIGNAL DETECT COMPARATORMAX1407/MAX1408/MAX1409-10010Differential Input-Detection
Threshold VoltageMAX1414445056mV
Common-Mode Input Voltage00.8V
Turn-On Time10µs
ANALOG INPUTSADC gain = 10VREF
ADC gain = 20VREF/2Unipolar mode
ADC gain = 1/30AVDD
ADC gain = 1-VREFVREF
ADC gain = 2-VREF/2VREF/2
Differential Input Voltage Range
Bipolar mode
ADC gain = 1/3-AVDDAVDD
Unbuffered-0.05AVDDAbsolute Input Voltage RangeBuffered0.051.40V
UnbufferedAGNDAVDDCommon-Mode Input Voltage
RangeBuffered0.051.40V
Common-Mode Rejection RatioGain = 1, unipolar and buffered mode90dB
30Hz data rate15.360Input Sampling RateFOUT = 2.4576MHz60Hz data rate30.720kHz
Input CurrentBuffered mode±0.5nA
Input Capacitance15pF
O R C E- SEN SE D A C ( al l m easur em ents m ad e w i th FB1( 2) shor ted to O U T1( 2) , unl ess other w i se noted ) .M AX 1407/M AX 1409/M AX 1414 onl y)
Resolution10Bits
Differential NonlinearityGuaranteed monotonic (Note 2)±1.0LSB
Integral Nonlinearity(Note 2)±1.0LSB
Offset Error(Note 3)±20mV
Offset Drift±5µV/°C
Gain ErrorExcludes offset and reference drift3.6mV
Gain DriftExcludes offset and reference drift10ppm/°C
Line Regulation190µV/V
Current into FB1(2)±0.5nA
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T SOutput Slew Rate010hex to 3FFhex and 3FFhex to 010hex
cod e sw i ng , RL = 12kΩ , C L = 200p F18.0V/ms
Output Settling Time
To ±1/2 LSB (at 10-bit accuracy) of full-
scale with code transition from 010hex
to 3FFhex, RL = 12kΩ, CL = 200pFµs
Turn-On Time100µs
OUT1, OUT2 Output RangeNo Load (Note 4)0.05 AVDD
- 0.2V
EXTERNAL REFERENCE (internal reference powered down)Input Voltage Range1.25 ±0.10V
Input Resistance540kΩ
Input Current2.3µA
INTERNAL REFERENCE (AVDD = 3V, unless otherwise noted)Output VoltageTA = +25°C1.2251.251.275V
Output Voltage Temperature
Coefficient18p p m /° C
Output Short-Circuit Current3.4mA
Line RegulationΔV RE F /ΔV DD2.7
ISOURCE = 0µA to 500µA, TA = +25°C1Load RegulationISINK = 0µA to 50µA, TA = +25°C2µV/µA
0.1Hz to 10Hz40Noise VoltageeOUT10Hz to 10kHz400µVp-p
Power-Supply Rejection Ratio±100mV, f = 120Hz70dB
Turn-On Time3ms
µP RESET
Supply Voltage RangeFor valid RESET13.6V
Bit VM = 11.8001.8651.930RESET Trip Threshold LowVTHAVDD fallingBit VM = 02.702.752.80V
Low AVDD Trip ThresholdFor Normal, Idle, and Standby modes,
AVDD falling2.702.752.80V
RESET Output Low Voltage
(Open-Drain Output)ISINK = 1mA, AVDD = 1.8V0.4V
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T S
RESET Output LeakageAVDD > VTH, RESET deasserted0.0020.1µA
Turn-On Time2ms
CRYSTAL OSCILLATOR
Crystal FrequencyAVDD = +3V32.768kHz
Crystal Load Capacitance6pF
Oscillator StabilityAV D D = + 1.8V to + 3.6V , excl ud i ng cr ystal 0ppm/V
Oscillator Startup Time1.5s
PLL
FOUT FrequencyAVDD = +3V2.4576MHz
Absolute Clock JitterCycle-to-cycle10ns
Overtemperature excluding crystal,
TA = TMIN to TMAX0p p m /° C Frequency Tolerance/Stability
Over supp l y vol tag e, + 2.7V < AV D D < +3.6V0p p m /m V
FOUT Rise/Fall Time20% to 80% waveform, CL = 30pF1530ns
Duty Cycle405060%
DIGITAL INPUTS (DIN, SCLK, CS, WU1, WU2)
Input High VoltageDVDD = +1.8V to +3.6V0.7 x
DVDDV
Input Low VoltageDVDD = +1.8V to +3.6V0.3 x
DVDDV
Input HysteresisDVDD = +3V200mV
DIN, SCLK, CS, Input CurrentVIN = 0 or VIN = DVDD±0.01±10µA
WU1, WU2 Input CurrentVIN = AVDD0.0110µA
WU1, WU2 Pullup CurrentVIN = 010µA
Input Capacitance10pF
DIGITAL OUTPUTS (DOUT, FOUT, INT, DRDY, SHDN, D0)
DOUT, FOUT, DRDY, INT
Output Low VoltageVOLISINK = 1mA, DVDD = +1.8V to +3.6V0.4V
DOUT, FOUT, DRDY, INT,
SHDN Output High VoltageVOHISOURCE = 0.2mA, DVDD = +1.8V to +3.6V0.8 x DVDDV
DOUT Three-State Leakage±0.01±10µA
DOUT Three-State Capacitance15pF
ISINK = 1mA, DVDD = +1.8V to +3.6V0.4SHDN Output Low Voltage
(MAX1407/MAX1408/MAX1414
only)ISINK = 50µA, DVDD = +1.8V to +3.6V0.04 x
DVDD
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
ELECTRICAL CHARACTERISTICS (continued)
(DVDD= AVDD= +2.7V to 3.6V, 4.7µF at REF, internal VREF, 18nF between CPLL and AVDD, 32.768kHz crystal across CLKIN and
CLKOUT, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXU N I T S
D0 Output Low Voltage
(MAX1407/MAX1408/MAX1414
only)
ISINK = 200µA, DVDD = +2.7V to +3.6V0.7mV
D0 Output High Voltage
(MAX1407/MAX1408/MAX1414
only)
IS OU RC E = 2m A, D V D D = + 2.7V to + 3.6V DVDD
- 0.1V
POWER REQUIREMENTS
Run, Idle, and Standby mode2.73.6Supply Voltage RangeVDDSleep mode1.83.6V
MAX1407/MAX14141.15
MAX14081.03Run mode
MAX14091.09
MAX1407/MAX1414650
MAX1408530Idle mode
MAX1409590
Standby modeMAX1407/MAX1408/
MAX1409/MAX1414330
Supply Current (Note 5)IDD
Sleep mode
VDD = 2.7V
MAX1407/MAX1408/
MAX1409/MAX14141.72.5
TIMING CHARACTERISTICS
(MAX1407/MAX1408/MAX1409/MAX1414: AVDD = DVDD = 2.7V to 3.6V, TA = TMINto TMAX,unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING PARAMETERS
SCLK Operating FrequencyfSCLK2.1MHz
SCLK Cycle TimetCYC476ns
SCLK Pulse Width HightCH190ns
SCLK Pulse Width LowtCL190ns
DIN to SCLK SetuptDS100ns
DIN to SCLK HoldtDH0ns
SCLK Fall to Output Data ValidtDOCL = 50pF (see load circuit)200ns
CS Fall to Output EnabletDVCL = 50pF (see load circuit)240ns
CS Rise to Output DisabletTRCL = 50pF (see load circuit)240ns
CS to SCLK Rise SetuptCSS100ns
CS to SCLK Rise HoldtCSH0ns
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Note 1:Single conversion.
Note 2:DNL and INL are measured between code 010hex and 3FFhex.
Note 3:Offset error is referenced to code 010hex.
Note 4:Output swing is a function of external gain-setting feedback resistors and REF voltage.
Note 5:Measured with no load on FOUT, DOUT, and the DAC amplifiers. SCLK is idle, and all digital inputs are at DGND or DVDD.
Note 6:SHDNstays high if the PLL is on.
Note 7:Actual worst-case performance is ±2.5LSB. Guaranteed limit of ±3.5LSB is due to production test limitation.
Note 8:Guaranteed by design. Not production tested.
TIMING CHARACTERISTICS (continued)
(MAX1407/MAX1408/MAX1409/MAX1414: AVDD = DVDD = 2.7V to 3.6V, TA = TMINto TMAX,unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TYPICAL TIMING PARAMETERS
OUT1/OUT2 Turn-Off TimeInput impedance > 1MΩ
(MAX1407/MAX1409/MAX1414 only)100µs
Sleep Voltage Monitor Timeout
PeriodtDSLP
The delay for the sleep voltage monitor
output, RESET, to go high after AVDD rises
above the reset threshold (+1.8V when bit
VM = 1 and +2.7V, when bit VM = 0); this is
largely driven by the startup of the 32kHz
oscillator
1.54s
WU1 or WU2 Pulse WidthtWUMinimum pulse width required to detect a
wake-up event1µs
Shutdown Deassert DelaytDPUThe delay for SHDN to go high after a valid
wake-up event1µs
FOUT Turn-On TimetDFON
The turn-on time for the high-frequency
clock; it is gated by an AND function with
three signals—the RESET signal, the internal
low voltage VDD monitor signal, and the
assertion of the PLL; the time delay is timed
from when the low-voltage monitor trips or
the RESET going high, whichever happens
later; FOUT always starts in the low state
31.25ms
INT DelaytDFI
The delay for INT to go low after the FOUT
clock output has been enabled; INT is used
as an interrupt signal to inform the µP the
high-frequency clock has started
7.82ms
FOUT Disable DelaytDFOF
The delay after a shutdown command has
asserted and before FOUT is disabled; this
gives the microcontroller time to clean up
and go into Sleep mode properly
1.95ms
SHDN Assertion DelaytDPD
The delay after a shutdown command has
asserted and before SHDN is pulled low
(turning off the DC-DC converter) (Note 6)
2.93ms
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs.
SUPPLY VOLTAGE
MAX1407 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
RUN MODE
IDLE MODE
STANDBY
SUPPLY CURRENT vs.
TEMPERATURE
MAX1407 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (
STANDBY
IDLE MODE
RUN MODE
SLEEP CURRENT vs. FALLING VDD
MAX1407 toc03
SUPLLY VOLTAGE (V)
SLEEP CURRENT (
SLEEP MODE SUPPLY CURRENT
vs. TEMPERATURE
MAX1407 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (
Load Circuits
6kΩ
6kΩ
DOUT
DOUT
DGNDDGND
DVDD
a) VOH TO HIGH-Zb) VOL TO HIGH-Z
CLOAD
50pFCLOAD
50pF
LOAD CIRCUITS FOR DISABLE TIME
6kΩ
6kΩ
DOUT
DOUT
DGNDDGND
DVDD
a) HIGH-Z TO VOH AND VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL
CLOAD
50pFCLOAD
50pF
LOAD CIRCUITS FOR ENABLE TIME
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
MAXIMUM INL vs. VDD
(UNIPOLAR MODE, T = +25°C,
PSEUDO-DIFFERENTIAL INPUT)
MAX1407 toc05
VDD (V)
MAXIMUM INL (LSB)A
A: GAIN = 1, UNBUFFERED MODE, 60sps
B: GAIN = 1, UNBUFFERED MODE, 30sps
MAXIMUM INL vs. VDD
(BIPOLAR MODE, T = +25°C,
FULLY DIFFERENTIAL INPUT)
MAX1407 toc06
VDD (V)
MAXIMUM INL (LSB)
A: GAIN = 2, BUFFERED MODE, 60sps
B: GAIN = 2, BUFFERED MODE, 30sps
MAXIMUM INL vs. TEMPERATURE
(UNIPOLAR MODE, VDD = 3V,
PSEUDO-DIFFERENTIAL INPUT)
MAX1407 toc07
TEMPERATURE (°C)
MAXIMUM INL (LSB)
A: GAIN = 1, UNBUFFERED MODE, 60sps
B: GAIN = 1, UNBUFFERED MODE, 30sps
MAXIMUM INL vs. TEMPERATURE
(BIPOLAR MODE, VDD = 3V,
FULLY DIFFERENTIAL INPUT)
MAX1407 toc08
TEMPERATURE (°C)
MAXIMUM INL (LSB)A
A: GAIN = 2, BUFFERED MODE, 60sps
B: GAIN = 2, BUFFERED MODE, 30sps
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
MAXIMUM INL vs. COMMON-MODE
INPUT VOLTAGE (BIPOLAR MODE,
BUFFERED MODE, VDD = 2.7V, 30sps,
FULLY DIFFERENTIAL INPUT, T = +25°C)
MAX1407 toc09
COMMON-MODE INPUT VOLTAGE (V)
MAXIMUM INL (LSB)
A: GAIN = 1
B: GAIN = 2
INL vs. FULLY DIFFERENTIAL
INPUT VOLTAGE (BIPOLAR MODE,
GAIN = 1, UNBUFFERED MODE,
VCM = 0.625V, VDD = 3V, T = +25°C)
MAX1407 toc10
DIFFERENTIAL INPUT VOLTAGE (V)
INL (LSB)
INL vs. PSEUDO-DIFFERENTIAL INPUT
VOLTAGE RANGE (UNIPOLAR MODE,
GAIN = 1, UNBUFFERED MODE,
VNEG = 0, VDD = 3V, T = +25°C)
MAX1407 toc11
DIFFERENTIAL VOLTAGE (V)
INL (LSB)
UNCORRECTED OFFSET ERROR
vs. TEMPERATURE
(UNBUFFERED MODE, VDD = 3V)
MAX1407 toc12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
A: GAIN = 1, UNIPOLAR MODE
B: GAIN = 2, BIPOLAR MODE
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
GAIN ERROR vs. TEMPERATURE
MAX1407 toc13
TEMPERATURE (°C)
GAIN ERROR (%)206080
VDD = 3V
A: GAIN = 1, UNIPOLAR MODE, UNBUFFERED MODE
B: GAIN = 1, BIPOLAR MODE, UNBUFFERED MODE
C: GAIN = 2, UNIPOLAR MODE, BUFFERED MODE
D: GAIN = 2, BIPOLAR MODE, BUFFERED MODE
REFERENCE VOLTAGE vs.
TEMPERATURE
MAX1407 toc14
TEMPERATURE (°C)
% DEVIATION
VREF = 1.24406V
IREF = 0
REFERENCE VOLTAGE vs.
OUTPUT SOURCE CURRENT
MAX1407 toc15
SOURCE CURRENT (μA)
REFERENCE
VOLTAGE
(V)
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
MAX1407 toc16
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
NO LOAD
DAC OFFSET ERROR vs.
TEMPERATURE
MAX1407 toc17
TEMPERATURE (°C)
OFFSET ERROR (mV)
IDLE MODE
DAC OFFSET ERROR vs.
SUPPLY VOLTAGE
MAX1407 toc18
SUPPLY VOLTAGE (V)
OFFSET ERROR (mV)
IDLE MODE
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
DAC GAIN ERROR vs.
TEMPERATURE
MAX1407 toc19
TEMPERATURE (°C)
GAIN ERROR (LSB)
IDLE MODE
INTERNAL REF USED-0.20
DAC GAIN ERROR vs.
SUPPLY VOLTAGE
MAX1407 toc20
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
IDLE MODE
INTERNAL REF USED
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE (AVDD = 2.7V)
MAX1407 toc21
CODE
INL (LSB)
DAC INTEGRAL NONLINEARITY
vs. DIGITAL CODE (AVDD = 3.6V)
MAX1407 toc22
CODE
INL (LSB)
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE (AVDD = 2.7V)
MAX1407 toc23
CODE
DNL (LSB)
DAC DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE (AVDD = 3.6V)
MAX1407 toc24
CODE
DNL (LSB)
DAC LARGE-SIGNAL OUTPUT
STEP RESPONSE
VREF = 1.25V, AVDD = 3.0V, RL = 0
MAX1407 toc25
OUT_
500mV/DIV
2V/DIV
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, MAX1407 used, TA = +25°C, unless otherwise noted.)
DAC OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX1407 toc26
SUPPLY VOLTAGE (V)
DAC OUTPUT VOLTAGE (V)
OUTPUT AT FULL SCALE
NO LOAD
DAC BUFFER IN UNITY GAIN
DAC OUTPUT VOLTAGE
vs. SOURCE CURRENT
MAX1407 toc27
LOAD CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
OUTPUT AT FULL SCALE
DAC BUFFER IN UNITY GAIN
DAC OUTPUT VOLTAGE
vs. SINK CURRENT
MAX1407 toc28
SINK CURRENT (µA)
DAC OUTPUT VOLTAGE (V)
DAC OUTPUT VOLTAGE vs.
TEMPERATURE
MAX1407 toc29
TEMPERATURE (°C)
DAC OUTPUT VOLTAGE (%)
VREF = 1.24406V
IREF = 0
VOLTAGE MONITOR THRESHOLD
vs. TEMPERATURE
MAX1407 toc30
TEMPERATURE (°C)
% DEVIATION
V1.8V_THRESHOLD = 1.865V
V2.7V_THRESHOLD = 2.75V
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
MAX1407
MAX1414MAX1408MAX1409PINFUNCTION——FB2Force/Sense DAC2 Feedback Input1—IN7Analog Input. Analog input to the negative mux only.1FB1Force/Sense DAC1 Feedback Input—D0Digital Output. Three-state general-purpose digital output.——FB1Force/Sense DAC1 Feedback Input3—IN6Analog Input. Analog input to the negative mux only.—2OUT1Force/Sense DAC1 Output4—IN4Analog Input. Analog input to the positive mux only.53IN0Analog Input. Analog input to both the positive and negative mux.64REF
1.25V Reference Buffer Output/External Reference Input. Reference voltage
for the ADC and the DAC. Connect a 4.7µF capacitor to REF between REF
and AGND.75AGNDAnalog Ground. Reference point for the analog circuitry. AGND connects to
the IC substrate.6AVDDAnalog Supply Voltage97CPLLPLL Capacitor Connection Pin. Connect an 18nF ceramic capacitor between
CPLL and AVDD.108WU1Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU1 is asserted.119WU2Active-Low Wake-Up Input. Internally pulled up. The device will wake-up from
Sleep mode to Standby mode when WU2 is asserted.1210RESET
Active-Low RESET Output. It remains low while AVDD is below the threshold
and stays low for a timeout period after AVDD rises above the threshold.
RESET is an open-drain output.13—IN1Analog Input. Analog input to both the positive and negative mux.14—IN2Analog Input. Analog input to both the positive and negative mux.15—SHDNProgrammable Shutdown Output. Goes low in Sleep mode.16—DRDY
Active-Low Data Ready Output. A logic low indicates that a new conversion
result is available in the Data register. DRDY returns high upon completion of
a full output word read operation. DRDY also signals the end of an ADC
offset-calibration.1711FOUT2.4576MHz Clock Output. FOUT can be used to drive the input clock of a µP.1812CLKOUT32kHz Crystal Output. Connect a 32kHz crystal between CLKIN and
CLKOUT.1913CLKIN32kHz Crystal Input. Connect a 32kHz crystal between CLKIN and CLKOUT.
Pin Description
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Detailed Information
The MAX1407/MAX1408/MAX1409/MAX1414 are low-
power, general-purpose, multichannel DAS featuring a
multiplexed fully differential 16-bit ∑Δanalog-to-digital
converter (ADC), 10-bit force/sense digital-to-analog
converters (DAC), a real-time clock (RTC) with an
alarm, a bandgap voltage reference, a signal detect
comparator, two power-supply voltage monitors, wake-
up control circuitry, and a high-frequency phase-locked
loop (PLL) clock output all controlled by a 3-wire serial
interface. (See Table 1 for the MAX1407/MAX1408/
MAX1409/MAX1414 feature sets and Figures 1, 2, 3 for
the Functional Diagrams). These DAS directly interface
to various sensor outputs and once configured provide
the stimulus, conditioning, and data conversion, as well
as microprocessor support. Figure 4 is a Typical
Application Circuitfor the MAX1407/MAX1414.
The 16-bit ∑ΔADC is capable of programmable contin-
uous conversion rates of 30Hz or 60Hz and gains of
1/3, 1, and 2V/V to suit applications with different power
and dynamic range constraints. The force/sense DACs
provide 10-bit linearity for precise sensor applications.
MAX1407
MAX1414MAX1408MAX1409PINFUNCTION2014INTActive-Low Interrupt Output. INT goes low when the PLL output is ready,
when the signal-detect comparator is tripped, or when the alarm is triggered.2115DOUTSerial Data Output. DOUT outputs serial data from the internal shift register
on SCLK’s falling edge. When CS is high, DOUT is three-stated.2216DINSerial Data Input. Data on DIN is written to the input shift register and is
clocked in at SCLK’s rising edge when CS is low.2317SCLK
Serial Clock Input. Apply an external serial clock to transfer data to and from
the device. This serial clock can be continuous, with data transmitted in a
train of pulses, or intermittent while CS is low.2418CS
Active-Low Chip-Select Input. CS is used to select the active device in
systems with more than one device on the serial bus. Data will not be
clocked into DIN unless CS is low. When CS is high, DOUT is three-stated.2519DGNDDigital Ground. Reference point for digital circuitry.2620DVDDDigital Supply Voltage27—IN3Analog Input. Analog input to both the positive and negative mux.——OUT2Force/Sense DAC2 Output28—IN5Analog Input. Analog input to the positive mux only.
Pin Description (continued)
Table 1. MAX1407/MAX1408/MAX1409/MAX1414 Feature Sets
PART
ADC
AUXILIARY
ANALOG
INPUTS
FORCE/
SENSE
DAC
THREE-
STATE
DIGITAL
OUTPUT
COMPARATOR
THRESHOLD
(mV)
RTC
ADC DATA
READY
(DRDY)
EXTERNAL
POWER-
SUPPLY
SHUTDOWN
CONTROL
ADC
DIFFERENTIAL
INPUT MUX
MAX140742Yes0YesYesYes8
MAX141442Yes50YesYesYes8
MAX140880Yes0YesYesYes8
MAX140911No0YesNoNo4
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
With the use of two external resistors, the DAC output
can go from 0.05V to AVDD- 0.2V. The ADCs and
DACs both utilize a precise low-drift 1.25V internal
bandgap reference for conversions and setting of the
full-scale range. For applications that require increased
accuracy, power-down the internal reference and con-
nect an external reference at REF. The RTC is leap year
compensated until 9999 and provides an alarm function
that can be used to wake-up the system or cause an
interrupt at a predefined time. The power-supply volt-
age monitors detect when AVDDfalls below a trip
threshold voltage at either +1.8V or +2.7V causing the
reset to be asserted. The 4-wire serial interface is used
to communicate directly between SPI, QSPI, and
MICROWIRE devices for system configuration and
readback functions.
Analog Input Protection
Internal protection diodes clamp the analog input to
AVDDand AGND, which allow the channel input pins to
swing from AGND - 0.3V to AVDD+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed AVDDby more than 50mV
or be lower than AGND by 50mV.
Analog Mux
The MAX1407/MAX1408/MAX1414 include a dual 8 to 1
multiplexer for the positive and negative inputs of the
ADC. The MAX1409 has a dual 4 to 1 multiplexer at the
inputs of the ADC. Figures 1, 2, and 3 illustrate which
signals are present at the inputs of each multiplexer for
the MAX1407/MAX1408/MAX1409/MAX1414. The
MUXP and MUXN bits of the MUX register choose
which inputs will be seen at the input to the ADC
(Tables 4 and 5) and the signal-detect comparator. See
the MUX Register description under the On-Chip
Registerssection for multiplexer functionality.
Input Buffers
The MAX1407/MAX1408/MAX1409/MAX1414 provide
input buffers to isolate the analog inputs from the capaci-
tive load presented by the ADC modulator (Figure 5 and
6). The buffers are chopper stabilized to reduce the effect
of their DC offsets and low-frequency noise. Since the
buffers can represent more than 25% of the total analog
power dissipation (typically 220µA), they may be shut
down in applications where minimum power dissipation is
required and the capacitive input load is not a concern
(see ADC and Power1 Registers). Disable the buffers in
applications where the inputs must operate close to
AGND or above +1.4V. The buffers are individually
enabled or disabled.
Figure 1. MAX1407/MAX1414 Functional Diagram
MAX1407/MAX1414
*MAX1414 HAS A +50mV SIGNAL-DETECT COMPARATOR THRESHOLD.
10-BIT DAC
INTERRUPT
GENERATOR
REFRESETDGND
16-BIT ADCPGA
BUF
BUF
WAKE-UP
LOGIC
SERIAL
INTERFACE
2.4576MHz
PLL
32.768kHz
OSCILLATOR
1.25V
BANDGAP
REFERENCE
1.8V/2.7V
SUPERVISORS
RESET
GENERATOR
RTC AND
ALARM
DIGITAL
OUTPUT
10-BIT DAC
8:1
INPUT
MUX
8:1
INPUT
MUX
BUF
AGND
CPLLFOUTCLKINCLKOUT
COMPARATOR
AVDD
SCLK
DIN
DOUT
OUT2
OUT1IN3
IN2
IN1
IN0
REFAVDD
FB2
FB1
IN3
IN2
IN1
IN0
REF
AGND
WU2
WU1
SHDN
INT
DRDY
OUT1
FB1
OUT2
FB2
DVDD
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Figure 3. MAX1409 Functional Diagram
MAX1409
INTERRUPT
GENERATOR
REFRESETDGND
16-BIT ADCPGA
BUF
BUF
WAKE-UP
LOGIC
SERIAL
INTERFACE
2.4576MHz
PLL
32.768kHz
OSCILLATOR
1.25V
BANDGAP
REFERENCE
1.8V/2.7VμP
SUPERVISORS
RESET
GENERATOR
RTC AND
ALARM
10-BIT DAC
4:1
INPUT
MUX
4:1
INPUT
MUX
BUF
AGND
CPLLFOUTCLKINCLKOUT
COMPARATOR
AVDD
SCLK
DIN
DOUT
WU2
WU1
INT
OUT1
FB1
OUT1
AVDD
IN0
REF
DVDD
FB1
IN0
REF
AGND
Figure 2. MAX1408 Functional Diagram
MAX1408
INTERRUPT
GENERATOR
REFRESETDGND
16-BIT ADCPGA
BUF
BUF
WAKE-UP
LOGIC
SERIAL
INTERFACE
2.4576MHz
PLL
32.768kHz
OSCILLATOR
1.25V
BANDGAP
REFERENCE
1.8V/2.7V
SUPERVISORS
RESET
GENERATOR
RTC AND
ALARM
DIGITAL
OUTPUT
8:1
INPUT
MUX
8:1
INPUT
MUX
BUF
AGND
CPLLFOUTCLKINCLKOUT
COMPARATOR
AVDD
SCLK
DIN
DOUT
IN5
IN4IN3
IN2
IN1
IN0
REFAVDD
IN7
IN6
IN3
IN2
IN1
IN0
REF
AGND
WU2
WU1
SHDN
INT
DRDY
DVDD
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Buffered Mode
When used in buffered mode, the buffers isolate the
inputs from the sampling capacitors. The sampling-
related gain error is dramatically reduced since only a
small dynamic load is present from the chopper. The
multiplexer exhibits an input leakage current of 0.5nA
(typ). With high-source resistances, this leakage cur-
rent may result in a large DC offset error.
Figure 4. MAX1407/MAX1414 Typical Application Circuit
MAX1407
MAX1414
MAX1833
IN0
REF
IN1
10μF
10μF
VDD = 3.3V OR VBAT
0.1μF0.1μF18nF
4.7μF
FB1
FB2
OUT2
OUT1
RESET
CLKIN
CLKOUT
FOUT
SCLK
DIN
DOUT
INT
DRDY
RESET
CLKIN
0.1μF
OUTPUT
SCK
MOSI
MISO
INPUT
INPUT
μP/μC
WU2I/O
VBAT
BATT
OUT
RST
SHDN
SENSOR
GNDCPLL
AGNDDGND
AVDDDVDDVDD
VSS
SHDN
32.768kHz
WU1I/O
Figure 5. Analog Input—Buffered Mode
REXT
CEXT
RMUX
CPIN
RIN
CSTCAMP
CSAMPLECC
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Unbuffered Mode
When used in unbuffered mode, the switched capacitor
sampling front end of the modulator presents a dynam-
ic load to the driving circuitry. The size of the internal
sampling capacitor and the input sampling frequency
(Figure 6) determines the dynamic load (see Dynamic
Input Impedancesection). As the gain increases, the
input sampling capacitance also increases. Since the
MAX1407/MAX1408/MAX1409/MAX1414 sample at a
constant rate for all gain settings, the dynamic load pre-
sented by the inputs varies with the gain setting.
PGA Gain
An integrated programmable-gain amplifier (PGA) pro-
vides three user-selectable gains: +1/3V/V, +1V/V, and
+2V/V to maximize the dynamic range of the ADC. Bits
GAIN1 and GAIN0 set the desired gain (see ADC
Register). The gain of +1/3V/V allows the direct mea-
surement of the supply voltage through an internal mul-
tiplexer input or through an auxillary input.
ADC Modulator
The MAX1407/MAX1408/MAX1409/MAX1414 perform
analog-to-digital conversions using a single-bit, sec-
ond-order, switched-capacitor delta-sigma modulator.
The delta-sigma modulation converts the input signal
into a digital pulse train whose average duty cycle rep-
resents the digitized signal information. The pulse train
is then processed by a digital decimation filter.
The modulator provides 2nd-order frequency shaping
of the quantization noise resulting from the single bit
quantizer. The modulator is fully differential for maxi-
mum signal-to-noise ratio and minimum susceptibility to
power-supply noise. The modulator operates at one of
two different sampling rates resulting in an output data
rate of either 30Hz or 60Hz (see ADC Register).
ADC Offset Calibration
The MAX1407/MAX1408/MAX1409/MAX1414 are capa-
ble of performing digital offset correction to eliminate
changes due to power-supply voltage or system tem-
perature. At the end of a calibration cycle, a 16-bit cali-
bration value is stored in the Offset register in two’s
compliment format. After completing a conversion, the
MAX1407/MAX1408/MAX1409/MAX1414 subtract the
calibration value from the ADC conversion result and
write the offset compensated data to the Data register
(see Offset Registersection). Either a positive or nega-
tive offset can be calibrated. During offset calibration,
DRDYwill go high. DRDYgoes low after calibration is
complete. The offset register can be programmed to
skew the ADC offset with a maximum range from -215to
(+215- 1)LSBs, e.g., if the programmed 2’s complement
value is +2LSB (-2LSB), this translates to a -2LSB
(+2LSB) shift in bipolar mode or a -4LSB (+4LSB) shift in
unipolar mode.To maintain optimum performance, recal-
ibrate the ADC if the temperature changes by more than
20°C. Offset calibration should also be performed after
any changes in PGA gain, bipolar/unipolar input range,
buffered/unbuffered mode, or conversion speed. During
calibration, the two mulitplexers will be disabled and the
inputs to the ADC will internally be shorted to a com-
mon-mode voltage.
ADC Digital Filter
The on-chip digital filter processes the 1-bit data
stream from the modulator using a SINC3filter function.
The SINC3filters settle in three data word periods. The
settling time is 3/60Hz or 50ms (for RATE bit in ADC
register set to 1) and 3/30Hz or 100ms (for RATE bit set
to “0”).
ADC Digital Filter Characteristics
The transfer function for a SINC3filter function is that of
three cascaded SINC1filters. This can be described in
the Z-domain by:
and in the frequency domain by:
where N, the decimation factor, is the ratio of the modu-
lator frequency fMto the output frequency fN.ƒ()=
sin
sin()=−()()11
Figure 6. Analog Input—Unbuffered Mode
REXT
CEXT
RMUX
CPIN
RSW
CSTCSAMPLECC
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Figure 7 shows the filter frequency response. The
SINC3characteristic cutoff frequency is 0.262 times the
first notch frequency. This results in a cutoff frequency
of 15.72Hz for a first filter notch frequency of 60Hz (out-
put data rate of 60Hz). The response shown in Figure 7
is repeated at either side of the digital filter’s sample
frequency (fM) (fM= 15.36kHz for 30Hz and fM=
30.72kHz for 60Hz) and at either side of the related har-
monics (2fM, 3fM,....).
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. Therefore, for the plot of Figure 7
where the first notch of the filter is at 60Hz, the output
data rate is 60Hz. The notches of this (sinx/x)3 filter are
repeated at multiples of the first notch frequency. The
SINC3filter provides an attenuation of better than
100dB at these notches.
For step changes at the input, enough settling time
must be allowed before valid data can be read. The
settling time depends upon the output data rate chosen
for the filter. The settling time of the SINC3filter to a full-
scale step input can be up to four times the output data
period, or three times if the step change is synchrozied
with FSYNC.
Force/Sense DAC
(MAX1407/MAX1409/MAX1414)
The MAX1407/MAX1414 incorporate two 10-bit force/
sense DACs while the MAX1409 has one. The DACs
use a precise 1.25V internal bandgap reference for set-
ting the full-scale range. Program the DAC1 and DAC2
registers through the serial interface to set the output
voltages of the DACs seen at OUT1 and OUT2.
Shorting FB1(2) and OUT1(2) configures the DAC in a
unity-gain setting. Connecting resistors in a voltage-
divider configuration between OUT1(2), FB1(2), and
GND sets a different closed-loop gain for the output
amplifier (see the Applications Informationsection).
The DAC output amplifier typically settles to ±1/2LSB
from a full-scale transition within 65µs, when it is con-
nected in unity gain and loaded with 12kΩin parallel
with 200pF. Loads less than 2kΩmay degrade perfor-
mance. See the Typical Operating Characteristicssec-
tion for the source-and-sink capabilty of the DAC
output.
The MAX1407/MAX1409/MAX1414 feature a software-
programmable shutdown mode for the DACs that
reduce the total power consumption when they are not
used. The two DACs can be powered-down indepen-
dently or simultaneously by clearing the DA1E and
DA2E bits (see Power1 Register). DAC outputs OUT1
and OUT2 go high impedance when powered down.
The DACs are automatically powered up and ready for
a conversion when Idle or Run mode is entered.
Voltage Monitors
The MAX1407/MAX1408/MAX1409/MAX1414 include
two on-board voltage monitors. When AVDDis below
the RESETtrip threshold, RESETgoes low and the RST
bit of the Status register is set to “1”. When AVDD is
below the Low VDDtrip threshold, the LVD bit of the
Status register is set to 1.
RESETVoltage Monitor
The RESETvoltage monitor is powered up at all times
(provided that VM = 0 and LVDE = 1 or VM = 1 and
LSDE = 1). A threshold voltage of either +1.8V or +2.7V
may be selected for the RESETvoltage monitor (see
Power2 Register). At initial power-up, the RESETtrip
threshold is set to 2.7V. If the RESETvoltage monitor is
tripped, the RST bit of the status register is set to “1”
and RESETgoes low. RESETis held low for 1.54
seconds (typ) after AVDDrises above the RESETvoltage
monitor threshold. If AVDDis no longer below the RESET
threshold, reading the Status register will clear RST.
Low VDDVoltage Monitor
When the device is operating in Run, Idle, or Standby
mode (see Power Modes) and AVDDgoes below +2.7V,
the low VDDmonitor trips, indicating that the supply volt-
age is below the safe minimum for proper operation.
When tripped, the Low VDDVoltage Monitor sets the LVD
bit of the Status register to 1. If AVDDis no longer below
+2.7V, reading the Status register will clear LVD. The low
VDDmonitor is powered down in Sleep mode. When it is
powered down, the LVD bit stays unchanged. The LVD is
cleared if it is read in Sleep mode.
Figure 7. Frequency Response of the SINC3Filter (Notch at
60Hz)
FREQUENCY (Hz)
GAIN (dB)
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Internal/External Reference
The MAX1407/MAX1408/MAX1409/MAX1414 have an
internal low-drift +1.25V reference used for both ADC
and DAC conversion. The buffered reference output
can be used as a reference source for other devices in
the system. The internal reference requires a 4.7µF low-
ESR ceramic capacitor or tantalum capacitor connect-
ed between REF and AGND. For applications that
require increased accuracy, power-down the internal
reference by writing a 0 to the REFE bit of the Power1
register and connect an external reference source to
REF. The valid external reference voltage range is
1.25V ±100mV.
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) connected between CLKIN and CLKOUT
with an operating frequency of 32.768kHz. This oscilla-
tor is used for the RTC, alarm, signal-detect compara-
tor, and PLL. The oscillator is operational down to 1.8V.
In any crystal-based oscillator circuit, the oscillator fre-
quency is based on the characteristics of the crystal. It
is important to select a crystal that meets the design
requirements, especially the capacitive load (CL) that
must be placed across the crystal pins in order for the
crystal to oscillate at its specified frequency. CLis the
capacitance that the crystal needs to “see” from the
oscillator circuit; it is not the capacitance of the crystal
itself. The MAX1407/MAX1408/MAX1409/MAX1414
have 6pF of capacitance across the CLKIN and CLK-
OUT pins. Choose a crystal with a 32.768kHz oscillation
frequency and a 6pF capacitive load such as the C-
002RX32-E from Epson Crystal. Using a crystal with athat is larger than the load capacitance of the oscil-
lator circuit will cause the oscillator to run faster than
the specified nominal frequency of the crystal.
Conversely, using a crystal with a CLthat is smaller
than the load capacitance of the oscillator circuit will
cause the oscillator to run slower than the specified
nominal frequency of the crystal.
Phase-Locked Loop (PLL) and FOUT
An on-board phase-locked loop generates a
2.4576MHz clock at FOUT from the 32.768kHz crystal
oscillator. FOUT can be used to clock a µP or other dig-
ital circuitry. Connect an 18nF ceramic capacitor from
CPLL to AVDDto create the 2.4576MHz clock signal at
FOUT. To power down the PLL, clear PLLE in the
Power2 register (see Power2 Register) or write to the
Sleep register. FOUT will be active for 1.95ms (tDFOF)
after receiving either power-down command and then
go low. This provides extra clock signals to the µP to
complete a shutdown sequence. The PLL is active in all
modes except the sleep mode (see Power Modes). To
reactivate the PLL, the following conditions must be
met: AVDDis greater than the low VDDvoltage monitor
threshold, RESETis deasserted, and the PLLE bit is
equal to “1”. FOUT is enabled 31.25ms (tDFON) after
the PLL is activated. At initial power-up, the PLL is
enabled. If RESETis asserted while the PLL is running,
the PLL does not shut down.
Real-Time Clock (RTC)
The integrated RTC provides the current second,
minute, hour, date, month, day, year, century, and mil-
lenium information. An internally generated reference
clock of 1.024kHz (derived from the 32.768kHz crystal)
drives the RTC. The RTC operates in either 24-hour or
12-hour format with an AM/PM indicator (see RTC_Hour
Register). An internal calendar compensates for months
with less than 31 days and includes leap year correc-
tion through the year 9999. The RTC operates from a
supply voltage of +1.8V to +3.6V and consumes less
than 1µA current.
Time of Day Alarm
The MAX1407/MAX1408/MAX1409/MAX1414 offer a time
of day alarm which generates an interrupt when the RTC
reaches a preset combination of seconds, minutes,
hours, and day (see Alarm Registers). In addition to set-
ting a “single-shot” alarm, the Time of Day Alarm can
also be programmed to generate an alarm every sec-
ond, minute, hour, day, or week. “Don’t care” states can
be inserted into one or more fields if it is desired for them
to be ignored for the alarm condition. The Time of Day
Alarm wakes up the device into Standby mode if it is in
Sleep mode. The Time of Day Alarm operates from a
supply voltage of +1.8V to +3.6V.
Interrupt (IINNTT)
INTindicates one of three conditions. After receiving a
valid interrupt (INTgoes low), read the Status register
and the Al_Status register (if the alarm is enabled) to
identify the source of the interrupt. The three sources of
interrupts are from the CLK, SDC, and ALIRQ bits.
PLL Ready
On power-up, INTis high. 7.82ms (tDFI) after the PLL
output appears on FOUT, INTgoes low (see Figure 15).
The CLK bit of the Status register is set to “1” after
FOUT is enabled. Reading the Status register clears the
CLK bit. INT remains low until the device detects a start
bit through the serial interface from the µP. The purpose
of this interrupt is to inform the µP that the FOUT clock
signal is present.
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
Signal Detect
The INTpin will also go low and stay low when the dif-
ferential voltage on the selected analog inputs exceeds
the signal-detect comparator trip threshold (0mV for the
MAX1407/MAX1408/MAX1409 and 50mV for the
MAX1414). This will latch the SDC bit of the Status reg-
ister to one. Additional signal detect interrupts cannot
be generated unless the SDC bit is cleared. To clear
the SDC bit, the Status register must be read and the
input must be below the signal-detect threshold.
Powering down the signal detect-comparator without
reading the Status register will also clear the SDC bit.
Similar to the power-up case, INTgoes high when the
device detects a start bit through the serial interface
from the µP.
Time of Day Alarm
If the device is in Sleep mode, the alarm will wake up
the device and set the ALIRQ bit. INTis asserted when
the PLL is turned on. If an alarm occurs while the
device is awake (BIASE = 1), the ALIRQ bit will be set
and INTwill go low. INTremains low until the device
detects a start bit through the serial interface from the
µP. ALIRQ is reset to 0 when any alarm register is read
or written to.
Shutdown (SSHHDDNN)
SHDNis an active-low output that can be used to con-
trol an external power supply. Powering up the PLL
(PLLE = 1) or writing a “1” to the SHDEbit of the
Power2 register causes SHDNto go high. SHDNgoes
low when the SHDEbit is set to 0 only if the PLL is pow-
ered down (PLLE = 0). The SHDNoutput stays high for
2.93ms (tDPD) after receiving a power-down command,
allowing the external power supply to stay alive so that
the µP can properly complete a shutdown sequence.
SHDNis not available on the MAX1409. Note:Entering
Sleep mode automatically sets PLLE and SHDEto 0.
Any wake-up event will cause SHDN to go high. (See
Wake-Up section.)
Data Ready (DDRRDDYY)
This pin will go low and stay low upon completion of an
ADC conversion or end of an ADC calibration. This sig-
nals the µP that a valid conversion or calibration result
has been written to the DATA or the OFFSET register.
The DRDYpin goes high either when the µP has fin-
ished reading the conversion/calibration result on the
last rising edge of SCLK (see Figure 8), or when the
next conversion result is about to be written to the
DATA register. When no read operation is performed,
DRDYpulses at 60Hz with a pulse high time of
162.76µs (or 30Hz with a pulse high time of 325.52µs)
DRDYis not available on the MAX1409. To see when
the ADC has completed a normal conversion or a cali-
bration conversion for the MAX1409, check the status
of the ADD bit in the Status register.
Serial Digital Interface
The SPI/QSPI/MICROWIRE-serial interface consists of
chip select (CS), serial clock (SCLK), data in (DIN), and
data out (DOUT) (See Figure 9). The serial interface
provides access to 29 on-chip registers, allowing con-
trol to all the power modes and functional blocks,
including the ADCs, DACs, and RTC. Table 2 lists the
address and read/write accessibility of all the registers.
A logic high on CSthree-states DOUT and causes the
MAX1407/MAX1408/MAX1409/MAX1414 to ignore any
signals on SCLK and DIN. To clock data into or out of
the internal shift register, drive CSlow. SCLK synchro-
nizes the data transfer. The rising edge of SCLK clocks
DIN into the shift register, and the falling edge of SCLK
Figure 8. ADC Conversion Timing Diagram
SCLK
DIN
DOUT0A4A3A2A1A0x11A4A3A2A1A0xD6D5D4D3D2D1D0D8D9D15D14D13D12D11D10
DRDYD6D5D4D3D2D1D0
ADC
CONV
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
clocks DOUT out of the shift register. DIN and DOUT are
transferred as MSB first (data is left justified). Figure 10
shows detailed serial interface timing.
All communication with the MAX1407/MAX1408/
MAX1409/MAX1414 begins with a command byte on
DIN, where the first logic 1 on DIN will be recognized as
the START bit (MSB) for the command byte (Table 3).
The following seven clock cycles load the command into
a shift register. These seven bits specify which of the
registers will be accessed, whether a read or write oper-
ation will take place, and the length of the subsequent
data (0-bit, 8-bit, 16-bit, or burst mode). Idle DIN low
between writes to the MAX1407/MAX1408/MAX1409/
MAX1414. Figures 11–14 show the read and write timing
for 8- and 16-bit data. Data is updated on the last rising
edge of the SCLK in the command word. CSshould not
go high between data transfers. If CSis toggled before
the end of a write or read operation, the device can
enter an incorrect mode. Clock in 72 zeros to clear this
state and re-arm the serial interface.
After loading the command byte into the shift register,
additional clocks shift out data on DOUT for a read and
shift in data on DIN for a write operation.
Figure 9. SPI/QSPI Interface Connections
MAX1407
MAX1408
MAX1409
MAX1414
DRDY NOT AVAILABLE ON MAX1409
RESET
CLKIN
CLKOUT
FOUT
SCLK
DIN
DOUT
INT
DRDY
RESET
CLKIN
OUTPUT
SCK
MOSI
MISO
INPUT
INPUT
μP/μC
WU2I/O
32.768kHz
WU1I/O
Figure 10. Detailed Serial Interface Timing
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSHtCL
tDS
tDH
tDV
tCHtCYC
tDOtTR
tCSHtCSS
MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTCallows the SCLK, DIN, and DOUT signals to be
shared among several devices. When short on proces-
sor I/O pins, connect CSto DGND, and operate the seri-
al digital interface in CPOL = 1, CPHA = 1 or CPOL = 0,
CPHA = 0 modes using SCLK, DIN, and DOUT.
SCLK
DIN
DOUT0A4A3A2A1D7D6D5D4D3D2D1D0D8D9A0xD15D14D13D12D11D10
Figure 11. Serial Interface 16-Bit Write Timing Diagram
SCLK
DIN
DOUT0A4A3A2A1D7D6D5D4D3D2D1D0A0x
Figure 12. Serial Interface 8-Bit Write Timing Diagram
SCLK
DIN
DOUT1A4A3A2A1A0xD6D5D4D3D2D1D0D8D9D15D14D13D12D11D10
Figure 13. Serial Interface 16-Bit Read Timing Diagram
